Skip to content

K
kawamura-solver
Commit 940a7e2c authored by kazushi.kawamura's avatar kazushi.kawamura
Browse files
Options

upload hardware design

parent 0d5842fb
Show whitespace changes
Inline Side-by-side
Showing with 6457 additions and 0 deletions
hardware_design/190826_solver/design_1.hwh 0 → 100755
View file @ 940a7e2c
This source diff could not be displayed because it is too large. You can view the blob instead.
hardware_design/for_pynq_design/led_pin_assignment.xdc 0 → 100755
View file @ 940a7e2c
set_property PACKAGE_PIN R14 [get_ports {led[0]}]
set_property PACKAGE_PIN P14 [get_ports {led[1]}]
set_property PACKAGE_PIN N16 [get_ports {led[2]}]
set_property PACKAGE_PIN M14 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
hardware_design/for_pynq_design/pynq_revC.tcl 0 → 100755
View file @ 940a7e2c
proc getPresetInfo {} {
return [dict create name {PYNQ} description {PYNQ} vlnv xilinx.com:ip:processing_system7:5.5 display_name {PYNQ} ]
}
proc validate_preset {IPINST} { return true }
proc apply_preset {IPINST} {
return [dict create \
CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
CONFIG.PCW_FCLK_CLK0_BUF {true} \
CONFIG.PCW_FCLK_CLK1_BUF {false} \
CONFIG.PCW_FCLK_CLK2_BUF {false} \
CONFIG.PCW_FCLK_CLK3_BUF {false} \
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
CONFIG.PCW_UIPARAM_DDR_CL {7} \
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
CONFIG.PCW_UIPARAM_DDR_AL {0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \
CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \
CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \
CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \
CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \
CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \
CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \
CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {50.000000} \
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {50.000000} \
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {50.000000} \
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
CONFIG.PCW_CLK0_FREQ {100000000} \
CONFIG.PCW_CLK1_FREQ {50000000} \
CONFIG.PCW_CLK2_FREQ {50000000} \
CONFIG.PCW_CLK3_FREQ {50000000} \
CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {20} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {20} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {20} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \
CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \
CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
CONFIG.PCW_EN_EMIO_CAN0 {0} \
CONFIG.PCW_EN_EMIO_CAN1 {0} \
CONFIG.PCW_EN_EMIO_ENET0 {0} \
CONFIG.PCW_EN_EMIO_ENET1 {0} \
CONFIG.PCW_EN_PTP_ENET0 {0} \
CONFIG.PCW_EN_PTP_ENET1 {0} \
CONFIG.PCW_EN_EMIO_GPIO {0} \
CONFIG.PCW_EN_EMIO_I2C0 {0} \
CONFIG.PCW_EN_EMIO_I2C1 {0} \
CONFIG.PCW_EN_EMIO_PJTAG {0} \
CONFIG.PCW_EN_EMIO_SDIO0 {0} \
CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
CONFIG.PCW_EN_EMIO_SDIO1 {0} \
CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
CONFIG.PCW_EN_EMIO_SPI0 {0} \
CONFIG.PCW_EN_EMIO_SPI1 {0} \
CONFIG.PCW_EN_EMIO_UART0 {0} \
CONFIG.PCW_EN_EMIO_UART1 {0} \
CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
CONFIG.PCW_EN_EMIO_TTC0 {0} \
CONFIG.PCW_EN_EMIO_TTC1 {0} \
CONFIG.PCW_EN_EMIO_WDT {0} \
CONFIG.PCW_EN_EMIO_TRACE {0} \
CONFIG.PCW_USE_AXI_NONSECURE {0} \
CONFIG.PCW_USE_M_AXI_GP0 {0} \
CONFIG.PCW_USE_M_AXI_GP1 {0} \
CONFIG.PCW_USE_S_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_GP1 {0} \
CONFIG.PCW_USE_S_AXI_ACP {0} \
CONFIG.PCW_USE_S_AXI_HP0 {0} \
CONFIG.PCW_USE_S_AXI_HP1 {0} \
CONFIG.PCW_USE_S_AXI_HP2 {0} \
CONFIG.PCW_USE_S_AXI_HP3 {0} \
CONFIG.PCW_M_AXI_GP0_FREQMHZ {10} \
CONFIG.PCW_M_AXI_GP1_FREQMHZ {10} \
CONFIG.PCW_S_AXI_GP0_FREQMHZ {10} \
CONFIG.PCW_S_AXI_GP1_FREQMHZ {10} \
CONFIG.PCW_S_AXI_ACP_FREQMHZ {10} \
CONFIG.PCW_S_AXI_HP0_FREQMHZ {10} \
CONFIG.PCW_S_AXI_HP1_FREQMHZ {10} \
CONFIG.PCW_S_AXI_HP2_FREQMHZ {10} \
CONFIG.PCW_S_AXI_HP3_FREQMHZ {10} \
CONFIG.PCW_USE_DMA0 {0} \
CONFIG.PCW_USE_DMA1 {0} \
CONFIG.PCW_USE_DMA2 {0} \
CONFIG.PCW_USE_DMA3 {0} \
CONFIG.PCW_USE_TRACE {0} \
CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
CONFIG.PCW_USE_CROSS_TRIGGER {0} \
CONFIG.PCW_FTM_CTI_IN0 {<Select>} \
CONFIG.PCW_FTM_CTI_IN1 {<Select>} \
CONFIG.PCW_FTM_CTI_IN2 {<Select>} \
CONFIG.PCW_FTM_CTI_IN3 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT0 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT1 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT2 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT3 {<Select>} \
CONFIG.PCW_USE_DEBUG {0} \
CONFIG.PCW_USE_CR_FABRIC {1} \
CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
CONFIG.PCW_USE_DDR_BYPASS {0} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
CONFIG.PCW_USE_EXPANDED_IOP {0} \
CONFIG.PCW_USE_HIGH_OCM {0} \
CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
CONFIG.PCW_USE_CORESIGHT {0} \
CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
CONFIG.PCW_UART0_BAUD_RATE {115200} \
CONFIG.PCW_UART1_BAUD_RATE {115200} \
CONFIG.PCW_EN_4K_TIMER {0} \
CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
CONFIG.PCW_EN_DDR {1} \
CONFIG.PCW_EN_SMC {0} \
CONFIG.PCW_EN_QSPI {1} \
CONFIG.PCW_EN_CAN0 {0} \
CONFIG.PCW_EN_CAN1 {0} \
CONFIG.PCW_EN_ENET0 {1} \
CONFIG.PCW_EN_ENET1 {0} \
CONFIG.PCW_EN_GPIO {1} \
CONFIG.PCW_EN_I2C0 {0} \
CONFIG.PCW_EN_I2C1 {0} \
CONFIG.PCW_EN_PJTAG {0} \
CONFIG.PCW_EN_SDIO0 {1} \
CONFIG.PCW_EN_SDIO1 {0} \
CONFIG.PCW_EN_SPI0 {0} \
CONFIG.PCW_EN_SPI1 {0} \
CONFIG.PCW_EN_UART0 {1} \
CONFIG.PCW_EN_UART1 {0} \
CONFIG.PCW_EN_MODEM_UART0 {0} \
CONFIG.PCW_EN_MODEM_UART1 {0} \
CONFIG.PCW_EN_TTC0 {0} \
CONFIG.PCW_EN_TTC1 {0} \
CONFIG.PCW_EN_WDT {0} \
CONFIG.PCW_EN_TRACE {0} \
CONFIG.PCW_EN_USB0 {1} \
CONFIG.PCW_EN_USB1 {0} \
CONFIG.PCW_DQ_WIDTH {32} \
CONFIG.PCW_DQS_WIDTH {4} \
CONFIG.PCW_DM_WIDTH {4} \
CONFIG.PCW_MIO_PRIMITIVE {54} \
CONFIG.PCW_EN_CLK0_PORT {1} \
CONFIG.PCW_EN_CLK1_PORT {0} \
CONFIG.PCW_EN_CLK2_PORT {0} \
CONFIG.PCW_EN_CLK3_PORT {0} \
CONFIG.PCW_EN_RST0_PORT {1} \
CONFIG.PCW_EN_RST1_PORT {0} \
CONFIG.PCW_EN_RST2_PORT {0} \
CONFIG.PCW_EN_RST3_PORT {0} \
CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
CONFIG.PCW_P2F_DMAC0_INTR {0} \
CONFIG.PCW_P2F_DMAC1_INTR {0} \
CONFIG.PCW_P2F_DMAC2_INTR {0} \
CONFIG.PCW_P2F_DMAC3_INTR {0} \
CONFIG.PCW_P2F_DMAC4_INTR {0} \
CONFIG.PCW_P2F_DMAC5_INTR {0} \
CONFIG.PCW_P2F_DMAC6_INTR {0} \
CONFIG.PCW_P2F_DMAC7_INTR {0} \
CONFIG.PCW_P2F_SMC_INTR {0} \
CONFIG.PCW_P2F_QSPI_INTR {0} \
CONFIG.PCW_P2F_CTI_INTR {0} \
CONFIG.PCW_P2F_GPIO_INTR {0} \
CONFIG.PCW_P2F_USB0_INTR {0} \
CONFIG.PCW_P2F_ENET0_INTR {0} \
CONFIG.PCW_P2F_SDIO0_INTR {0} \
CONFIG.PCW_P2F_I2C0_INTR {0} \
CONFIG.PCW_P2F_SPI0_INTR {0} \
CONFIG.PCW_P2F_UART0_INTR {0} \
CONFIG.PCW_P2F_CAN0_INTR {0} \
CONFIG.PCW_P2F_USB1_INTR {0} \
CONFIG.PCW_P2F_ENET1_INTR {0} \
CONFIG.PCW_P2F_SDIO1_INTR {0} \
CONFIG.PCW_P2F_I2C1_INTR {0} \
CONFIG.PCW_P2F_SPI1_INTR {0} \
CONFIG.PCW_P2F_UART1_INTR {0} \
CONFIG.PCW_P2F_CAN1_INTR {0} \
CONFIG.PCW_IRQ_F2P_INTR {0} \
CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
CONFIG.PCW_CORE0_FIQ_INTR {0} \
CONFIG.PCW_CORE0_IRQ_INTR {0} \
CONFIG.PCW_CORE1_FIQ_INTR {0} \
CONFIG.PCW_CORE1_IRQ_INTR {0} \
CONFIG.PCW_VALUE_SILVERSION {3} \
CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
CONFIG.PCW_UIPARAM_DDR_BL {8} \
CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {<Select>} \
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {<Select>} \
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {<Select>} \
CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {<Select>} \
CONFIG.PCW_DDR_PRIORITY_READPORT_0 {<Select>} \
CONFIG.PCW_DDR_PRIORITY_READPORT_1 {<Select>} \
CONFIG.PCW_DDR_PRIORITY_READPORT_2 {<Select>} \
CONFIG.PCW_DDR_PRIORITY_READPORT_3 {<Select>} \
CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_NAND_NAND_IO {<Select>} \
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
CONFIG.PCW_NAND_GRP_D8_IO {<Select>} \
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_NOR_NOR_IO {<Select>} \
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
CONFIG.PCW_NOR_GRP_A25_IO {<Select>} \
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
CONFIG.PCW_NOR_GRP_CS0_IO {<Select>} \
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {<Select>} \
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
CONFIG.PCW_NOR_GRP_CS1_IO {<Select>} \
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {<Select>} \
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
CONFIG.PCW_NOR_GRP_SRAM_INT_IO {<Select>} \
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
CONFIG.PCW_QSPI_GRP_SS1_IO {<Select>} \
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
CONFIG.PCW_QSPI_GRP_IO1_IO {<Select>} \
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
CONFIG.PCW_ENET_RESET_ENABLE {1} \
CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
CONFIG.PCW_ENET0_RESET_ENABLE {1} \
CONFIG.PCW_ENET0_RESET_IO {MIO 9} \
CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_ENET1_ENET1_IO {<Select>} \
CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
CONFIG.PCW_ENET1_GRP_MDIO_IO {<Select>} \
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
CONFIG.PCW_ENET1_RESET_IO {<Select>} \
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
CONFIG.PCW_SD0_GRP_WP_IO {<Select>} \
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
CONFIG.PCW_SD0_GRP_POW_IO {<Select>} \
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_SD1_SD1_IO {<Select>} \
CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
CONFIG.PCW_SD1_GRP_CD_IO {<Select>} \
CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
CONFIG.PCW_SD1_GRP_WP_IO {<Select>} \
CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
CONFIG.PCW_SD1_GRP_POW_IO {<Select>} \
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
CONFIG.PCW_UART0_GRP_FULL_IO {<Select>} \
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_UART1_UART1_IO {<Select>} \
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
CONFIG.PCW_UART1_GRP_FULL_IO {<Select>} \
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_SPI0_SPI0_IO {<Select>} \
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
CONFIG.PCW_SPI0_GRP_SS0_IO {<Select>} \
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
CONFIG.PCW_SPI0_GRP_SS1_IO {<Select>} \
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
CONFIG.PCW_SPI0_GRP_SS2_IO {<Select>} \
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_SPI1_SPI1_IO {<Select>} \
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
CONFIG.PCW_SPI1_GRP_SS0_IO {<Select>} \
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
CONFIG.PCW_SPI1_GRP_SS1_IO {<Select>} \
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
CONFIG.PCW_SPI1_GRP_SS2_IO {<Select>} \
CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_CAN0_CAN0_IO {<Select>} \
CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
CONFIG.PCW_CAN0_GRP_CLK_IO {<Select>} \
CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_CAN1_CAN1_IO {<Select>} \
CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
CONFIG.PCW_CAN1_GRP_CLK_IO {<Select>} \
CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_TRACE_TRACE_IO {<Select>} \
CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_2BIT_IO {<Select>} \
CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_4BIT_IO {<Select>} \
CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_8BIT_IO {<Select>} \
CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_16BIT_IO {<Select>} \
CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_32BIT_IO {<Select>} \
CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_WDT_WDT_IO {<Select>} \
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_TTC0_TTC0_IO {<Select>} \
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_TTC1_TTC1_IO {<Select>} \
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
CONFIG.PCW_USB_RESET_ENABLE {1} \
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
CONFIG.PCW_USB0_RESET_ENABLE {1} \
CONFIG.PCW_USB0_RESET_IO {MIO 46} \
CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_USB1_USB1_IO {<Select>} \
CONFIG.PCW_USB1_RESET_ENABLE {0} \
CONFIG.PCW_USB1_RESET_IO {<Select>} \
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_I2C0_I2C0_IO {<Select>} \
CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
CONFIG.PCW_I2C0_GRP_INT_IO {<Select>} \
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
CONFIG.PCW_I2C0_RESET_IO {<Select>} \
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
CONFIG.PCW_I2C1_GRP_INT_IO {<Select>} \
CONFIG.PCW_I2C_RESET_ENABLE {1} \
CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
CONFIG.PCW_I2C1_RESET_IO {<Select>} \
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>} \
CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
CONFIG.PCW_MIO_0_PULLUP {enabled} \
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_0_DIRECTION {inout} \
CONFIG.PCW_MIO_0_SLEW {slow} \
CONFIG.PCW_MIO_1_PULLUP {enabled} \
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_1_DIRECTION {out} \
CONFIG.PCW_MIO_1_SLEW {slow} \
CONFIG.PCW_MIO_2_PULLUP {disabled} \
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_2_DIRECTION {inout} \
CONFIG.PCW_MIO_2_SLEW {slow} \
CONFIG.PCW_MIO_3_PULLUP {disabled} \
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_3_DIRECTION {inout} \
CONFIG.PCW_MIO_3_SLEW {slow} \
CONFIG.PCW_MIO_4_PULLUP {disabled} \
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_4_DIRECTION {inout} \
CONFIG.PCW_MIO_4_SLEW {slow} \
CONFIG.PCW_MIO_5_PULLUP {disabled} \
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_5_DIRECTION {inout} \
CONFIG.PCW_MIO_5_SLEW {slow} \
CONFIG.PCW_MIO_6_PULLUP {disabled} \
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_6_DIRECTION {out} \
CONFIG.PCW_MIO_6_SLEW {slow} \
CONFIG.PCW_MIO_7_PULLUP {disabled} \
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_7_DIRECTION {out} \
CONFIG.PCW_MIO_7_SLEW {slow} \
CONFIG.PCW_MIO_8_PULLUP {disabled} \
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_8_DIRECTION {out} \
CONFIG.PCW_MIO_8_SLEW {slow} \
CONFIG.PCW_MIO_9_PULLUP {enabled} \
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_9_DIRECTION {out} \
CONFIG.PCW_MIO_9_SLEW {slow} \
CONFIG.PCW_MIO_10_PULLUP {enabled} \
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_10_DIRECTION {inout} \
CONFIG.PCW_MIO_10_SLEW {slow} \
CONFIG.PCW_MIO_11_PULLUP {enabled} \
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_11_DIRECTION {inout} \
CONFIG.PCW_MIO_11_SLEW {slow} \
CONFIG.PCW_MIO_12_PULLUP {enabled} \
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_12_DIRECTION {inout} \
CONFIG.PCW_MIO_12_SLEW {slow} \
CONFIG.PCW_MIO_13_PULLUP {enabled} \
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_13_DIRECTION {inout} \
CONFIG.PCW_MIO_13_SLEW {slow} \
CONFIG.PCW_MIO_14_PULLUP {enabled} \
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_14_DIRECTION {in} \
CONFIG.PCW_MIO_14_SLEW {slow} \
CONFIG.PCW_MIO_15_PULLUP {enabled} \
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_15_DIRECTION {out} \
CONFIG.PCW_MIO_15_SLEW {slow} \
CONFIG.PCW_MIO_16_PULLUP {enabled} \
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_16_DIRECTION {out} \
CONFIG.PCW_MIO_16_SLEW {slow} \
CONFIG.PCW_MIO_17_PULLUP {enabled} \
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_17_DIRECTION {out} \
CONFIG.PCW_MIO_17_SLEW {slow} \
CONFIG.PCW_MIO_18_PULLUP {enabled} \
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_18_DIRECTION {out} \
CONFIG.PCW_MIO_18_SLEW {slow} \
CONFIG.PCW_MIO_19_PULLUP {enabled} \
CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_19_DIRECTION {out} \
CONFIG.PCW_MIO_19_SLEW {slow} \
CONFIG.PCW_MIO_20_PULLUP {enabled} \
CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_20_DIRECTION {out} \
CONFIG.PCW_MIO_20_SLEW {slow} \
CONFIG.PCW_MIO_21_PULLUP {enabled} \
CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_21_DIRECTION {out} \
CONFIG.PCW_MIO_21_SLEW {slow} \
CONFIG.PCW_MIO_22_PULLUP {enabled} \
CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_22_DIRECTION {in} \
CONFIG.PCW_MIO_22_SLEW {slow} \
CONFIG.PCW_MIO_23_PULLUP {enabled} \
CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_23_DIRECTION {in} \
CONFIG.PCW_MIO_23_SLEW {slow} \
CONFIG.PCW_MIO_24_PULLUP {enabled} \
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_24_DIRECTION {in} \
CONFIG.PCW_MIO_24_SLEW {slow} \
CONFIG.PCW_MIO_25_PULLUP {enabled} \
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_25_DIRECTION {in} \
CONFIG.PCW_MIO_25_SLEW {slow} \
CONFIG.PCW_MIO_26_PULLUP {enabled} \
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_26_DIRECTION {in} \
CONFIG.PCW_MIO_26_SLEW {slow} \
CONFIG.PCW_MIO_27_PULLUP {enabled} \
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_27_DIRECTION {in} \
CONFIG.PCW_MIO_27_SLEW {slow} \
CONFIG.PCW_MIO_28_PULLUP {enabled} \
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_28_DIRECTION {inout} \
CONFIG.PCW_MIO_28_SLEW {slow} \
CONFIG.PCW_MIO_29_PULLUP {enabled} \
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_29_DIRECTION {in} \
CONFIG.PCW_MIO_29_SLEW {slow} \
CONFIG.PCW_MIO_30_PULLUP {enabled} \
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_30_DIRECTION {out} \
CONFIG.PCW_MIO_30_SLEW {slow} \
CONFIG.PCW_MIO_31_PULLUP {enabled} \
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_31_DIRECTION {in} \
CONFIG.PCW_MIO_31_SLEW {slow} \
CONFIG.PCW_MIO_32_PULLUP {enabled} \
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_32_DIRECTION {inout} \
CONFIG.PCW_MIO_32_SLEW {slow} \
CONFIG.PCW_MIO_33_PULLUP {enabled} \
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_33_DIRECTION {inout} \
CONFIG.PCW_MIO_33_SLEW {slow} \
CONFIG.PCW_MIO_34_PULLUP {enabled} \
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_34_DIRECTION {inout} \
CONFIG.PCW_MIO_34_SLEW {slow} \
CONFIG.PCW_MIO_35_PULLUP {enabled} \
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_35_DIRECTION {inout} \
CONFIG.PCW_MIO_35_SLEW {slow} \
CONFIG.PCW_MIO_36_PULLUP {enabled} \
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_36_DIRECTION {in} \
CONFIG.PCW_MIO_36_SLEW {slow} \
CONFIG.PCW_MIO_37_PULLUP {enabled} \
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_37_DIRECTION {inout} \
CONFIG.PCW_MIO_37_SLEW {slow} \
CONFIG.PCW_MIO_38_PULLUP {enabled} \
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_38_DIRECTION {inout} \
CONFIG.PCW_MIO_38_SLEW {slow} \
CONFIG.PCW_MIO_39_PULLUP {enabled} \
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_39_DIRECTION {inout} \
CONFIG.PCW_MIO_39_SLEW {slow} \
CONFIG.PCW_MIO_40_PULLUP {enabled} \
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_40_DIRECTION {inout} \
CONFIG.PCW_MIO_40_SLEW {slow} \
CONFIG.PCW_MIO_41_PULLUP {enabled} \
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_41_DIRECTION {inout} \
CONFIG.PCW_MIO_41_SLEW {slow} \
CONFIG.PCW_MIO_42_PULLUP {enabled} \
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_42_DIRECTION {inout} \
CONFIG.PCW_MIO_42_SLEW {slow} \
CONFIG.PCW_MIO_43_PULLUP {enabled} \
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_43_DIRECTION {inout} \
CONFIG.PCW_MIO_43_SLEW {slow} \
CONFIG.PCW_MIO_44_PULLUP {enabled} \
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_44_DIRECTION {inout} \
CONFIG.PCW_MIO_44_SLEW {slow} \
CONFIG.PCW_MIO_45_PULLUP {enabled} \
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_45_DIRECTION {inout} \
CONFIG.PCW_MIO_45_SLEW {slow} \
CONFIG.PCW_MIO_46_PULLUP {enabled} \
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_46_DIRECTION {out} \
CONFIG.PCW_MIO_46_SLEW {slow} \
CONFIG.PCW_MIO_47_PULLUP {enabled} \
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_47_DIRECTION {in} \
CONFIG.PCW_MIO_47_SLEW {slow} \
CONFIG.PCW_MIO_48_PULLUP {enabled} \
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_48_DIRECTION {inout} \
CONFIG.PCW_MIO_48_SLEW {slow} \
CONFIG.PCW_MIO_49_PULLUP {enabled} \
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_49_DIRECTION {inout} \
CONFIG.PCW_MIO_49_SLEW {slow} \
CONFIG.PCW_MIO_50_PULLUP {enabled} \
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_50_DIRECTION {inout} \
CONFIG.PCW_MIO_50_SLEW {slow} \
CONFIG.PCW_MIO_51_PULLUP {enabled} \
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_51_DIRECTION {inout} \
CONFIG.PCW_MIO_51_SLEW {slow} \
CONFIG.PCW_MIO_52_PULLUP {enabled} \
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_52_DIRECTION {out} \
CONFIG.PCW_MIO_52_SLEW {slow} \
CONFIG.PCW_MIO_53_PULLUP {enabled} \
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_53_DIRECTION {inout} \
CONFIG.PCW_MIO_53_SLEW {slow} \
CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \
CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
CONFIG.PCW_NOR_CS0_T_TR {1} \
CONFIG.PCW_NOR_CS0_T_PC {1} \
CONFIG.PCW_NOR_CS0_T_WP {1} \
CONFIG.PCW_NOR_CS0_T_CEOE {1} \
CONFIG.PCW_NOR_CS0_T_WC {11} \
CONFIG.PCW_NOR_CS0_T_RC {11} \
CONFIG.PCW_NOR_CS0_WE_TIME {0} \
CONFIG.PCW_NOR_CS1_T_TR {1} \
CONFIG.PCW_NOR_CS1_T_PC {1} \
CONFIG.PCW_NOR_CS1_T_WP {1} \
CONFIG.PCW_NOR_CS1_T_CEOE {1} \
CONFIG.PCW_NOR_CS1_T_WC {11} \
CONFIG.PCW_NOR_CS1_T_RC {11} \
CONFIG.PCW_NOR_CS1_WE_TIME {0} \
CONFIG.PCW_NAND_CYCLES_T_RR {1} \
CONFIG.PCW_NAND_CYCLES_T_AR {1} \
CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
CONFIG.PCW_NAND_CYCLES_T_WP {1} \
CONFIG.PCW_NAND_CYCLES_T_REA {1} \
CONFIG.PCW_NAND_CYCLES_T_WC {11} \
CONFIG.PCW_NAND_CYCLES_T_RC {11} \
CONFIG.PCW_SMC_CYCLE_T0 {NA} \
CONFIG.PCW_SMC_CYCLE_T1 {NA} \
CONFIG.PCW_SMC_CYCLE_T2 {NA} \
CONFIG.PCW_SMC_CYCLE_T3 {NA} \
CONFIG.PCW_SMC_CYCLE_T4 {NA} \
CONFIG.PCW_SMC_CYCLE_T5 {NA} \
CONFIG.PCW_SMC_CYCLE_T6 {NA} \
CONFIG.PCW_PACKAGE_NAME {clg400} \
CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
]
}
hardware_design/source_code/param.hpp 0 → 100755
View file @ 940a7e2c
#ifndef __PARAM_HPP__
#define __PARAM_HPP__
#define MAX_BLOCKS 128
#define MAX_LINES 256
#define MAX_PATH 128
#define MAX_CELLS 16384 // 128x128
#define MAX_SIZE 128
#define MAX_SIZE_BIT 7
#define SLOT_MAX_SIZE 64
#define ROUND_LIMIT 4096 //32768 // Max=65534(=2^16-2)
//#define PRINT_BOARD
//#define PRINT_SEARCH // for router debug
#define PQ_BIT 12
#define MAX_PQ 4096
#define PRIO_BIT 16
#define DATA_BIT 16
#define ELEM_BIT 32 // ELEM_BIT = PRIO_BIT + DATA_BIT
#define DATA_MASK 65535 // 0000 FFFF
#define DATA_MAX 65535 // FFFF
#define PRIO_MAX 65535 // FFFF
#define LE 1
#define TO 2
#define RI 3
#define BO 4
#define SA_O 1000
#define SA_I 100000
#define TEMP_S 500
#define TEMP_E 0.1
#define INTER_BLOCK_MARGIN 2
#define LOOP 50
#define TRY_LIMIT 500
#define NO_MOVE 10
#define LFSR_RAND_MAX 4294967295
#endif /* __PARAM_HPP__ */
hardware_design/source_code/solver.cpp 0 → 100755
View file @ 940a7e2c
#include "solver.hpp"
static unsigned int lfsr, lfsr_x, lfsr_y;
static void lfsr_random_init(unsigned int seed, unsigned int seed_x, unsigned int seed_y) {
#pragma HLS INLINE
lfsr = seed;
lfsr_x = seed_x;
lfsr_y = seed_y;
}
static unsigned int lfsr_random() {
#pragma HLS INLINE
bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
if((lfsr >> 0) % 2 == 1) b_32 = true;
if((lfsr >> 10) % 2 == 1) b_22 = true;
if((lfsr >> 30) % 2 == 1) b_2 = true;
if((lfsr >> 31) % 2 == 1) b_1 = true;
bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
lfsr >>= 1;
if(new_bit) lfsr |= 0x80000000;
return lfsr;
}
static unsigned int lfsr_x_random() {
#pragma HLS INLINE
bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
if((lfsr_x >> 0) % 2 == 1) b_32 = true;
if((lfsr_x >> 10) % 2 == 1) b_22 = true;
if((lfsr_x >> 30) % 2 == 1) b_2 = true;
if((lfsr_x >> 31) % 2 == 1) b_1 = true;
bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
lfsr_x >>= 1;
if(new_bit) lfsr_x |= 0x80000000;
return lfsr_x;
}
static unsigned int lfsr_y_random() {
#pragma HLS INLINE
bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
if((lfsr_y >> 0) % 2 == 1) b_32 = true;
if((lfsr_y >> 10) % 2 == 1) b_22 = true;
if((lfsr_y >> 30) % 2 == 1) b_2 = true;
if((lfsr_y >> 31) % 2 == 1) b_1 = true;
bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
lfsr_y >>= 1;
if(new_bit) lfsr_y |= 0x80000000;
return lfsr_y;
}
bool solver(hls::stream<ap_uint<4> >& state, unsigned int seed[3], short int *pbnum, short int *plnum,
short int block_info[MAX_BLOCKS+1][5][3], short int *pwi, short int *phi, short int block_place_global[MAX_BLOCKS+1][2], short int opt_result[MAX_CELLS]) {
#pragma HLS INTERFACE s_axilite port=return
#pragma HLS INTERFACE ap_hs register port=state
#pragma HLS INTERFACE m_axi depth=1 port=seed offset=slave bundle=io_data
#pragma HLS INTERFACE m_axi depth=1 port=pbnum offset=slave bundle=io_data
#pragma HLS INTERFACE m_axi depth=1 port=plnum offset=slave bundle=io_data
#pragma HLS INTERFACE m_axi depth=1 port=block_info offset=slave bundle=io_data
#pragma HLS INTERFACE m_axi depth=1 port=pwi offset=slave bundle=io_data
#pragma HLS INTERFACE m_axi depth=1 port=phi offset=slave bundle=io_data
#pragma HLS INTERFACE m_axi depth=1 port=block_place_global offset=slave bundle=io_data
#pragma HLS INTERFACE m_axi depth=1 port=opt_result offset=slave bundle=io_data
state.write(0b0000);
short int blocks = *pbnum;
short int line_num = *plnum;
short int wi, hi;
lfsr_random_init(seed[0], seed[1], seed[2]);
bool status;
state.write(0b0001);
status = local_placement_1(line_num, blocks, &wi, &hi, block_info, block_place_global, opt_result);
if(!status) { // Cannot route
state.write(0b0010);
return false;
}
state.write(0b0011);
status = local_placement_2(line_num, blocks, &wi, &hi, block_info, opt_result);
if(!status) {
state.write(0b0100);
return false;
}
else {
state.write(0b0111);
}
*pwi = wi;
*phi = hi;
return true;
}
bool local_placement_1(short int line_num, short int blocks, short int *pwi, short int *phi, short int block_info[MAX_BLOCKS+1][5][3], short int block_place_global[MAX_BLOCKS+1][2], short int opt_result[MAX_CELLS]) {
short int wi, hi; // board size (w, h)
// size of each slot (w, h)
short int slot_w[SLOT_MAX_SIZE];
short int slot_h[SLOT_MAX_SIZE];
// basic position of each slot (x, y)
short int slot_w_t[SLOT_MAX_SIZE];
short int slot_h_t[SLOT_MAX_SIZE];
short int block_place_slack[MAX_BLOCKS+1][2];
short int block_place_basis[MAX_BLOCKS+1][2];
short int block_place_delta[MAX_BLOCKS+1][2];
short int block_place_opt[MAX_BLOCKS+1][2];
short int board_str[MAX_CELLS];
#pragma HLS ARRAY_PARTITION variable=board_str cyclic factor=4 dim=1
// load a placement result
short int min_x = SLOT_MAX_SIZE, min_y = SLOT_MAX_SIZE, max_x = 0, max_y = 0;
PLACE_1_LOAD_1:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int p = block_place_global[i][0];
short int q = block_place_global[i][1];
if(p < min_x) { min_x = p; }
if(q < min_y) { min_y = q; }
if(p > max_x) { max_x = p; }
if(q > max_y) { max_y = q; }
}
PLACE_1_LOAD_2:
for(short int p = min_x; p <= max_x; p++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=64
slot_w[p] = 0;
}
PLACE_1_LOAD_3:
for(short int q = min_y; q <= max_y; q++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=64
slot_h[q] = 0;
}
PLACE_1_LOAD_4:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int sx = block_info[i][0][0];
short int sy = block_info[i][0][1];
short int p = block_place_global[i][0];
short int q = block_place_global[i][1];
if(sx > slot_w[p]) { slot_w[p] = sx; }
if(sy > slot_h[q]) { slot_h[q] = sy; }
}
wi = INTER_BLOCK_MARGIN;
PLACE_1_LOAD_5:
for(short int p = min_x; p <= max_x; p++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=64
slot_w_t[p] = wi;
wi += slot_w[p] + INTER_BLOCK_MARGIN;
}
hi = INTER_BLOCK_MARGIN;
PLACE_1_LOAD_6:
for(short int q = min_y; q <= max_y; q++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=64
slot_h_t[q] = hi;
hi += slot_h[q] + INTER_BLOCK_MARGIN;
}
#ifdef DEBUG_PRINT
cout << "== Local placement with routing (1) ==" << endl;
cout << "Board size = " << wi << "X" << hi << endl;
#endif
// calculate slack for each block
PLACE_1_CALC_SLACK:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int sx = block_info[i][0][0];
short int sy = block_info[i][0][1];
short int p = block_place_global[i][0];
short int q = block_place_global[i][1];
block_place_basis[i][0] = slot_w_t[p];
block_place_basis[i][1] = slot_h_t[q];
block_place_slack[i][0] = slot_w[p] - sx;
block_place_slack[i][1] = slot_h[q] - sy;
}
bool find_route = false;
int min_status = MAX_CELLS;
PLACE_1_SEARCH:
for(int counter = 0; counter < LOOP; counter++) {
#ifdef DEBUG_PRINT
cout << "."; fflush(stdout);
#endif
PLACE_1_SEARCH_INIT:
for(int s = 0; s < MAX_CELLS; s++) {
#pragma HLS UNROLL factor=8
board_str[s] = 0;
}
PLACE_1_SEARCH_SET:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int x = block_place_basis[i][0];
short int y = block_place_basis[i][1];
short int dx = lfsr_x_random() % (block_place_slack[i][0] + 1);
short int dy = lfsr_y_random() % (block_place_slack[i][1] + 1);
block_place_delta[i][0] = dx;
block_place_delta[i][1] = dy;
PLACE_1_SEARCH_SET_1:
for(int it = 1; it < 5; it++) {
short int tx = block_info[i][it][0];
short int ty = block_info[i][it][1];
short int tn = block_info[i][it][2];
if(tn < 0) break;
short int p = x + dx + tx;
short int q = y + dy + ty;
short int idx = q * MAX_SIZE + p;
if(tn > 0) { board_str[idx] = tn; }
else { board_str[idx] = -1; }
}
}
int status = router(wi, hi, line_num, board_str); // routing
if(status >= 0 && status < min_status) {
min_status = status;
find_route = true;
PLACE_1_SEARCH_OUT_1:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
block_place_opt[i][0] = block_place_basis[i][0] + block_place_delta[i][0];
block_place_opt[i][1] = block_place_basis[i][1] + block_place_delta[i][1];
}
PLACE_1_SEARCH_OUT_2_Y:
for(short int y = 0; y < hi; y++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
PLACE_1_SEARCH_OUT_2_X:
for(short int x = 0; x < wi; x++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int idx = y * MAX_SIZE + x;
opt_result[idx] = board_str[idx];
}
}
}
}
#ifdef DEBUG_PRINT
cout << endl;
#endif
if(!find_route) return false;
// Update
PLACE_1_UPDATE_I:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
block_place_basis[i][0] = block_place_opt[i][0];
block_place_basis[i][1] = block_place_opt[i][1];
}
/// print for debug ///
#ifdef DEBUG_PRINT
cout << "Min-wire status: " << min_status << endl;
show_result(line_num, blocks, wi, hi, opt_result);
#endif
/// print for debug ///
//cout << "== Local placement with routing (1+) ==" << endl;
bool remove_flag;
short int deleted_line_w = 0, deleted_line_h = 0;
PLACE_1_UPDATE_Y:
for(short int q = hi - 1; q >= 0; q--) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
remove_flag = true;
PLACE_1_UPDATE_Y_X:
for(short int p = 0; p < wi; p++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int idx = q * MAX_SIZE + p;
if(opt_result[idx] != 0) {
remove_flag = false;
break;
}
}
if(!remove_flag) continue;
PLACE_1_UPDATE_Y_B:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
if(block_place_basis[i][1] > q) { block_place_basis[i][1] -= 1; }
}
deleted_line_h++;
}
PLACE_1_UPDATE_X:
for(short int p = wi - 1; p >= 0; p--) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
remove_flag = true;
PLACE_1_UPDATE_X_Y:
for(short int q = 0; q < hi; q++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int idx = q * MAX_SIZE + p;
if(opt_result[idx] != 0) {
remove_flag = false;
break;
}
}
if(!remove_flag) continue;
PLACE_1_UPDATE_X_B:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
if(block_place_basis[i][0] > p) { block_place_basis[i][0] -= 1; }
}
deleted_line_w++;
}
hi -= deleted_line_h;
wi -= deleted_line_w;
PLACE_1_REROUTE_INIT:
for(int s = 0; s < MAX_CELLS; s++) {
#pragma HLS UNROLL factor=8
board_str[s] = 0;
}
PLACE_1_REROUTE_SET:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int x = block_place_basis[i][0];
short int y = block_place_basis[i][1];
PLACE_1_REROUTE_SET_1:
for(int it = 1; it < 5; it++) {
short int tx = block_info[i][it][0];
short int ty = block_info[i][it][1];
short int tn = block_info[i][it][2];
if(tn < 0) break;
short int p = x + tx;
short int q = y + ty;
short int idx = q * MAX_SIZE + p;
if(tn > 0) { board_str[idx] = tn; }
else { board_str[idx] = -1; }
}
}
int counter = 0;
PLACE_1_REROUTE_LOOP:
while(router(wi, hi, line_num, board_str) < 0) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=5
if(counter++ >= LOOP) return false;
}
PLACE_1_O_1_Y:
for(short int y = 0; y < hi; y++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
PLACE_1_O_1_X:
for(short int x = 0; x < wi; x++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int idx = y * MAX_SIZE + x;
opt_result[idx] = board_str[idx];
}
}
PLACE_1_O_2:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
block_info[i][0][0] = block_place_basis[i][0];
block_info[i][0][1] = block_place_basis[i][1];
}
*pwi = wi;
*phi = hi;
return true;
}
bool local_placement_2(short int line_num, short int blocks, short int *pwi, short int *phi, short int block_info[MAX_BLOCKS+1][5][3], short int opt_result[MAX_CELLS]) {
short int wi = *pwi, hi = *phi;
short int block_place_slack[MAX_BLOCKS+1][2];
short int block_place_basis[MAX_BLOCKS+1][2];
short int block_place_delta[MAX_BLOCKS+1][2];
short int block_place_opt[MAX_BLOCKS+1][2];
short int board_str[MAX_CELLS];
#pragma HLS ARRAY_PARTITION variable=board_str cyclic factor=4 dim=1
PLACE_2_I:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
block_place_basis[i][0] = block_info[i][0][0];
block_place_basis[i][1] = block_info[i][0][1];
}
#ifdef DEBUG_PRINT
cout << "== Local placement with routing (2) ==" << endl;
#endif
int direction = 0; // 0: X, 1: Y
int try_count = 1;
int no_update = 0;
if(hi > wi) direction = 1;
PLACE_2_BODY:
while(try_count <= TRY_LIMIT) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=50
#ifdef DEBUG_PRINT
cout << "Phase " << try_count << ": direction: ";
switch(direction) {
case 0: cout << "X" << endl; break;
case 1: cout << "Y" << endl; break;
}
cout << "Board size = " << wi << "X" << hi << endl;
#endif
// calculate slack for each block
PLACE_2_CALC_SLACK:
for(int t = 1; t <= blocks; t++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
block_place_slack[t][0] = 0;
block_place_slack[t][1] = 0;
PLACE_2_CALC_SLACK_I:
for(int s = 0; s < MAX_CELLS; s++) {
#pragma HLS UNROLL factor=8
board_str[s] = 0;
}
PLACE_2_CALC_SLACK_1:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
if(i == t) continue;
short int x = block_place_basis[i][0];
short int y = block_place_basis[i][1];
PLACE_2_CALC_SLACK_1_1:
for(int it = 1; it < 5; it++) {
short int tx = block_info[i][it][0];
short int ty = block_info[i][it][1];
short int tn = block_info[i][it][2];
if(tn < 0) break;
short int p = x + tx;
short int q = y + ty;
short int idx = q * MAX_SIZE + p;
if(tn > 0) { board_str[idx] = tn; }
else { board_str[idx] = -1; }
}
}
bool move_x = true, move_y = true;
PLACE_2_CALC_SLACK_2: // X direction
while(direction == 0) {
#pragma HLS LOOP_TRIPCOUNT min=0 max=10
short int x = block_place_basis[t][0];
short int y = block_place_basis[t][1];
PLACE_2_CALC_SLACK_2_1:
for(int it = 1; it < 5; it++) {
short int tx = block_info[t][it][0];
short int ty = block_info[t][it][1];
short int tn = block_info[t][it][2];
if(tn < 0) break;
short int p = x + tx - (block_place_slack[t][0]+1);
short int q = y + ty;
short int idx = q * MAX_SIZE + p;
if(p < 0 || board_str[idx] != 0) {
move_x = false;
break;
}
}
if(move_x) {
if(++block_place_slack[t][0] >= 9) break;
}
else {
break;
}
}
PLACE_2_CALC_SLACK_3: // Y direction
while(direction == 1) {
#pragma HLS LOOP_TRIPCOUNT min=0 max=10
short int x = block_place_basis[t][0];
short int y = block_place_basis[t][1];
PLACE_2_CALC_SLACK_3_1:
for(int it = 1; it < 5; it++) {
short int tx = block_info[t][it][0];
short int ty = block_info[t][it][1];
short int tn = block_info[t][it][2];
if(tn < 0) break;
short int p = x + tx;
short int q = y + ty - (block_place_slack[t][1]+1);
short int idx = q * MAX_SIZE + p;
if(q < 0 || board_str[idx] != 0) {
move_y = false;
break;
}
}
if(move_y) {
if(++block_place_slack[t][1] >= 9) break;
}
else {
break;
}
}
}
no_update++;
bool find_route = false;
int d_sum_max = 0;
PLACE_2_SEARCH:
for(int counter = 0; counter < LOOP; counter++) {
#ifdef DEBUG_PRINT
cout << "."; fflush(stdout);
#endif
PLACE_2_SEARCH_INIT:
for(int s = 0; s < MAX_CELLS; s++) {
#pragma HLS UNROLL factor=8
board_str[s] = 0;
}
int d_sum = 0;
PLACE_2_SEARCH_SET:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int x = block_place_basis[i][0];
short int y = block_place_basis[i][1];
short int dx = 0;
short int dy = 0;
switch(direction) {
case 0: dx = lfsr_x_random() % (block_place_slack[i][0] + 1); break;
case 1: dy = lfsr_y_random() % (block_place_slack[i][1] + 1); break;
}
if(lfsr_random() % 16 >= 2) {
dx = 0;
dy = 0;
}
block_place_delta[i][0] = dx;
block_place_delta[i][1] = dy;
d_sum += dx + dy;
PLACE_2_SEARCH_SET_1:
for(int it = 1; it < 5; it++) {
short int tx = block_info[i][it][0];
short int ty = block_info[i][it][1];
short int tn = block_info[i][it][2];
if(tn < 0) break;
short int p = x - dx + tx;
short int q = y - dy + ty;
short int idx = q * MAX_SIZE + p;
if(tn > 0) { board_str[idx] = tn; }
else{ board_str[idx] = -1; }
}
}
int status = router(wi, hi, line_num, board_str);
if(status >= 0 && d_sum > d_sum_max) {
d_sum_max = d_sum;
find_route = true;
PLACE_2_SEARCH_OUT_1:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
block_place_opt[i][0] = block_place_basis[i][0] - block_place_delta[i][0];
block_place_opt[i][1] = block_place_basis[i][1] - block_place_delta[i][1];
}
PLACE_2_SEARCH_OUT_2_Y:
for(short int y = 0; y < hi; y++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
PLACE_2_SEARCH_OUT_2_X:
for(short int x = 0; x < wi; x++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int idx = y * MAX_SIZE + x;
opt_result[idx] = board_str[idx];
}
}
}
}
#ifdef DEBUG_PRINT
cout << endl;
#endif
if(find_route) {
no_update = 0; // reset
// Update
PLACE_2_UPDATE_I:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
block_place_basis[i][0] = block_place_opt[i][0];
block_place_basis[i][1] = block_place_opt[i][1];
}
/// print for debug ///
#ifdef DEBUG_PRINT
cout << "Max dSum: " << d_sum_max << endl;
show_result(line_num, blocks, wi, hi, opt_result);
#endif
/// print for debug ///
bool remove_flag;
short int deleted_line_w = 0, deleted_line_h = 0;
PLACE_2_UPDATE_Y:
for(short int q = hi - 1; q >= 0; q--) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
remove_flag = true;
PLACE_2_UPDATE_Y_X:
for(short int p = 0; p < wi; p++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int idx = q * MAX_SIZE + p;
if(opt_result[idx] != 0) {
remove_flag = false;
break;
}
}
if(!remove_flag) continue;
PLACE_2_UPDATE_Y_B:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
if(block_place_basis[i][1] > q) { block_place_basis[i][1] -= 1; }
}
deleted_line_h++;
}
PLACE_2_UPDATE_X:
for(short int p = wi - 1; p >= 0; p--) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
remove_flag = true;
PLACE_2_UPDATE_X_Y:
for(short int q = 0; q < hi; q++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int idx = q * MAX_SIZE + p;
if(opt_result[idx] != 0) {
remove_flag = false;
break;
}
}
if(!remove_flag) continue;
PLACE_2_UPDATE_X_B:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
if(block_place_basis[i][0] > p) { block_place_basis[i][0] -= 1; }
}
deleted_line_w++;
}
hi -= deleted_line_h;
wi -= deleted_line_w;
PLACE_2_REROUTE_INIT:
for(int s = 0; s < MAX_CELLS; s++) {
#pragma HLS UNROLL factor=8
board_str[s] = 0;
}
PLACE_2_REROUTE_SET:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int x = block_place_basis[i][0];
short int y = block_place_basis[i][1];
PLACE_2_REROUTE_SET_1:
for(int it = 1; it < 5; it++) {
short int tx = block_info[i][it][0];
short int ty = block_info[i][it][1];
short int tn = block_info[i][it][2];
if(tn < 0) break;
short int p = x + tx;
short int q = y + ty;
short int idx = q * MAX_SIZE + p;
if(tn > 0) { board_str[idx] = tn; }
else { board_str[idx] = -1; }
}
}
int counter = 0;
PLACE_2_REROUTE_LOOP:
while(router(wi, hi, line_num, board_str) < 0) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=5
if(counter++ >= LOOP) return false;
}
PLACE_2_REROUTE_OUT_Y:
for(short int y = 0; y < hi; y++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
PLACE_2_REROUTE_OUT_X:
for(short int x = 0; x < wi; x++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int idx = y * MAX_SIZE + x;
opt_result[idx] = board_str[idx];
}
}
} // End update
if(no_update >= NO_MOVE) break;
try_count++;
switch(direction) {
case 0: direction = 1; break;
case 1: direction = 0; break;
}
}
#ifdef DEBUG_PRINT
cout << "#Tries: " << try_count << endl;
#endif
PLACE_2_O_2:
for(int i = 1; i <= blocks; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
block_info[i][0][0] = block_place_basis[i][0];
block_info[i][0][1] = block_place_basis[i][1];
}
*pwi = wi;
*phi = hi;
return true;
}
unsigned short int new_weight(unsigned short int x) {
#pragma HLS INLINE
unsigned short int y = (x & 0x00FF) + 1;
return y;
}
unsigned short int my_abs(short int x) {
#pragma HLS INLINE
if(x < 0) x *= -1;
return x;
}
// DATA_BIT: bit length of cell idx
// PRIO_BIT: bit length of cost(priority)
int router(short int size_x, short int size_y, short int line_num, short int board_str[MAX_CELLS]) {
if(line_num == 0) return 0;
short int terminals[MAX_LINES][2];
short int paths_size[MAX_LINES];
unsigned short int paths[MAX_LINES][MAX_PATH];
bool adjacents[MAX_LINES];
unsigned short int weights[MAX_CELLS];
SET_LOOP_1:
for(int i = 0; i < line_num; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=256
terminals[i][0] = -1;
terminals[i][1] = -1;
paths_size[i] = 0;
adjacents[i] = false;
}
SET_LOOP_2_Y:
for(short int y = 0; y < size_y; y++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
SET_LOOP_2_X:
for(short int x = 0; x < size_x; x++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int j = y * MAX_SIZE + x;
short int num = board_str[j];
switch(num) {
case 0:
weights[j] = 1;
break;
case -1:
weights[j] = PRIO_MAX;
break;
default:
weights[j] = PRIO_MAX;
if(terminals[num-1][0] >= 0) { terminals[num-1][1] = j; }
else { terminals[num-1][0] = j; }
break;
}
}
}
#ifdef PRINT_BOARD
cout << "== Print board ==" << endl;
for(short int y = 0; y < size_y; y++) {
for(short int x = 0; x < size_x; x++) {
short int j = y * MAX_SIZE + x;
short int num = board_str[j];
if(num == 0) { cout << "--"; }
else if(num == -1) { cout << "XX"; }
else{ cout << setfill('0') << setw(2) << hex << num; }
if(x != size_x-1) { cout << " "; }
}
cout << endl;
}
cout << setfill(' ');
cout << dec;
#endif
SET_LOOP_3:
for(int i = 0; i < line_num; i++) {
#pragma HLS UNROLL factor=2
#pragma HLS LOOP_TRIPCOUNT min=1 max=256
short int t1 = terminals[i][0];
short int t2 = terminals[i][1];
short int t1_y = t1 / MAX_SIZE;
short int t1_x = t1 - MAX_SIZE * t1_y;
short int t2_y = t2 / MAX_SIZE;
short int t2_x = t2 - MAX_SIZE * t2_y;
unsigned short int dist = my_abs(t1_x - t2_x) + my_abs(t1_y - t2_y);
if(dist == 1) {
adjacents[i] = true;
#ifdef PRINT_BOARD
cout << "Line #" << i + 1 << " needs no routing" << endl;
#endif
}
}
// Step 1 //
ROUTING_1:
for(int i = 0; i < line_num; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=256
if(adjacents[i]) continue;
#ifdef PRINT_SEARCH
cout << "Line #" << i + 1 << endl;
#endif
short int t1 = terminals[i][0];
short int t2 = terminals[i][1];
weights[t1] = 1;
if(search(size_x, size_y, &paths_size[i], paths[i], t1, t2, weights) < 0) { return -1; }
weights[t1] = PRIO_MAX;
}
bool has_overlap;
short int overlap_checks[MAX_CELLS];
short int last_target = -1;
// Step 2 //
ROUTING_2:
for(int round = 1; round <= ROUND_LIMIT; round++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=4096
short int target = lfsr_random() % line_num;
if(adjacents[target]) continue;
if(target == last_target) continue;
last_target = target;
unsigned short int round_weight = new_weight(round);
#ifdef PRINT_SEARCH
cout << "Line #" << target + 1 << "(round: " << round << ", weight: " << round_weight << ")" << endl;
#endif
short int t1 = terminals[target][0];
short int t2 = terminals[target][1];
WEIGHT_UPDATE_1:
for(short int p = 0; p < paths_size[target]; p++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
weights[paths[target][p]] = 1;
}
WEIGHT_UPDATE_2:
for(int i = 0; i < line_num; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=256
if(i == target) continue;
WEIGHT_UPDATE_2_1:
for(short int p = 0; p < paths_size[i]; p++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
weights[paths[i][p]] = round_weight;
}
}
weights[t1] = 1;
search(size_x, size_y, &paths_size[target], paths[target], t1, t2, weights);
weights[t1] = PRIO_MAX;
has_overlap = false;
OVERLAP_CHECK_1:
for(short int y = 0; y < size_y; y++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
OVERLAP_CHECK_1_1:
for(short int x = 0; x < size_x; x++) {
#pragma HLS LOOP_TRIPCOUNT min=10 max=128
short int j = y * MAX_SIZE + x;
overlap_checks[j] = 0;
}
}
OVERLAP_CHECK_2:
for(int i = 0; i < line_num && !has_overlap; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=256
OVERLAP_CHECK_2_1:
for(short int p = 0; p < paths_size[i]; p++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int cell_id = paths[i][p];
if(overlap_checks[cell_id] == 1) {
has_overlap = true;
break;
}
overlap_checks[cell_id] = 1;
}
}
if(!has_overlap) break;
}
if(has_overlap) { // Cannot solve
return -1;
}
int total_wire_length = 0;
OUTPUT_1:
for(short int i = 0; i < line_num; i++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=256
total_wire_length += paths_size[i];
OUTPUT_1_1:
for(short int p = 0; p < paths_size[i]; p++) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
short int cell_id = paths[i][p];
board_str[cell_id] = i + 1;
}
}
#ifdef PRINT_BOARD
cout << "== Print answer ==" << endl;
for(short int y = 0; y < size_y; y++) {
for(short int x = 0; x < size_x; x++) {
short int j = y * MAX_SIZE + x;
short int num = board_str[j];
if(num == 0) { cout << "--"; }
else if(num == -1) { cout << "XX"; }
else{ cout << setfill('0') << setw(2) << hex << num; }
if(x != size_x-1) { cout << " "; }
}
cout << endl;
}
cout << setfill(' ');
cout << dec;
#endif
return total_wire_length;
}
int search(short int size_x, short int size_y, short int *path_size, unsigned short int path[MAX_PATH], unsigned short int start, unsigned short int goal, unsigned short int w[MAX_CELLS]) {
unsigned short int dist[MAX_CELLS];
#pragma HLS ARRAY_PARTITION variable=dist cyclic factor=16 dim=1
unsigned short int prev[MAX_CELLS];
#pragma HLS ARRAY_PARTITION variable=prev cyclic factor=16 dim=1
SEARCH_INIT_DIST:
for(int j = 0; j < MAX_CELLS; j++) {
#pragma HLS UNROLL factor=32
dist[j] = PRIO_MAX;
}
ap_uint<PQ_BIT> pq_len = 0;
bool is_empty = true;
unsigned int pq_nodes[MAX_PQ];
short int goal_y = goal / MAX_SIZE;
short int goal_x = goal - MAX_SIZE * goal_y;
dist[start] = 0;
enqueue(pq_nodes, 0, start, &pq_len, &is_empty);
bool find_path = false;
SEARCH_BODY:
while(!is_empty) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=1000
unsigned short int prev_cost;
unsigned short int s;
dequeue(pq_nodes, &prev_cost, &s, &pq_len, &is_empty);
if(s == goal) {
find_path = true;
break;
}
unsigned short int dist_s = dist[s];
unsigned short int cost = w[s];
unsigned short int dist_d = dist_s + cost;
short int s_y = s / MAX_SIZE;
short int s_x = s - MAX_SIZE * s_y;
SEARCH_ADJACENTS:
for(int a = 0; a < 4; a++) {
#pragma HLS UNROLL
short int d_x = s_x;
short int d_y = s_y;
switch(a) {
case 0: d_x -= 1; break;
case 1: d_x += 1; break;
case 2: d_y -= 1; break;
case 3: d_y += 1; break;
}
if(d_x >= 0 && d_x < size_x && d_y >= 0 && d_y < size_y) {
unsigned short int d = d_y * MAX_SIZE + d_x;
if(w[d] == PRIO_MAX && d != goal) continue;
if(dist_d < dist[d]) {
dist[d] = dist_d;
prev[d] = s;
unsigned short int new_dist = dist_d + my_abs(d_x - goal_x) + my_abs(d_y - goal_y);
enqueue(pq_nodes, new_dist, d, &pq_len, &is_empty);
}
}
}
}
if(!find_path){ return -1; }
unsigned short int t = prev[goal];
short int p = 0;
#ifdef PRINT_SEARCH
cout << "Path: ";
#endif
SEARCH_BACKTRACK:
while(t != start) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=128
#ifdef PRINT_SEARCH
cout << "(" << t % MAX_SIZE << ", " << t / MAX_SIZE << ")";
#endif
path[p] = t;
p++;
t = prev[t];
}
#ifdef PRINT_SEARCH
cout << endl;
#endif
*path_size = p;
return 0;
}
// Enqueue (Insert an element)
void enqueue(unsigned int pq_nodes[MAX_PQ], unsigned short int queue_priority, unsigned short int queue_data, ap_uint<PQ_BIT> *pq_len, bool *is_empty) {
#pragma HLS INLINE
(*pq_len)++;
if ((*pq_len) == 0) { (*pq_len)--; } // Queue is full -> Last element is automatically removed
// Note that last element is not always the lowest priority one. //
ap_uint<PQ_BIT> i = (*pq_len);
ap_uint<PQ_BIT> p = (*pq_len) >> 1; // parent node
ENQUEUE_LOOP:
while (i > 1 && (unsigned short int)(pq_nodes[p] >> DATA_BIT) >= queue_priority) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=12
pq_nodes[i] = pq_nodes[p];
i = p;
p = p >> 1; // parent node
}
pq_nodes[i] = ((unsigned int)queue_priority << DATA_BIT) | (unsigned int)queue_data;
*is_empty = false;
}
// Dequeue (Extract and remove the top element)
void dequeue(unsigned int pq_nodes[MAX_PQ], unsigned short int *ret_priority, unsigned short int *ret_data, ap_uint<PQ_BIT> *pq_len, bool *is_empty) {
#pragma HLS INLINE
*ret_priority = (unsigned short int)(pq_nodes[1] >> DATA_BIT);
*ret_data = (unsigned short int)(pq_nodes[1] & DATA_MASK);
ap_uint<PQ_BIT> i = 1; // root node
unsigned short int last_priority = (unsigned short int)(pq_nodes[*pq_len] >> DATA_BIT); // Priority of last element
DEQUEUE_LOOP:
while (!(i >> (PQ_BIT-1))) {
#pragma HLS LOOP_TRIPCOUNT min=1 max=12
ap_uint<PQ_BIT> c1 = i << 1; // child node (L)
ap_uint<PQ_BIT> c2 = c1 + 1; // child node (R)
if (c1 < *pq_len && (unsigned short int)(pq_nodes[c1] >> DATA_BIT) <= last_priority) {
if (c2 < *pq_len && (unsigned short int)(pq_nodes[c2] >> DATA_BIT) <= (unsigned short int)(pq_nodes[c1] >> DATA_BIT)) {
pq_nodes[i] = pq_nodes[c2];
i = c2;
}
else {
pq_nodes[i] = pq_nodes[c1];
i = c1;
}
}
else {
if (c2 < *pq_len && (unsigned short int)(pq_nodes[c2] >> DATA_BIT) <= last_priority) {
pq_nodes[i] = pq_nodes[c2];
i = c2;
}
else {
break;
}
}
}
pq_nodes[i] = pq_nodes[*pq_len];
(*pq_len)--;
if ((*pq_len) == 0) { *is_empty = true; }
}
hardware_design/source_code/solver.hpp 0 → 100755
View file @ 940a7e2c
#ifndef __SOLVER_HPP__
#define __SOLVER_HPP__
//#define DEBUG_PRINT
#include <iostream>
#include "param.hpp"
#include <ap_int.h>
#include <hls_stream.h>
#ifdef DEBUG_PRINT
#include "tools.hpp"
#endif
using namespace std;
bool solver(hls::stream<ap_uint<4> >& state, unsigned int seed[3], short int *pbnum, short int *plnum, short int block_info[MAX_BLOCKS+1][5][3], short int *pwi, short int *phi, short int block_place_global[MAX_BLOCKS+1][2], short int opt_result[MAX_CELLS]);
bool local_placement_1(short int line_num, short int blocks, short int *pwi, short int *phi, short int block_info[MAX_BLOCKS+1][5][3], short int block_place_global[MAX_BLOCKS+1][2], short int opt_result[MAX_CELLS]);
bool local_placement_2(short int line_num, short int blocks, short int *pwi, short int *phi, short int block_info[MAX_BLOCKS+1][5][3], short int opt_result[MAX_CELLS]);
int router(short int size_x, short int size_y, short int line_num, short int board_str[MAX_CELLS]);
int search(short int size_x, short int size_y, short int *path_size, unsigned short int path[MAX_PATH], unsigned short int start, unsigned short int goal, unsigned short int w[MAX_CELLS]);
void enqueue(unsigned int pq_nodes[MAX_PQ], unsigned short int queue_priority, unsigned short int queue_data, ap_uint<PQ_BIT> *pq_len, bool *is_empty);
void dequeue(unsigned int pq_nodes[MAX_PQ], unsigned short int *ret_priority, unsigned short int *ret_data, ap_uint<PQ_BIT> *pq_len, bool *is_empty);
#endif /* __SOLVER_HPP__ */
hardware_design/test_bench/io.cpp 0 → 100755
View file @ 940a7e2c
#include "io.hpp"
void read_problem(short int *W, short int *H, short int *blocks, short int *line_num, short int block_info[][5][3], short int line_info[][2][5]) {
for(int i = 0; i < MAX_BLOCKS+1; i++) {
for(int j = 0; j < 5; j++) {
for(int k = 0; k < 3; k++) {
block_info[i][j][k] = -1;
}
}
}
for(int i = 0; i < MAX_LINES+1; i++) {
for(int j = 0; j < 2; j++) {
for(int k = 0; k < 5; k++) {
line_info[i][j][k] = -1;
}
}
}
*line_num = 0;
int now_block = 0, count;
short int size_x = -1, size_y = -1, now_x, now_y, num;
while(1) {
string line, tmp;
string::size_type pos;
if(!getline(cin,line)) break; // stdin
if(line.find("\n") != string::npos || line.find("\r") != string::npos) {
line.replace(line.length()-1, 1, ""); // Remove '\n' or '\r'
}
int len = line.length();
if(len == 0) continue;
if(line.find("SIZE") != string::npos) {
replace(line.begin(), line.end(), 'X', ' ');
istringstream iss(line);
iss >> tmp >> *W >> *H;
continue;
}
else if(line.find("BLOCK_NUM") != string::npos) {
istringstream iss(line);
iss >> tmp >> *blocks;
continue;
}
else if(line.find("BLOCK") != string::npos) {
now_block++;
replace(line.begin(), line.end(), 'X', ' ');
istringstream iss(line);
iss >> tmp >> size_x >> size_y;
now_y = 0;
count = 1;
block_info[now_block][0][0] = size_x;
block_info[now_block][0][1] = size_y;
continue;
}
// Replace ' ' -> ""
pos = 0;
while((pos = line.find(' ', pos)) != string::npos) {
line.replace(pos, 1, "");
}
// Replace '+' -> "-1"
pos = 0;
while((pos = line.find('+', pos)) != string::npos) {
line.replace(pos, 1, "-1");
}
// Replace ',' -> " "
pos = 0;
while((pos = line.find(',', pos)) != string::npos) {
line.replace(pos, 1, " ");
}
istringstream iss(line);
for(now_x = 0; now_x < size_x; now_x++) {
iss >> num;
if(num > 0) {
block_info[now_block][count][0] = now_x;
block_info[now_block][count][1] = now_y;
block_info[now_block][count][2] = num;
if(line_info[num][0][0] == -1) { line_info[num][0][0] = now_block; }
else if(line_info[num][1][0] == -1) { line_info[num][1][0] = now_block; }
else { cout << "Error(RE0): Line#" << num << endl; exit(1); }
if(num > *line_num) { *line_num = num; }
count++;
}
else if(num < 0) {
block_info[now_block][count][0] = now_x;
block_info[now_block][count][1] = now_y;
block_info[now_block][count][2] = 0;
count++;
}
}
now_y++;
}
cout << "W: " << *W << ", H: " << *H << endl;
/// Print block information ///
cout << "== Block information ==" << endl;
cout << "#Blocks = " << *blocks << endl;
for(int i = 1; i <= *blocks; i++) {
short int sx = block_info[i][0][0];
short int sy = block_info[i][0][1];
cout << "Block#" << i << ": (" << sx << ", " << sy << ")" << endl;
if(sx == 1 && sy == 1) { // monomino
short int tx = block_info[i][1][0];
short int ty = block_info[i][1][1];
short int tn = block_info[i][1][2];
cout << "- (" << tx << ", " << ty << ") " << tn << endl;
}
else {
for(int it = 1; it < 5; it++) {
short int tx = block_info[i][it][0];
short int ty = block_info[i][it][1];
short int tn = block_info[i][it][2];
cout << "- (" << tx << ", " << ty << ") " << tn << endl;
}
}
}
/// Print block information ///
}
void extract_line_info(short int line_num, short int blocks, short int block_info[][5][3], short int line_info[][2][5]) {
short int lines_x[4], lines_y[4]; // # of nums in a block for X- & Y- axes
for(int i = 1; i <= blocks; i++) {
short int sx = block_info[i][0][0];
short int sy = block_info[i][0][1];
if(sx == 1 && sy == 1) { // monomino
short int tx = block_info[i][1][0];
short int ty = block_info[i][1][1];
short int tn = block_info[i][1][2];
if(tn == 0) continue;
short int n_idx = 0;
while(line_info[tn][n_idx][1] != -1) {
n_idx++;
if(n_idx >= 2) { cout << "Error(EL0): Line#" << tn << endl; exit(1); }
}
line_info[tn][n_idx][LE] = 2;
line_info[tn][n_idx][TO] = 2;
line_info[tn][n_idx][RI] = 2;
line_info[tn][n_idx][BO] = 2;
continue;
}
for(short int p = 0; p < 4; p++) lines_x[p] = 0;
for(short int q = 0; q < 4; q++) lines_y[q] = 0;
for(int it = 1; it < 5; it++) {
short int tx = block_info[i][it][0];
short int ty = block_info[i][it][1];
short int tn = block_info[i][it][2];
if(tn > 0) {
lines_x[tx] += 1;
lines_y[ty] += 1;
}
}
for(int it = 1; it < 5; it++) {
short int tx = block_info[i][it][0];
short int ty = block_info[i][it][1];
short int tn = block_info[i][it][2];
if(tn == 0) continue;
short int n_idx = 0;
while(line_info[tn][n_idx][1] != -1) {
n_idx++;
if(n_idx >= 2) { cout << "Error(EL1): Line#" << tn << endl; exit(1); }
}
short int compe_cost, wall_cost;
// Map to left
compe_cost = 2;
compe_cost += lines_x[tx] - 1;
for(short int p = tx - 1; p >= 0; p--) { compe_cost += lines_x[p] * 2; }
wall_cost = 1;
for(int it2 = 1; it2 < 5; it2++) {
short int cx = block_info[i][it2][0];
short int cy = block_info[i][it2][1];
if(cx == tx && cy == ty) continue;
if(cy == ty && cx < tx) {
if(sx == 2 && sy == 3 && ty == 1) {
wall_cost = 4;
}
else {
wall_cost = 2;
}
}
}
line_info[tn][n_idx][LE] = compe_cost * wall_cost;
// Map to top
compe_cost = 2;
compe_cost += lines_y[ty] - 1;
for(short int q = ty - 1; q >= 0; q--) { compe_cost += lines_y[q] * 2; }
wall_cost = 1;
for(int it2 = 1; it2 < 5; it2++) {
short int cx = block_info[i][it2][0];
short int cy = block_info[i][it2][1];
if(cx == tx && cy == ty) continue;
if(cx == tx && cy < ty) {
if(sx == 3 && sy == 2 && tx == 1) {
wall_cost = 4;
}
else {
wall_cost = 2;
}
}
}
line_info[tn][n_idx][TO] = compe_cost * wall_cost;
// Map to right
compe_cost = 2;
compe_cost += lines_x[tx] - 1;
for(short int p = tx + 1; p < sx; p++) { compe_cost += lines_x[p] * 2; }
wall_cost = 1;
for(int it2 = 1; it2 < 5; it2++) {
short int cx = block_info[i][it2][0];
short int cy = block_info[i][it2][1];
if(cx == tx && cy == ty) continue;
if(cy == ty && cx > tx) {
if(sx == 2 && sy == 3 && ty == 1) {
wall_cost = 4;
}
else {
wall_cost = 2;
}
}
}
line_info[tn][n_idx][RI] = compe_cost * wall_cost;
// Map to bottom
compe_cost = 2;
compe_cost += lines_y[ty] - 1;
for(short int q = ty + 1; q < sy; q++) { compe_cost += lines_y[q] * 2; }
wall_cost = 1;
for(int it2 = 1; it2 < 5; it2++) {
short int cx = block_info[i][it2][0];
short int cy = block_info[i][it2][1];
if(cx == tx && cy == ty) continue;
if(cx == tx && cy > ty) {
if(sx == 3 && sy == 2 && tx == 1) {
wall_cost = 4;
}
else {
wall_cost = 2;
}
}
}
line_info[tn][n_idx][BO] = compe_cost * wall_cost;
}
}
/// Print line information ///
cout << "== Line information ==" << endl;
cout << "#Lines = " << line_num << endl;
for(int l = 1; l <= line_num; l++) {
short int block1 = line_info[l][0][0];
short int block2 = line_info[l][1][0];
cout << "Line#" << l << ": ";
cout << "Block#" << block1 << "(";
for(int i = 1; i < 5; i++) {
cout << (float)line_info[l][0][i] / 2;
if(i != 4) { cout << ", "; }
}
cout << "), ";
cout << "Block#" << block2 << "(";
for(int i = 1; i < 5; i++) {
cout << (float)line_info[l][1][i] / 2;
if(i != 4) { cout << ", "; }
}
cout << ")" << endl;
}
/// Print line information ///
}
static unsigned int lfsr, lfsr_x, lfsr_y;
static void lfsr_random_init(unsigned int seed, unsigned int seed_x, unsigned int seed_y) {
lfsr = seed;
lfsr_x = seed_x;
lfsr_y = seed_y;
}
static unsigned int lfsr_random() {
bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
if((lfsr >> 0) % 2 == 1) b_32 = true;
if((lfsr >> 10) % 2 == 1) b_22 = true;
if((lfsr >> 30) % 2 == 1) b_2 = true;
if((lfsr >> 31) % 2 == 1) b_1 = true;
bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
lfsr >>= 1;
if(new_bit) lfsr |= 0x80000000;
return lfsr;
}
static unsigned int lfsr_x_random() {
bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
if((lfsr_x >> 0) % 2 == 1) b_32 = true;
if((lfsr_x >> 10) % 2 == 1) b_22 = true;
if((lfsr_x >> 30) % 2 == 1) b_2 = true;
if((lfsr_x >> 31) % 2 == 1) b_1 = true;
bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
lfsr_x >>= 1;
if(new_bit) lfsr_x |= 0x80000000;
return lfsr_x;
}
static unsigned int lfsr_y_random() {
bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
if((lfsr_y >> 0) % 2 == 1) b_32 = true;
if((lfsr_y >> 10) % 2 == 1) b_22 = true;
if((lfsr_y >> 30) % 2 == 1) b_2 = true;
if((lfsr_y >> 31) % 2 == 1) b_1 = true;
bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
lfsr_y >>= 1;
if(new_bit) lfsr_y |= 0x80000000;
return lfsr_y;
}
float calcPlaceCost(short int line_num, short int line_info[MAX_LINES+1][2][5], short int block_place_global[MAX_BLOCKS+1][2]) {
short int block1, block2; // block idx
short int x1, y1; // 1st block
short int x2, y2; // 2nd block
short int delta_x, delta_y;
// delta_x > 0: 1st block is located in the East of 2nd block
// delta_x < 0: 1st block is located in the West of 2nd block
// delta_y > 0: 1st block is located in the South of 2nd block
// delta_y < 0: 1st block is located in the North of 2nd block
short int dist_x, dist_y; // distance between 2 blocks
short int dir_x1, dir_x2; // X-direction from 1st block to 2nd block and ...
short int dir_y1, dir_y2; // Y-direction from 1st block to 2nd block and ...
int cost = 0;
for(int l = 1; l <= line_num; l++) {
block1 = line_info[l][0][0]; // 1st block including line#L
block2 = line_info[l][1][0]; // 2nd block including line#L
x1 = block_place_global[block1][0];
y1 = block_place_global[block1][1];
x2 = block_place_global[block2][0];
y2 = block_place_global[block2][1];
delta_x = x1 - x2;
delta_y = y1 - y2;
//dist_x = abs(delta_x);
//dist_y = abs(delta_y);
dir_x1 = 0;
dir_x2 = 0;
dist_x = 0;
if(delta_x > 0) {
dist_x = delta_x;
dir_x1 = line_info[l][0][1];
dir_x2 = line_info[l][1][3];
}
else if(delta_x < 0) {
dist_x = delta_x * (-1);
dir_x1 = line_info[l][0][3];
dir_x2 = line_info[l][1][1];
}
dir_y1 = 0;
dir_y2 = 0;
dist_y = 0;
if(delta_y > 0) {
dist_y = delta_y;
dir_y1 = line_info[l][0][2];
dir_y2 = line_info[l][1][4];
}
else if(delta_y < 0) {
dist_y = delta_y * (-1);
dir_y1 = line_info[l][0][4];
dir_y2 = line_info[l][1][2];
}
cost += (dist_x * dir_x1 * dir_x2 + dist_y * dir_y1 * dir_y2);
}
return (float)cost / 4;
}
void global_placement(unsigned int seed[3], short int W, short int H, short int line_num, short int blocks, short int block_info[MAX_BLOCKS+1][5][3], short int line_info[MAX_LINES+1][2][5], short int block_place_global[MAX_BLOCKS+1][2]) {
lfsr_random_init(seed[0], seed[1], seed[2]);
cout << "== Global placement ==" << endl;
short int sx_sum = 0, sy_sum = 0;
for(int i = 1; i <= blocks; i++) {
sx_sum += block_info[i][0][0]; // block size (x)
sy_sum += block_info[i][0][1]; // block size (y)
}
// define #slots
short int max_x = W * blocks / sx_sum - 1;
short int max_y = H * blocks / sy_sum - 1;
while(((max_x + 1) * (max_y + 1)) < blocks) {
max_x += 1;
max_y += 1;
}
cout << "#Slots for X-axis: " << max_x + 1 << endl;
cout << "#Slots for Y-axis: " << max_y + 1 << endl;
// init. placement on global slot
short int global_slot[SLOT_MAX_SIZE][SLOT_MAX_SIZE];
short int i = 1;
for(short int q = 0; q <= max_y; q++) {
for(short int p = 0; p <= max_x; p++) {
if(i <= blocks) {
block_place_global[i][0] = p;
block_place_global[i][1] = q;
global_slot[q][p] = i;
i++;
}
else {
global_slot[q][p] = 0;
}
}
}
short int line_info_buf[MAX_LINES+1][2][5];
for(int l = 1; l <= line_num; l++) {
line_info_buf[l][0][0] = line_info[l][0][0];
line_info_buf[l][0][1] = line_info[l][0][1];
line_info_buf[l][0][2] = line_info[l][0][2];
line_info_buf[l][0][3] = line_info[l][0][3];
line_info_buf[l][0][4] = line_info[l][0][4];
line_info_buf[l][1][0] = line_info[l][1][0];
line_info_buf[l][1][1] = line_info[l][1][1];
line_info_buf[l][1][2] = line_info[l][1][2];
line_info_buf[l][1][3] = line_info[l][1][3];
line_info_buf[l][1][4] = line_info[l][1][4];
}
// cost calculation (may be inefficient)
float cost = calcPlaceCost(line_num, line_info_buf, block_place_global);
float init_cost = cost;
cout << "Cost = " << cost << " -> ";
// SA setup
float temperature = TEMP_S;
float delta = powf(((float)(TEMP_E)/(float)(TEMP_S)), (1./(float)(SA_O)));
// SA
for(int counter = 0; counter < SA_O; counter++) {
temperature *= delta; // Update temperature
// trgt_i, trgt_j: moved block idx (trgt_j == 0, no block is placed on slot(j_x,j_y))
// i_x, i_y, j_x, j_y
for(int counter_in = 0; counter_in < SA_I; counter_in++) {
short int trgt_i = lfsr_random() % blocks + 1;
short int i_x = block_place_global[trgt_i][0];
short int i_y = block_place_global[trgt_i][1];
short int j_x = lfsr_x_random() % SLOT_MAX_SIZE;
short int j_y = lfsr_y_random() % SLOT_MAX_SIZE;
if(j_x > max_x || j_y > max_y) continue;
short int trgt_j = global_slot[j_y][j_x]; // slot -> block
block_place_global[trgt_i][0] = j_x;
block_place_global[trgt_i][1] = j_y;
global_slot[j_y][j_x] = trgt_i;
block_place_global[trgt_j][0] = i_x;
block_place_global[trgt_j][1] = i_y;
global_slot[i_y][i_x] = trgt_j;
float new_cost = calcPlaceCost(line_num, line_info_buf, block_place_global);
if(new_cost > cost && (float)lfsr_random()/LFSR_RAND_MAX > expf(-(new_cost-cost)/temperature)) {
block_place_global[trgt_i][0] = i_x;
block_place_global[trgt_i][1] = i_y;
global_slot[i_y][i_x] = trgt_i;
block_place_global[trgt_j][0] = j_x;
block_place_global[trgt_j][1] = j_y;
global_slot[j_y][j_x] = trgt_j;
}
else if(new_cost != cost) { cost = new_cost; }
}
}
cout << cost << endl;
seed[0] = lfsr;
seed[1] = lfsr_x;
seed[2] = lfsr_y;
}
hardware_design/test_bench/io.hpp 0 → 100755
View file @ 940a7e2c
#ifndef __IO_HPP__
#define __IO_HPP__
#include <iostream>
#include <sstream> // for istringstream
#include <algorithm> // for replace
#include <math.h>
#include "param.hpp"
using namespace std;
void read_problem(short int *W, short int *H, short int *blocks, short int *line_num, short int block_info[][5][3], short int line_info[][2][5]);
void extract_line_info(short int line_num, short int blocks, short int block_info[][5][3], short int line_info[][2][5]);
float calcPlaceCost(short int line_num, short int line_info[MAX_LINES+1][2][5], pair<short int,short int> block_place_global[MAX_BLOCKS+1]);
void global_placement(unsigned int seed[3], short int W, short int H, short int line_num, short int blocks, short int block_info[MAX_BLOCKS+1][5][3], short int line_info[MAX_LINES+1][2][5], short int block_place_global[MAX_BLOCKS+1][2]);
#endif /* __IO_HPP__ */
hardware_design/test_bench/main.cpp 0 → 100755
View file @ 940a7e2c
#include <iostream>
#include <getopt.h>
#include "param.hpp"
#include "io.hpp"
#include "solver.hpp"
#include "tools.hpp"
using namespace std;
void usage() {
cout << "Usage: ./sim.exe [--output output-file] [--seed seed-value] < input-file" << endl;
exit(-1);
}
int main(int argc, char *argv[]) {
char *out_filename = NULL;
uint32_t seed_v = 214;
// Get options
struct option longopts[] = {
{"output", required_argument, NULL, 'o'},
{"seed", required_argument, NULL, 's'},
{0, 0, 0, 0}
};
int opt, optidx;
while((opt = getopt_long(argc, argv, "o:s:", longopts, &optidx)) != -1) {
switch(opt) {
case 'o':
out_filename = optarg;
break;
case 's':
sscanf(optarg, "%u", &seed_v);
break;
default:
usage();
}
}
// Init seed value
uint32_t seed[3];
srand(seed_v);
seed[0] = rand();
seed[1] = rand();
seed[2] = rand();
// W: Max width of a board (specified in a problem file)
// H: Max height of a board (specified in a problem file)
// blocks: # of blocks (specified in a problem file)
short int W, H, blocks, line_num;
// W_ext: Width of a current solution
// H_ext: Height of a current solution
short int W_ext, H_ext;
// block data
short int block_info[MAX_BLOCKS+1][5][3];
// line data
short int line_info[MAX_LINES+1][2][5];
// block positions on slot matrix
short int block_place_global[MAX_BLOCKS+1][2];
// An opt. result will be stored in the array
short int opt_result[MAX_CELLS];
// Check problem
read_problem(&W, &H, &blocks, &line_num, block_info, line_info);
extract_line_info(line_num, blocks, block_info, line_info);
// Solver body
global_placement(seed, W, H, line_num, blocks, block_info, line_info, block_place_global);
hls::stream<ap_uint<4> > state;
bool solved = solver(state, seed, &blocks, &line_num, block_info, &W_ext, &H_ext, block_place_global, opt_result);
// Check answer
if(!solved) {
cout << "Fail re-routing" << endl;
}
else {
cout << "== Answer ==" << endl;
cout << "SIZE " << W_ext << "X" << H_ext << endl;
show_result(line_num, blocks, W_ext, H_ext, opt_result);
}
if(W_ext > W || H_ext > H) {
cout << "Fail satisfying constraint T_T" << endl;
}
else {
cout << "Satisfy constraint ^_^" << endl;
if(out_filename == NULL) return 0;
cout << "Output to " << out_filename << endl;
short int block_place_basis[MAX_BLOCKS+1][2];
for(int i = 1; i <= blocks; i++) {
block_place_basis[i][0] = block_info[i][0][0];
block_place_basis[i][1] = block_info[i][0][1];
}
output_to_file(out_filename, line_num, blocks, W_ext, H_ext, opt_result, block_place_basis);
}
return 0;
}
hardware_design/test_bench/sample_Q.txt 0 → 100755
View file @ 940a7e2c
SIZE 10X10
BLOCK_NUM 8
BLOCK#1 1X4
1
+
8
7
BLOCK#2 3X2
0,8,0
7,6,+
BLOCK#3 2X3
10,0
+,0
3,9
BLOCK#4 2X2
1,2
4,+
BLOCK#5 3X2
11,+,+
0,0,3
BLOCK#6 3X2
0, +,2
5,11,0
BLOCK#7 3X2
0,10,6
9, 5,0
BLOCK#8 3X2
+,+,0
0,+,4
\ No newline at end of file
hardware_design/test_bench/tools.cpp 0 → 100755
View file @ 940a7e2c
#include "tools.hpp"
void output_to_file(char *f_name, short int line_num, short int blocks, short int wi, short int hi, short int board[], short int block_place[][2]) {
ofstream outputfile(f_name);
outputfile << "SIZE " << wi << "X" << hi << endl;
for(short int q = 0; q < hi; q++) {
for(short int p = 0; p < wi; p++) {
short int n = board[q*MAX_SIZE+p];
if(n == 0) { outputfile << 0; }
else if(n == -1) { outputfile << 0; }
else{ outputfile << n; }
if(p != wi-1) { outputfile << ", "; }
}
outputfile << endl;
}
outputfile << setfill(' ');
outputfile << dec;
for(int i = 1; i <= blocks; i++) {
outputfile << "BLOCK#" << i << " @(" << block_place[i][0] << "," << block_place[i][1] << ")" << endl;
}
outputfile.close();
}
void show_result(short int line_num, short int blocks, short int wi, short int hi, short int board[]) {
// This shows a number from 1 to 255
for(short int q = 0; q < hi; q++) {
for(short int p = 0; p < wi; p++) {
short int n = board[q*MAX_SIZE+p];
if(n == 0) { cout << "--"; }
else if(n == -1) { cout << "XX"; }
else{ cout << setfill('0') << setw(2) << hex << n; }
if(p != wi-1) { cout << " "; }
}
cout << endl;
}
cout << setfill(' ');
cout << dec;
}
hardware_design/test_bench/tools.hpp 0 → 100755
View file @ 940a7e2c
#ifndef __TOOLS_HPP__
#define __TOOLS_HPP__
using namespace std;
#include <iostream>
#include <iomanip> // for setw
#include <fstream>
#include "param.hpp"
void usage();
void output_to_file(char *f_name, short int line_num, short int blocks, short int wi, short int hi, short int board[], short int block_place[][2]);
void show_result(short int line_num, short int blocks, short int wi, short int hi, short int board[]);
#endif /* __TOOLS_HPP__ */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment