From 940a7e2cb757d4ef0db7854a13d057094f5e4331 Mon Sep 17 00:00:00 2001
From: KazushiKawamura <kazushi.kawamura@togawa.cs.waseda.ac.jp>
Date: Tue, 27 Aug 2019 00:35:48 +0900
Subject: [PATCH] upload hardware design

---
 hardware_design/190826_solver/design_1.bit    |  Bin 0 -> 4045676 bytes
 hardware_design/190826_solver/design_1.hwh    | 3729 +++++++++++++++++
 hardware_design/README.md                     |    0
 .../for_pynq_design/led_pin_assignment.xdc    |    8 +
 hardware_design/for_pynq_design/pynq_revC.tcl |  879 ++++
 hardware_design/source_code/param.hpp         |   46 +
 hardware_design/source_code/solver.cpp        | 1065 +++++
 hardware_design/source_code/solver.hpp        |   28 +
 hardware_design/test_bench/io.cpp             |  485 +++
 hardware_design/test_bench/io.hpp             |   19 +
 hardware_design/test_bench/main.cpp           |  103 +
 hardware_design/test_bench/sample_Q.txt       |   37 +
 hardware_design/test_bench/tools.cpp          |   42 +
 hardware_design/test_bench/tools.hpp          |   16 +
 14 files changed, 6457 insertions(+)
 create mode 100755 hardware_design/190826_solver/design_1.bit
 create mode 100755 hardware_design/190826_solver/design_1.hwh
 create mode 100644 hardware_design/README.md
 create mode 100755 hardware_design/for_pynq_design/led_pin_assignment.xdc
 create mode 100755 hardware_design/for_pynq_design/pynq_revC.tcl
 create mode 100755 hardware_design/source_code/param.hpp
 create mode 100755 hardware_design/source_code/solver.cpp
 create mode 100755 hardware_design/source_code/solver.hpp
 create mode 100755 hardware_design/test_bench/io.cpp
 create mode 100755 hardware_design/test_bench/io.hpp
 create mode 100755 hardware_design/test_bench/main.cpp
 create mode 100755 hardware_design/test_bench/sample_Q.txt
 create mode 100755 hardware_design/test_bench/tools.cpp
 create mode 100755 hardware_design/test_bench/tools.hpp

diff --git a/hardware_design/190826_solver/design_1.bit b/hardware_design/190826_solver/design_1.bit
new file mode 100755
index 0000000000000000000000000000000000000000..0e045ed1242d502db05b70bcc1755aca3d4e9cd3
GIT binary patch
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diff --git a/hardware_design/190826_solver/design_1.hwh b/hardware_design/190826_solver/design_1.hwh
new file mode 100755
index 0000000..5131ed4
--- /dev/null
+++ b/hardware_design/190826_solver/design_1.hwh
@@ -0,0 +1,3729 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon Aug 26 20:43:20 2019" VIVADOVERSION="2018.2">
+
+  <SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="design_1" PACKAGE="clg400" SPEEDGRADE="-1"/>
+
+  <EXTERNALPORTS>
+    <PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="DDR_cke" SIGIS="undef"/>
+    <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_n" SIGIS="clk"/>
+    <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_p" SIGIS="clk"/>
+    <PORT DIR="IO" NAME="DDR_cs_n" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="DDR_reset_n" SIGIS="rst"/>
+    <PORT DIR="IO" NAME="DDR_odt" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="DDR_ras_n" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="DDR_we_n" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="2" NAME="DDR_ba" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="14" NAME="DDR_addr" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="3" NAME="DDR_dm" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="31" NAME="DDR_dq" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_n" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_p" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef"/>
+    <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef"/>
+    <PORT DIR="O" LEFT="3" NAME="led" RIGHT="0" SIGIS="data" SIGNAME="solver_0_state_V_V">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="solver_0" PORT="state_V_V"/>
+      </CONNECTIONS>
+    </PORT>
+  </EXTERNALPORTS>
+
+  <EXTERNALINTERFACES>
+    <BUSINTERFACE BUSNAME="processing_system7_0_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR">
+      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+      <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
+      <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
+      <PARAMETER NAME="MEMORY_PART"/>
+      <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
+      <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
+      <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
+      <PARAMETER NAME="SLOT" VALUE="Single"/>
+      <PARAMETER NAME="CUSTOM_PARTS"/>
+      <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
+      <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
+      <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
+      <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
+      <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
+      <PORTMAPS>
+        <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_cas_n"/>
+        <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_cke"/>
+        <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_ck_n"/>
+        <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_ck_p"/>
+        <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_cs_n"/>
+        <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_reset_n"/>
+        <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_odt"/>
+        <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_ras_n"/>
+        <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_we_n"/>
+        <PORTMAP LOGICAL="BA" PHYSICAL="DDR_ba"/>
+        <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_addr"/>
+        <PORTMAP LOGICAL="DM" PHYSICAL="DDR_dm"/>
+        <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_dq"/>
+        <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_dqs_n"/>
+        <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_dqs_p"/>
+      </PORTMAPS>
+    </BUSINTERFACE>
+    <BUSINTERFACE BUSNAME="processing_system7_0_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR">
+      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+      <PORTMAPS>
+        <PORTMAP LOGICAL="MIO" PHYSICAL="FIXED_IO_mio"/>
+        <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="FIXED_IO_ddr_vrn"/>
+        <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="FIXED_IO_ddr_vrp"/>
+        <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="FIXED_IO_ps_srstb"/>
+        <PORTMAP LOGICAL="PS_CLK" PHYSICAL="FIXED_IO_ps_clk"/>
+        <PORTMAP LOGICAL="PS_PORB" PHYSICAL="FIXED_IO_ps_porb"/>
+      </PORTMAPS>
+    </BUSINTERFACE>
+  </EXTERNALINTERFACES>
+
+  <MODULES>
+    <MODULE BD="design_1_axi_smc_0" BDTYPE="SBD" DRIVERMODE="CORE" FULLNAME="/axi_smc" HWVERSION="1.0" INSTANCE="axi_smc" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" VLNV="xilinx.com:ip:smartconnect:1.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=smartconnect;v=v1_0;d=pg247-smartconnect.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="NUM_MI" VALUE="1"/>
+        <PARAMETER NAME="NUM_SI" VALUE="1"/>
+        <PARAMETER NAME="NUM_CLKS" VALUE="1"/>
+        <PARAMETER NAME="HAS_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="ADVANCED_PROPERTIES" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="design_1_axi_smc_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="aresetn" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_WLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_RLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="m_axi_io_data_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="solver_0_m_axi_io_data" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_processing_system7_0_0_FCLK_CLK0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_smc_M00_AXI" DATAWIDTH="64" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_processing_system7_0_0_FCLK_CLK0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE CONFIGURABLE="TRUE" FULLNAME="/processing_system7_0" HWVERSION="5.5" INSTANCE="processing_system7_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" IS_PL="FALSE" MODTYPE="processing_system7" VLNV="xilinx.com:ip:processing_system7:5.5">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=processing_system7;v=v5_3;d=pg082-processing-system7.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="" INTERFACE="S_AXI_HP0" NAME="HP0_DDR_LOWOCM" RANGE="536870912" USAGE="memory"/>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_EN_EMIO_PJTAG" VALUE="0"/>
+        <PARAMETER NAME="C_EN_EMIO_ENET0" VALUE="0"/>
+        <PARAMETER NAME="C_EN_EMIO_ENET1" VALUE="0"/>
+        <PARAMETER NAME="C_EN_EMIO_TRACE" VALUE="0"/>
+        <PARAMETER NAME="C_INCLUDE_TRACE_BUFFER" VALUE="0"/>
+        <PARAMETER NAME="C_TRACE_BUFFER_FIFO_SIZE" VALUE="128"/>
+        <PARAMETER NAME="USE_TRACE_DATA_EDGE_DETECTOR" VALUE="0"/>
+        <PARAMETER NAME="C_TRACE_PIPELINE_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C_TRACE_BUFFER_CLOCK_DELAY" VALUE="12"/>
+        <PARAMETER NAME="C_EMIO_GPIO_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_INCLUDE_ACP_TRANS_CHECK" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DEFAULT_ACP_USER_VAL" VALUE="0"/>
+        <PARAMETER NAME="C_S_AXI_ACP_ARUSER_VAL" VALUE="31"/>
+        <PARAMETER NAME="C_S_AXI_ACP_AWUSER_VAL" VALUE="31"/>
+        <PARAMETER NAME="C_M_AXI_GP0_ID_WIDTH" VALUE="12"/>
+        <PARAMETER NAME="C_M_AXI_GP0_ENABLE_STATIC_REMAP" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_GP1_ID_WIDTH" VALUE="12"/>
+        <PARAMETER NAME="C_M_AXI_GP1_ENABLE_STATIC_REMAP" VALUE="0"/>
+        <PARAMETER NAME="C_S_AXI_GP0_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="C_S_AXI_GP1_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="C_S_AXI_ACP_ID_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="C_S_AXI_HP0_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="C_S_AXI_HP0_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_S_AXI_HP1_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="C_S_AXI_HP1_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_S_AXI_HP2_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="C_S_AXI_HP2_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_S_AXI_HP3_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="C_S_AXI_HP3_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="C_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
+        <PARAMETER NAME="C_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
+        <PARAMETER NAME="C_NUM_F2P_INTR_INPUTS" VALUE="1"/>
+        <PARAMETER NAME="C_IRQ_F2P_MODE" VALUE="DIRECT"/>
+        <PARAMETER NAME="C_DQ_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_DQS_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_DM_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_MIO_PRIMITIVE" VALUE="54"/>
+        <PARAMETER NAME="C_TRACE_INTERNAL_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="C_USE_AXI_NONSECURE" VALUE="0"/>
+        <PARAMETER NAME="C_USE_M_AXI_GP0" VALUE="1"/>
+        <PARAMETER NAME="C_USE_M_AXI_GP1" VALUE="0"/>
+        <PARAMETER NAME="C_USE_S_AXI_GP0" VALUE="0"/>
+        <PARAMETER NAME="C_USE_S_AXI_GP1" VALUE="0"/>
+        <PARAMETER NAME="C_USE_S_AXI_HP0" VALUE="1"/>
+        <PARAMETER NAME="C_USE_S_AXI_HP1" VALUE="0"/>
+        <PARAMETER NAME="C_USE_S_AXI_HP2" VALUE="0"/>
+        <PARAMETER NAME="C_USE_S_AXI_HP3" VALUE="0"/>
+        <PARAMETER NAME="C_USE_S_AXI_ACP" VALUE="0"/>
+        <PARAMETER NAME="C_PS7_SI_REV" VALUE="PRODUCTION"/>
+        <PARAMETER NAME="C_FCLK_CLK0_BUF" VALUE="TRUE"/>
+        <PARAMETER NAME="C_FCLK_CLK1_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="C_FCLK_CLK2_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="C_FCLK_CLK3_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="C_PACKAGE_NAME" VALUE="clg400"/>
+        <PARAMETER NAME="C_GP0_EN_MODIFIABLE_TXN" VALUE="1"/>
+        <PARAMETER NAME="C_GP1_EN_MODIFIABLE_TXN" VALUE="1"/>
+        <PARAMETER NAME="PCW_DDR_RAM_BASEADDR" VALUE="0x00100000"/>
+        <PARAMETER NAME="PCW_DDR_RAM_HIGHADDR" VALUE="0x1FFFFFFF"/>
+        <PARAMETER NAME="PCW_UART0_BASEADDR" VALUE="0xE0000000"/>
+        <PARAMETER NAME="PCW_UART0_HIGHADDR" VALUE="0xE0000FFF"/>
+        <PARAMETER NAME="PCW_UART1_BASEADDR" VALUE="0xE0001000"/>
+        <PARAMETER NAME="PCW_UART1_HIGHADDR" VALUE="0xE0001FFF"/>
+        <PARAMETER NAME="PCW_I2C0_BASEADDR" VALUE="0xE0004000"/>
+        <PARAMETER NAME="PCW_I2C0_HIGHADDR" VALUE="0xE0004FFF"/>
+        <PARAMETER NAME="PCW_I2C1_BASEADDR" VALUE="0xE0005000"/>
+        <PARAMETER NAME="PCW_I2C1_HIGHADDR" VALUE="0xE0005FFF"/>
+        <PARAMETER NAME="PCW_SPI0_BASEADDR" VALUE="0xE0006000"/>
+        <PARAMETER NAME="PCW_SPI0_HIGHADDR" VALUE="0xE0006FFF"/>
+        <PARAMETER NAME="PCW_SPI1_BASEADDR" VALUE="0xE0007000"/>
+        <PARAMETER NAME="PCW_SPI1_HIGHADDR" VALUE="0xE0007FFF"/>
+        <PARAMETER NAME="PCW_CAN0_BASEADDR" VALUE="0xE0008000"/>
+        <PARAMETER NAME="PCW_CAN0_HIGHADDR" VALUE="0xE0008FFF"/>
+        <PARAMETER NAME="PCW_CAN1_BASEADDR" VALUE="0xE0009000"/>
+        <PARAMETER NAME="PCW_CAN1_HIGHADDR" VALUE="0xE0009FFF"/>
+        <PARAMETER NAME="PCW_GPIO_BASEADDR" VALUE="0xE000A000"/>
+        <PARAMETER NAME="PCW_GPIO_HIGHADDR" VALUE="0xE000AFFF"/>
+        <PARAMETER NAME="PCW_ENET0_BASEADDR" VALUE="0xE000B000"/>
+        <PARAMETER NAME="PCW_ENET0_HIGHADDR" VALUE="0xE000BFFF"/>
+        <PARAMETER NAME="PCW_ENET1_BASEADDR" VALUE="0xE000C000"/>
+        <PARAMETER NAME="PCW_ENET1_HIGHADDR" VALUE="0xE000CFFF"/>
+        <PARAMETER NAME="PCW_SDIO0_BASEADDR" VALUE="0xE0100000"/>
+        <PARAMETER NAME="PCW_SDIO0_HIGHADDR" VALUE="0xE0100FFF"/>
+        <PARAMETER NAME="PCW_SDIO1_BASEADDR" VALUE="0xE0101000"/>
+        <PARAMETER NAME="PCW_SDIO1_HIGHADDR" VALUE="0xE0101FFF"/>
+        <PARAMETER NAME="PCW_USB0_BASEADDR" VALUE="0xE0102000"/>
+        <PARAMETER NAME="PCW_USB0_HIGHADDR" VALUE="0xE0102fff"/>
+        <PARAMETER NAME="PCW_USB1_BASEADDR" VALUE="0xE0103000"/>
+        <PARAMETER NAME="PCW_USB1_HIGHADDR" VALUE="0xE0103fff"/>
+        <PARAMETER NAME="PCW_TTC0_BASEADDR" VALUE="0xE0104000"/>
+        <PARAMETER NAME="PCW_TTC0_HIGHADDR" VALUE="0xE0104fff"/>
+        <PARAMETER NAME="PCW_TTC1_BASEADDR" VALUE="0xE0105000"/>
+        <PARAMETER NAME="PCW_TTC1_HIGHADDR" VALUE="0xE0105fff"/>
+        <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE"/>
+        <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="525"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.91"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.040"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.058"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.009"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.033"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.223"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.212"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.085"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.092"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="15.6"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="18.8"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="16.5"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="18"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="25.8"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="25.8"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="105.056"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="66.904"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="89.1715"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="113.63"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="98.503"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="68.5855"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="90.295"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="103.977"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.4535"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.4535"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.4535"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.4535"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160"/>
+        <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.040"/>
+        <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.058"/>
+        <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.009"/>
+        <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.033"/>
+        <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY0" VALUE="0.223"/>
+        <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY1" VALUE="0.212"/>
+        <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY2" VALUE="0.085"/>
+        <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY3" VALUE="0.092"/>
+        <PARAMETER NAME="PCW_CPU_CPU_6X4X_MAX_RANGE" VALUE="667"/>
+        <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="650"/>
+        <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159"/>
+        <PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60"/>
+        <PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60"/>
+        <PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666"/>
+        <PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="-1"/>
+        <PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="-1"/>
+        <PARAMETER NAME="PCW_I2C_PERIPHERAL_FREQMHZ" VALUE="25"/>
+        <PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+        <PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+        <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+        <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+        <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+        <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+        <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+        <PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200"/>
+        <PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PCW_ACT_APU_PERIPHERAL_FREQMHZ" VALUE="650.000000"/>
+        <PARAMETER NAME="PCW_UIPARAM_ACT_DDR_FREQ_MHZ" VALUE="525.000000"/>
+        <PARAMETER NAME="PCW_ACT_DCI_PERIPHERAL_FREQMHZ" VALUE="10.096154"/>
+        <PARAMETER NAME="PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+        <PARAMETER NAME="PCW_ACT_SMC_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+        <PARAMETER NAME="PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" VALUE="125.000000"/>
+        <PARAMETER NAME="PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+        <PARAMETER NAME="PCW_ACT_USB0_PERIPHERAL_FREQMHZ" VALUE="60"/>
+        <PARAMETER NAME="PCW_ACT_USB1_PERIPHERAL_FREQMHZ" VALUE="60"/>
+        <PARAMETER NAME="PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" VALUE="50.000000"/>
+        <PARAMETER NAME="PCW_ACT_UART_PERIPHERAL_FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PCW_ACT_SPI_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+        <PARAMETER NAME="PCW_ACT_CAN_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+        <PARAMETER NAME="PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
+        <PARAMETER NAME="PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
+        <PARAMETER NAME="PCW_ACT_I2C_PERIPHERAL_FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PCW_ACT_WDT_PERIPHERAL_FREQMHZ" VALUE="108.333336"/>
+        <PARAMETER NAME="PCW_ACT_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
+        <PARAMETER NAME="PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+        <PARAMETER NAME="PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+        <PARAMETER NAME="PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100.000000"/>
+        <PARAMETER NAME="PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+        <PARAMETER NAME="PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+        <PARAMETER NAME="PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+        <PARAMETER NAME="PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="108.333336"/>
+        <PARAMETER NAME="PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="108.333336"/>
+        <PARAMETER NAME="PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="108.333336"/>
+        <PARAMETER NAME="PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="108.333336"/>
+        <PARAMETER NAME="PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="108.333336"/>
+        <PARAMETER NAME="PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="108.333336"/>
+        <PARAMETER NAME="PCW_CLK0_FREQ" VALUE="100000000"/>
+        <PARAMETER NAME="PCW_CLK1_FREQ" VALUE="10000000"/>
+        <PARAMETER NAME="PCW_CLK2_FREQ" VALUE="10000000"/>
+        <PARAMETER NAME="PCW_CLK3_FREQ" VALUE="10000000"/>
+        <PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0"/>
+        <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2"/>
+        <PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5"/>
+        <PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="20"/>
+        <PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10"/>
+        <PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5"/>
+        <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2"/>
+        <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8"/>
+        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1"/>
+        <PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="52"/>
+        <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="2"/>
+        <PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5"/>
+        <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1"/>
+        <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="26"/>
+        <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="20"/>
+        <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="21"/>
+        <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1300.000"/>
+        <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000"/>
+        <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1050.000"/>
+        <PARAMETER NAME="PCW_SMC_PERIPHERAL_VALID" VALUE="0"/>
+        <PARAMETER NAME="PCW_SDIO_PERIPHERAL_VALID" VALUE="1"/>
+        <PARAMETER NAME="PCW_SPI_PERIPHERAL_VALID" VALUE="0"/>
+        <PARAMETER NAME="PCW_CAN_PERIPHERAL_VALID" VALUE="0"/>
+        <PARAMETER NAME="PCW_UART_PERIPHERAL_VALID" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_EMIO_CAN0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_CAN1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_ENET0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_ENET1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_PTP_ENET0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_PTP_ENET1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_GPIO" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_I2C0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_I2C1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_PJTAG" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_SDIO0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_CD_SDIO0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_WP_SDIO0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_SDIO1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_CD_SDIO1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_WP_SDIO1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_SPI0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_SPI1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_UART0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_UART1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_MODEM_UART0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_MODEM_UART1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_TTC0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_TTC1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_WDT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_TRACE" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1"/>
+        <PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="1"/>
+        <PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0"/>
+        <PARAMETER NAME="PCW_M_AXI_GP0_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PCW_M_AXI_GP1_FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PCW_S_AXI_GP0_FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PCW_S_AXI_GP1_FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PCW_S_AXI_ACP_FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PCW_S_AXI_HP0_FREQMHZ" VALUE="100"/>
+        <PARAMETER NAME="PCW_S_AXI_HP1_FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PCW_S_AXI_HP2_FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PCW_S_AXI_HP3_FREQMHZ" VALUE="10"/>
+        <PARAMETER NAME="PCW_USE_DMA0" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_DMA1" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_DMA2" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_DMA3" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_TRACE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_PIPELINE_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="PCW_INCLUDE_TRACE_BUFFER" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_BUFFER_FIFO_SIZE" VALUE="128"/>
+        <PARAMETER NAME="PCW_USE_TRACE_DATA_EDGE_DETECTOR" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_BUFFER_CLOCK_DELAY" VALUE="12"/>
+        <PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0"/>
+        <PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_USE_DEBUG" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_CR_FABRIC" VALUE="1"/>
+        <PARAMETER NAME="PCW_USE_AXI_FABRIC_IDLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_DDR_BYPASS" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_FABRIC_INTERRUPT" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_PROC_EVENT_BUS" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_EXPANDED_IOP" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_HIGH_OCM" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_PS_SLCR_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_EXPANDED_PS_SLCR_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_CORESIGHT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_EMIO_SRAM_INT" VALUE="0"/>
+        <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="PCW_GP0_NUM_WRITE_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PCW_GP0_NUM_READ_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PCW_GP1_NUM_WRITE_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PCW_GP1_NUM_READ_THREADS" VALUE="4"/>
+        <PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200"/>
+        <PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200"/>
+        <PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0"/>
+        <PARAMETER NAME="PCW_M_AXI_GP0_ID_WIDTH" VALUE="12"/>
+        <PARAMETER NAME="PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" VALUE="0"/>
+        <PARAMETER NAME="PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" VALUE="0"/>
+        <PARAMETER NAME="PCW_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
+        <PARAMETER NAME="PCW_M_AXI_GP1_ID_WIDTH" VALUE="12"/>
+        <PARAMETER NAME="PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" VALUE="0"/>
+        <PARAMETER NAME="PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" VALUE="0"/>
+        <PARAMETER NAME="PCW_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
+        <PARAMETER NAME="PCW_S_AXI_GP0_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="PCW_S_AXI_GP1_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="PCW_S_AXI_ACP_ID_WIDTH" VALUE="3"/>
+        <PARAMETER NAME="PCW_INCLUDE_ACP_TRANS_CHECK" VALUE="0"/>
+        <PARAMETER NAME="PCW_USE_DEFAULT_ACP_USER_VAL" VALUE="0"/>
+        <PARAMETER NAME="PCW_S_AXI_ACP_ARUSER_VAL" VALUE="31"/>
+        <PARAMETER NAME="PCW_S_AXI_ACP_AWUSER_VAL" VALUE="31"/>
+        <PARAMETER NAME="PCW_S_AXI_HP0_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="PCW_S_AXI_HP1_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="PCW_S_AXI_HP2_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="PCW_S_AXI_HP3_ID_WIDTH" VALUE="6"/>
+        <PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64"/>
+        <PARAMETER NAME="PCW_NUM_F2P_INTR_INPUTS" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_DDR" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_SMC" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_QSPI" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_CAN0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_CAN1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_ENET0" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_ENET1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_GPIO" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_I2C0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_I2C1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_PJTAG" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_SDIO0" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_SDIO1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_SPI0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_SPI1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_UART0" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_UART1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_MODEM_UART0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_MODEM_UART1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_TTC0" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_TTC1" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_WDT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_TRACE" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_USB0" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_USB1" VALUE="0"/>
+        <PARAMETER NAME="PCW_DQ_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="PCW_DQS_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="PCW_DM_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="PCW_MIO_PRIMITIVE" VALUE="54"/>
+        <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_RST0_PORT" VALUE="1"/>
+        <PARAMETER NAME="PCW_EN_RST1_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_RST2_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_RST3_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_CLKTRIG0_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_CLKTRIG1_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_CLKTRIG2_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_EN_CLKTRIG3_PORT" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC_ABORT_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC0_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC1_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC2_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC3_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC4_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC5_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC6_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_DMAC7_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_SMC_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_QSPI_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_CTI_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_GPIO_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_USB0_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_ENET0_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_SDIO0_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_I2C0_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_SPI0_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_UART0_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_CAN0_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_USB1_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_ENET1_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_SDIO1_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_I2C1_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_SPI1_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_UART1_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_P2F_CAN1_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_IRQ_F2P_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT"/>
+        <PARAMETER NAME="PCW_CORE0_FIQ_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_CORE0_IRQ_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_CORE1_FIQ_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_CORE1_IRQ_INTR" VALUE="0"/>
+        <PARAMETER NAME="PCW_VALUE_SILVERSION" VALUE="3"/>
+        <PARAMETER NAME="PCW_GP0_EN_MODIFIABLE_TXN" VALUE="1"/>
+        <PARAMETER NAME="PCW_GP1_EN_MODIFIABLE_TXN" VALUE="1"/>
+        <PARAMETER NAME="PCW_IMPORT_BOARD_PRESET" VALUE="None"/>
+        <PARAMETER NAME="PCW_PERIPHERAL_BOARD_PRESET" VALUE="None"/>
+        <PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="16 Bit"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J256M16 RE-125"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0"/>
+        <PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0"/>
+        <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)"/>
+        <PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2"/>
+        <PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15"/>
+        <PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2"/>
+        <PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6"/>
+        <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6"/>
+        <PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4"/>
+        <PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8"/>
+        <PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF"/>
+        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27"/>
+        <PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53"/>
+        <PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin"/>
+        <PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="MIO 9"/>
+        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45"/>
+        <PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 47"/>
+        <PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 14 .. 15"/>
+        <PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2"/>
+        <PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39"/>
+        <PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin"/>
+        <PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 46"/>
+        <PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO"/>
+        <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="&lt;Select>"/>
+        <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1"/>
+        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps"/>
+        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps"/>
+        <PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL"/>
+        <PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL"/>
+        <PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External"/>
+        <PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External"/>
+        <PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External"/>
+        <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+        <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+        <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+        <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+        <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+        <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+        <PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+        <PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL"/>
+        <PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+        <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low"/>
+        <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low"/>
+        <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low"/>
+        <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled"/>
+        <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled"/>
+        <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled"/>
+        <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled"/>
+        <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled"/>
+        <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled"/>
+        <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled"/>
+        <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V"/>
+        <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="in"/>
+        <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out"/>
+        <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled"/>
+        <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V"/>
+        <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout"/>
+        <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow"/>
+        <PARAMETER NAME="preset" VALUE="None"/>
+        <PARAMETER NAME="PCW_UIPARAM_GENERATE_SUMMARY" VALUE="NA"/>
+        <PARAMETER NAME="PCW_MIO_TREE_PERIPHERALS" VALUE="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
+        <PARAMETER NAME="PCW_MIO_TREE_SIGNALS" VALUE="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
+        <PARAMETER NAME="PCW_PS7_SI_REV" VALUE="PRODUCTION"/>
+        <PARAMETER NAME="PCW_FPGA_FCLK0_ENABLE" VALUE="1"/>
+        <PARAMETER NAME="PCW_FPGA_FCLK1_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_FPGA_FCLK2_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_FPGA_FCLK3_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0"/>
+        <PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1"/>
+        <PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0"/>
+        <PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1"/>
+        <PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1"/>
+        <PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1"/>
+        <PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1"/>
+        <PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1"/>
+        <PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11"/>
+        <PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11"/>
+        <PARAMETER NAME="PCW_SMC_CYCLE_T0" VALUE="NA"/>
+        <PARAMETER NAME="PCW_SMC_CYCLE_T1" VALUE="NA"/>
+        <PARAMETER NAME="PCW_SMC_CYCLE_T2" VALUE="NA"/>
+        <PARAMETER NAME="PCW_SMC_CYCLE_T3" VALUE="NA"/>
+        <PARAMETER NAME="PCW_SMC_CYCLE_T4" VALUE="NA"/>
+        <PARAMETER NAME="PCW_SMC_CYCLE_T5" VALUE="NA"/>
+        <PARAMETER NAME="PCW_SMC_CYCLE_T6" VALUE="NA"/>
+        <PARAMETER NAME="PCW_PACKAGE_NAME" VALUE="clg400"/>
+        <PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="design_1_processing_system7_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x1FFFFFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="1" NAME="USB0_PORT_INDCTL" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="USB0_VBUS_PWRSELECT" SIGIS="undef"/>
+        <PORT DIR="I" NAME="USB0_VBUS_PWRFAULT" SIGIS="undef"/>
+        <PORT DIR="O" NAME="M_AXI_GP0_ARVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_GP0_AWVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_GP0_BREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_GP0_RREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_GP0_WLAST" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WLAST">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_GP0_WVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_ARID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_AWID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_WID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARBURST">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_ARLOCK" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARLOCK">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARSIZE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWBURST">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_AWLOCK" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWLOCK">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWSIZE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARPROT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWPROT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARADDR">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWADDR">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WDATA">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARCACHE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARLEN">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARQOS">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWCACHE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWLEN">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWQOS">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WSTRB">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="M_AXI_GP0_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_GP0_ARREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_GP0_AWREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_GP0_BVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_GP0_RLAST" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RLAST">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_GP0_RVALID" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_GP0_WREADY" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="11" NAME="M_AXI_GP0_BID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_bid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="11" NAME="M_AXI_GP0_RID" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BRESP">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RRESP">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M_AXI_GP0_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RDATA">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_HP0_ARREADY" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_HP0_AWREADY" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_HP0_BVALID" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_HP0_RLAST" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_HP0_RVALID" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_HP0_WREADY" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S_AXI_HP0_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S_AXI_HP0_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="5" NAME="S_AXI_HP0_BID" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="5" NAME="S_AXI_HP0_RID" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="63" NAME="S_AXI_HP0_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="S_AXI_HP0_RCOUNT" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="7" NAME="S_AXI_HP0_WCOUNT" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="2" NAME="S_AXI_HP0_RACOUNT" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="5" NAME="S_AXI_HP0_WACOUNT" RIGHT="0" SIGIS="undef"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="S_AXI_HP0_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_HP0_ARVALID" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_HP0_AWVALID" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_HP0_BREADY" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_HP0_RDISSUECAP1_EN" SIGIS="undef"/>
+        <PORT DIR="I" NAME="S_AXI_HP0_RREADY" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_HP0_WLAST" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_HP0_WRISSUECAP1_EN" SIGIS="undef"/>
+        <PORT DIR="I" NAME="S_AXI_HP0_WVALID" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S_AXI_HP0_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S_AXI_HP0_ARLOCK" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S_AXI_HP0_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S_AXI_HP0_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S_AXI_HP0_AWLOCK" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S_AXI_HP0_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S_AXI_HP0_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S_AXI_HP0_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S_AXI_HP0_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S_AXI_HP0_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="5" NAME="S_AXI_HP0_ARID" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="5" NAME="S_AXI_HP0_AWID" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="5" NAME="S_AXI_HP0_WID" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="63" NAME="S_AXI_HP0_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="7" NAME="S_AXI_HP0_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="O" NAME="FCLK_CLK0" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="ap_clk"/>
+            <CONNECTION INSTANCE="axi_smc" PORT="aclk"/>
+            <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="slowest_sync_clk"/>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ACLK"/>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ACLK"/>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_ACLK"/>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_ACLK"/>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="ACLK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="FCLK_RESET0_N" SIGIS="rst" SIGNAME="processing_system7_0_FCLK_RESET0_N">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="ext_reset_in"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="IO" LEFT="53" NAME="MIO" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="DDR_CAS_n" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="DDR_CKE" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="DDR_Clk_n" SIGIS="clk"/>
+        <PORT DIR="IO" NAME="DDR_Clk" SIGIS="clk"/>
+        <PORT DIR="IO" NAME="DDR_CS_n" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="DDR_DRSTB" SIGIS="rst"/>
+        <PORT DIR="IO" NAME="DDR_ODT" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="DDR_RAS_n" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="DDR_WEB" SIGIS="undef"/>
+        <PORT DIR="IO" LEFT="2" NAME="DDR_BankAddr" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" LEFT="14" NAME="DDR_Addr" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="DDR_VRN" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="DDR_VRP" SIGIS="undef"/>
+        <PORT DIR="IO" LEFT="3" NAME="DDR_DM" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" LEFT="31" NAME="DDR_DQ" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" LEFT="3" NAME="DDR_DQS_n" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" LEFT="3" NAME="DDR_DQS" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="PS_SRSTB" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="PS_CLK" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="PS_PORB" SIGIS="undef"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="processing_system7_0_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR" VLNV="xilinx.com:interface:ddrx:1.0">
+          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+          <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
+          <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
+          <PARAMETER NAME="MEMORY_PART"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
+          <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
+          <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
+          <PARAMETER NAME="SLOT" VALUE="Single"/>
+          <PARAMETER NAME="CUSTOM_PARTS"/>
+          <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
+          <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
+          <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
+          <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
+          <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_CAS_n"/>
+            <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_CKE"/>
+            <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_Clk_n"/>
+            <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_Clk"/>
+            <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_CS_n"/>
+            <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_DRSTB"/>
+            <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_ODT"/>
+            <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_RAS_n"/>
+            <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_WEB"/>
+            <PORTMAP LOGICAL="BA" PHYSICAL="DDR_BankAddr"/>
+            <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_Addr"/>
+            <PORTMAP LOGICAL="DM" PHYSICAL="DDR_DM"/>
+            <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_DQ"/>
+            <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_DQS_n"/>
+            <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_DQS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="processing_system7_0_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR" VLNV="xilinx.com:display_processing_system7:fixedio:1.0">
+          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="MIO" PHYSICAL="MIO"/>
+            <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="DDR_VRN"/>
+            <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="DDR_VRP"/>
+            <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="PS_SRSTB"/>
+            <PORTMAP LOGICAL="PS_CLK" PHYSICAL="PS_CLK"/>
+            <PORTMAP LOGICAL="PS_PORB" PHYSICAL="PS_PORB"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" NAME="USBIND_0" TYPE="INITIATOR" VLNV="xilinx.com:display_processing_system7:usbctrl:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="PORT_INDCTL" PHYSICAL="USB0_PORT_INDCTL"/>
+            <PORTMAP LOGICAL="VBUS_PWRSELECT" PHYSICAL="USB0_VBUS_PWRSELECT"/>
+            <PORTMAP LOGICAL="VBUS_PWRFAULT" PHYSICAL="USB0_VBUS_PWRFAULT"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" NAME="S_AXI_HP0_FIFO_CTRL" TYPE="TARGET" VLNV="xilinx.com:display_processing_system7:hpstatusctrl:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="RCOUNT" PHYSICAL="S_AXI_HP0_RCOUNT"/>
+            <PORTMAP LOGICAL="WCOUNT" PHYSICAL="S_AXI_HP0_WCOUNT"/>
+            <PORTMAP LOGICAL="RACOUNT" PHYSICAL="S_AXI_HP0_RACOUNT"/>
+            <PORTMAP LOGICAL="WACOUNT" PHYSICAL="S_AXI_HP0_WACOUNT"/>
+            <PORTMAP LOGICAL="RDISSUECAPEN" PHYSICAL="S_AXI_HP0_RDISSUECAP1_EN"/>
+            <PORTMAP LOGICAL="WRISSUECAPEN" PHYSICAL="S_AXI_HP0_WRISSUECAP1_EN"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="processing_system7_0_M_AXI_GP0" DATAWIDTH="32" NAME="M_AXI_GP0" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="12"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_processing_system7_0_0_FCLK_CLK0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M_AXI_GP0_ARVALID"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M_AXI_GP0_AWVALID"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M_AXI_GP0_BREADY"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M_AXI_GP0_RREADY"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="M_AXI_GP0_WLAST"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M_AXI_GP0_WVALID"/>
+            <PORTMAP LOGICAL="ARID" PHYSICAL="M_AXI_GP0_ARID"/>
+            <PORTMAP LOGICAL="AWID" PHYSICAL="M_AXI_GP0_AWID"/>
+            <PORTMAP LOGICAL="WID" PHYSICAL="M_AXI_GP0_WID"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M_AXI_GP0_ARBURST"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M_AXI_GP0_ARLOCK"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M_AXI_GP0_ARSIZE"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M_AXI_GP0_AWBURST"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M_AXI_GP0_AWLOCK"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M_AXI_GP0_AWSIZE"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M_AXI_GP0_ARPROT"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M_AXI_GP0_AWPROT"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M_AXI_GP0_ARADDR"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M_AXI_GP0_AWADDR"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M_AXI_GP0_WDATA"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M_AXI_GP0_ARCACHE"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M_AXI_GP0_ARLEN"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M_AXI_GP0_ARQOS"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M_AXI_GP0_AWCACHE"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M_AXI_GP0_AWLEN"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M_AXI_GP0_AWQOS"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M_AXI_GP0_WSTRB"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M_AXI_GP0_ARREADY"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M_AXI_GP0_AWREADY"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M_AXI_GP0_BVALID"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="M_AXI_GP0_RLAST"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M_AXI_GP0_RVALID"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M_AXI_GP0_WREADY"/>
+            <PORTMAP LOGICAL="BID" PHYSICAL="M_AXI_GP0_BID"/>
+            <PORTMAP LOGICAL="RID" PHYSICAL="M_AXI_GP0_RID"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M_AXI_GP0_BRESP"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M_AXI_GP0_RRESP"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M_AXI_GP0_RDATA"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_smc_M00_AXI" DATAWIDTH="64" NAME="S_AXI_HP0" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_processing_system7_0_0_FCLK_CLK0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S_AXI_HP0_ARREADY"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S_AXI_HP0_AWREADY"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="S_AXI_HP0_BVALID"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="S_AXI_HP0_RLAST"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="S_AXI_HP0_RVALID"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="S_AXI_HP0_WREADY"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="S_AXI_HP0_BRESP"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="S_AXI_HP0_RRESP"/>
+            <PORTMAP LOGICAL="BID" PHYSICAL="S_AXI_HP0_BID"/>
+            <PORTMAP LOGICAL="RID" PHYSICAL="S_AXI_HP0_RID"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="S_AXI_HP0_RDATA"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S_AXI_HP0_ARVALID"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S_AXI_HP0_AWVALID"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="S_AXI_HP0_BREADY"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="S_AXI_HP0_RREADY"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="S_AXI_HP0_WLAST"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="S_AXI_HP0_WVALID"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S_AXI_HP0_ARBURST"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S_AXI_HP0_ARLOCK"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S_AXI_HP0_ARSIZE"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S_AXI_HP0_AWBURST"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S_AXI_HP0_AWLOCK"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S_AXI_HP0_AWSIZE"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S_AXI_HP0_ARPROT"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S_AXI_HP0_AWPROT"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S_AXI_HP0_ARADDR"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S_AXI_HP0_AWADDR"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S_AXI_HP0_ARCACHE"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S_AXI_HP0_ARLEN"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S_AXI_HP0_ARQOS"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S_AXI_HP0_AWCACHE"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S_AXI_HP0_AWLEN"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S_AXI_HP0_AWQOS"/>
+            <PORTMAP LOGICAL="ARID" PHYSICAL="S_AXI_HP0_ARID"/>
+            <PORTMAP LOGICAL="AWID" PHYSICAL="S_AXI_HP0_AWID"/>
+            <PORTMAP LOGICAL="WID" PHYSICAL="S_AXI_HP0_WID"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="S_AXI_HP0_WDATA"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S_AXI_HP0_WSTRB"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_S_AXI_AXILITES_BASEADDR" BASEVALUE="0x43C00000" HIGHNAME="C_S_AXI_AXILITES_HIGHADDR" HIGHVALUE="0x43C0FFFF" INSTANCE="solver_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi_AXILiteS"/>
+      </MEMORYMAP>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="solver_0"/>
+      </PERIPHERALS>
+    </MODULE>
+    <MODULE FULLNAME="/ps7_0_axi_periph" HWVERSION="2.1" INSTANCE="ps7_0_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="NUM_SI" VALUE="1"/>
+        <PARAMETER NAME="NUM_MI" VALUE="1"/>
+        <PARAMETER NAME="STRATEGY" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+        <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+        <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
+        <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M00_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M01_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M02_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M03_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M04_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M05_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M06_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M07_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M08_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M09_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M10_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M11_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M12_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M13_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M14_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M15_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M16_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M17_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M18_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M19_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M20_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M21_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M22_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M23_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M24_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M25_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M26_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M27_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M28_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M29_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M30_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M31_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M32_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M33_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M34_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M35_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M36_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M37_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M38_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M39_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M40_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M41_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M42_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M43_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M44_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M45_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+        <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="design_1_ps7_0_axi_periph_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_100M_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="interconnect_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WLAST">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="11" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="11" NAME="S00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARBURST">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARLOCK">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARSIZE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWBURST">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWBURST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWLOCK">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWLOCK"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWSIZE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWSIZE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARPROT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWPROT">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARADDR">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWADDR">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WDATA">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARCACHE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARLEN">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARQOS">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWCACHE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWCACHE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWLEN">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWLEN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWQOS">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWQOS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WSTRB">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_ARREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_AWREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RLAST">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RLAST"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_WREADY">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="11" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="11" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_BRESP">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RRESP">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_M_AXI_GP0_RDATA">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="s_axi_AXILiteS_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="processing_system7_0_M_AXI_GP0" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
+            <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
+            <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
+            <PORTMAP LOGICAL="WID" PHYSICAL="S00_AXI_wid"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+            <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
+            <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ps7_0_axi_periph_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE FULLNAME="/rst_ps7_0_100M" HWVERSION="5.0" INSTANCE="rst_ps7_0_100M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
+        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
+        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
+        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="design_1_rst_ps7_0_100M_0"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ext_reset_in" SIGIS="rst" SIGNAME="processing_system7_0_FCLK_RESET0_N">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_RESET0_N"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="aux_reset_in" SIGIS="rst"/>
+        <PORT DIR="I" NAME="mb_debug_sys_rst" SIGIS="rst"/>
+        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
+        <PORT DIR="O" NAME="mb_reset" SIGIS="rst"/>
+        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" RIGHT="0" SIGIS="rst"/>
+        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" RIGHT="0" SIGIS="rst"/>
+        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_ps7_0_100M_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="ap_rst_n"/>
+            <CONNECTION INSTANCE="axi_smc" PORT="aresetn"/>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_ARESETN"/>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="S00_ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE FULLNAME="/solver_0" HWVERSION="1.0" INSTANCE="solver_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="solver" VLNV="xilinx.com:hls:solver:1.0">
+      <DOCUMENTS/>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_AXILiteS" NAME="Reg" RANGE="65536" USAGE="register">
+          <REGISTERS>
+            <REGISTER NAME="CTRL">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Control signals"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="AP_START">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Control signal Register for 'ap_start'."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="modify"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="AP_DONE">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Control signal Register for 'ap_done'."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="AP_IDLE">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Control signal Register for 'ap_idle'."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="AP_READY">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Control signal Register for 'ap_ready'."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="RESERVED_1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reserved.  0s on read."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="3"/>
+                </FIELD>
+                <FIELD NAME="AUTO_RESTART">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Control signal Register for 'auto_restart'."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="modify"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="RESERVED_2">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reserved.  0s on read."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="24"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="GIER">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Global Interrupt Enable Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="Enable">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Master enable for the device interrupt output to the system interrupt controller: 0 = Disabled, 1 = Enabled"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="modify"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="RESERVED">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reserved.  0s on read."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="31"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IP_IER">
+              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Enable Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="CHAN0_INT_EN">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Channel 0 (ap_done) Interrupt.  0 = Disabled, 1 = Enabled."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="modify"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CHAN1_INT_EN">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Channel 1 (ap_ready) Interrupt.  0 = Disabled, 1 = Enabled."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="modify"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="RESERVED">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reserved.  0s on read."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="30"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IP_ISR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="CHAN0_INT_ST">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Channel 0 (ap_done) Interrupt Status. 0 = No Channel 0 input interrupt, 1 = Channel 0 input interrup"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CHAN1_INT_ST">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Channel 1 (ap_ready) Interrupt Status. 0 = No Channel 1 input interrupt, 1 = Channel 1 input interrup"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="RESERVED">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reserved.  0s on read."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="30"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="ap_return">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ap_return"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="ap_return">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 0 to 0 Data signal of ap_return"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="RESERVED">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reserved.  0s on read."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="31"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="seed">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of seed"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="seed">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 Data signal of seed"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="pbnum">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of pbnum"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="32"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="pbnum">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 Data signal of pbnum"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="plnum">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of plnum"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="40"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="plnum">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 Data signal of plnum"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="block_info">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of block_info"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="48"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="block_info">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 Data signal of block_info"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="pwi">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of pwi"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="56"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="pwi">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 Data signal of pwi"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="phi">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of phi"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="64"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="phi">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 Data signal of phi"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="block_place_global">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of block_place_global"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="72"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="block_place_global">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 Data signal of block_place_global"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="opt_result">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of opt_result"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="80"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="opt_result">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 Data signal of opt_result"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+          </REGISTERS>
+        </ADDRESSBLOCK>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_S_AXI_AXILITES_ADDR_WIDTH" VALUE="7"/>
+        <PARAMETER NAME="C_S_AXI_AXILITES_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_AWUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_ARUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_WUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_RUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_BUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_USER_VALUE" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_PROT_VALUE" VALUE="&quot;000&quot;"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_CACHE_VALUE" VALUE="&quot;0011&quot;"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_ENABLE_ID_PORTS" VALUE="false"/>
+        <PARAMETER NAME="C_M_AXI_IO_DATA_ENABLE_USER_PORTS" VALUE="false"/>
+        <PARAMETER NAME="Component_Name" VALUE="design_1_solver_0_0"/>
+        <PARAMETER NAME="clk_period" VALUE="10"/>
+        <PARAMETER NAME="machine" VALUE="64"/>
+        <PARAMETER NAME="combinational" VALUE="0"/>
+        <PARAMETER NAME="latency" VALUE="207874"/>
+        <PARAMETER NAME="II" VALUE="x"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_S_AXI_AXILITES_BASEADDR" VALUE="0x43C00000"/>
+        <PARAMETER NAME="C_S_AXI_AXILITES_HIGHADDR" VALUE="0x43C0FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" NAME="state_V_V_ap_vld" SIGIS="undef" SIGNAME="solver_0_state_V_V_ap_vld">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="state_V_V_ap_ack"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="state_V_V_ap_ack" SIGIS="undef" SIGNAME="solver_0_state_V_V_ap_vld">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="solver_0" PORT="state_V_V_ap_vld"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="6" NAME="s_axi_AXILiteS_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_AXILiteS_AWVALID" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_AXILiteS_AWREADY" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_AXILiteS_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_AXILiteS_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_AXILiteS_WVALID" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_AXILiteS_WREADY" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_AXILiteS_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_AXILiteS_BVALID" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_AXILiteS_BREADY" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="6" NAME="s_axi_AXILiteS_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_AXILiteS_ARVALID" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_AXILiteS_ARREADY" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_AXILiteS_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_AXILiteS_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_AXILiteS_RVALID" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_AXILiteS_RREADY" SIGIS="undef" SIGNAME="ps7_0_axi_periph_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ps7_0_axi_periph" PORT="M00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="ap_clk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ap_rst_n" SIGIS="rst" SIGNAME="rst_ps7_0_100M_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="rst_ps7_0_100M" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT"/>
+        <PORT DIR="O" LEFT="31" NAME="m_axi_io_data_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axi_io_data_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_io_data_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="m_axi_io_data_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="m_axi_io_data_AWLOCK" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_io_data_AWREGION" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_io_data_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_io_data_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_io_data_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_io_data_AWVALID" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_io_data_AWREADY" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="m_axi_io_data_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_io_data_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_io_data_WLAST" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_wlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_io_data_WVALID" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_io_data_WREADY" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="m_axi_io_data_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_io_data_BVALID" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_io_data_BREADY" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="m_axi_io_data_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="7" NAME="m_axi_io_data_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arlen">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arlen"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_io_data_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arsize">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arsize"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="m_axi_io_data_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arburst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arburst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="m_axi_io_data_ARLOCK" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arlock">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arlock"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_io_data_ARREGION" RIGHT="0" SIGIS="undef"/>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_io_data_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arcache">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arcache"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="m_axi_io_data_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="m_axi_io_data_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arqos">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arqos"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_io_data_ARVALID" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_io_data_ARREADY" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="m_axi_io_data_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="m_axi_io_data_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_io_data_RLAST" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rlast">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rlast"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="m_axi_io_data_RVALID" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="m_axi_io_data_RREADY" SIGIS="undef" SIGNAME="axi_smc_S00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="state_V_V" RIGHT="0" SIGIS="data" SIGNAME="solver_0_state_V_V">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="led"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="ps7_0_axi_periph_M00_AXI" DATAWIDTH="32" NAME="s_axi_AXILiteS" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="LAYERED_METADATA" VALUE="xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_processing_system7_0_0_FCLK_CLK0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_AXILiteS_AWADDR"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_AXILiteS_AWVALID"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_AXILiteS_AWREADY"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_AXILiteS_WDATA"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_AXILiteS_WSTRB"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_AXILiteS_WVALID"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_AXILiteS_WREADY"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_AXILiteS_BRESP"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_AXILiteS_BVALID"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_AXILiteS_BREADY"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_AXILiteS_ARADDR"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_AXILiteS_ARVALID"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_AXILiteS_ARREADY"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_AXILiteS_RDATA"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_AXILiteS_RRESP"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_AXILiteS_RVALID"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_AXILiteS_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="solver_0_m_axi_io_data" DATAWIDTH="32" NAME="m_axi_io_data" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
+          <PARAMETER NAME="MAX_READ_BURST_LENGTH" VALUE="16"/>
+          <PARAMETER NAME="MAX_WRITE_BURST_LENGTH" VALUE="16"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="1"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.000"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_processing_system7_0_0_FCLK_CLK0"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_io_data_AWADDR"/>
+            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_io_data_AWLEN"/>
+            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_io_data_AWSIZE"/>
+            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_io_data_AWBURST"/>
+            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="m_axi_io_data_AWLOCK"/>
+            <PORTMAP LOGICAL="AWREGION" PHYSICAL="m_axi_io_data_AWREGION"/>
+            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_io_data_AWCACHE"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_io_data_AWPROT"/>
+            <PORTMAP LOGICAL="AWQOS" PHYSICAL="m_axi_io_data_AWQOS"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_io_data_AWVALID"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_io_data_AWREADY"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_io_data_WDATA"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_io_data_WSTRB"/>
+            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_io_data_WLAST"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_io_data_WVALID"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_io_data_WREADY"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_io_data_BRESP"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_io_data_BVALID"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_io_data_BREADY"/>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="m_axi_io_data_ARADDR"/>
+            <PORTMAP LOGICAL="ARLEN" PHYSICAL="m_axi_io_data_ARLEN"/>
+            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="m_axi_io_data_ARSIZE"/>
+            <PORTMAP LOGICAL="ARBURST" PHYSICAL="m_axi_io_data_ARBURST"/>
+            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="m_axi_io_data_ARLOCK"/>
+            <PORTMAP LOGICAL="ARREGION" PHYSICAL="m_axi_io_data_ARREGION"/>
+            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="m_axi_io_data_ARCACHE"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="m_axi_io_data_ARPROT"/>
+            <PORTMAP LOGICAL="ARQOS" PHYSICAL="m_axi_io_data_ARQOS"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="m_axi_io_data_ARVALID"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="m_axi_io_data_ARREADY"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="m_axi_io_data_RDATA"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="m_axi_io_data_RRESP"/>
+            <PORTMAP LOGICAL="RLAST" PHYSICAL="m_axi_io_data_RLAST"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="m_axi_io_data_RVALID"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="m_axi_io_data_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE ADDRESSBLOCK="HP0_DDR_LOWOCM" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="processing_system7_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="m_axi_io_data" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0"/>
+      </MEMORYMAP>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="processing_system7_0"/>
+      </PERIPHERALS>
+    </MODULE>
+  </MODULES>
+
+</EDKSYSTEM>
diff --git a/hardware_design/README.md b/hardware_design/README.md
new file mode 100644
index 0000000..e69de29
diff --git a/hardware_design/for_pynq_design/led_pin_assignment.xdc b/hardware_design/for_pynq_design/led_pin_assignment.xdc
new file mode 100755
index 0000000..3b622a1
--- /dev/null
+++ b/hardware_design/for_pynq_design/led_pin_assignment.xdc
@@ -0,0 +1,8 @@
+set_property PACKAGE_PIN R14 [get_ports {led[0]}]
+set_property PACKAGE_PIN P14 [get_ports {led[1]}]
+set_property PACKAGE_PIN N16 [get_ports {led[2]}]
+set_property PACKAGE_PIN M14 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
diff --git a/hardware_design/for_pynq_design/pynq_revC.tcl b/hardware_design/for_pynq_design/pynq_revC.tcl
new file mode 100755
index 0000000..efee522
--- /dev/null
+++ b/hardware_design/for_pynq_design/pynq_revC.tcl
@@ -0,0 +1,879 @@
+proc getPresetInfo {} {
+  return [dict create name {PYNQ} description {PYNQ}  vlnv xilinx.com:ip:processing_system7:5.5 display_name {PYNQ} ]
+}
+
+proc validate_preset {IPINST} { return true }
+
+
+proc apply_preset {IPINST} {
+return [dict create \
+    CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000}  \
+    CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF}  \
+    CONFIG.PCW_UART0_BASEADDR {0xE0000000}  \
+    CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF}  \
+    CONFIG.PCW_UART1_BASEADDR {0xE0001000}  \
+    CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF}  \
+    CONFIG.PCW_I2C0_BASEADDR {0xE0004000}  \
+    CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF}  \
+    CONFIG.PCW_I2C1_BASEADDR {0xE0005000}  \
+    CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF}  \
+    CONFIG.PCW_SPI0_BASEADDR {0xE0006000}  \
+    CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF}  \
+    CONFIG.PCW_SPI1_BASEADDR {0xE0007000}  \
+    CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF}  \
+    CONFIG.PCW_CAN0_BASEADDR {0xE0008000}  \
+    CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF}  \
+    CONFIG.PCW_CAN1_BASEADDR {0xE0009000}  \
+    CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF}  \
+    CONFIG.PCW_GPIO_BASEADDR {0xE000A000}  \
+    CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF}  \
+    CONFIG.PCW_ENET0_BASEADDR {0xE000B000}  \
+    CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF}  \
+    CONFIG.PCW_ENET1_BASEADDR {0xE000C000}  \
+    CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF}  \
+    CONFIG.PCW_SDIO0_BASEADDR {0xE0100000}  \
+    CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF}  \
+    CONFIG.PCW_SDIO1_BASEADDR {0xE0101000}  \
+    CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF}  \
+    CONFIG.PCW_USB0_BASEADDR {0xE0102000}  \
+    CONFIG.PCW_USB0_HIGHADDR {0xE0102fff}  \
+    CONFIG.PCW_USB1_BASEADDR {0xE0103000}  \
+    CONFIG.PCW_USB1_HIGHADDR {0xE0103fff}  \
+    CONFIG.PCW_TTC0_BASEADDR {0xE0104000}  \
+    CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff}  \
+    CONFIG.PCW_TTC1_BASEADDR {0xE0105000}  \
+    CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff}  \
+    CONFIG.PCW_FCLK_CLK0_BUF {true}  \
+    CONFIG.PCW_FCLK_CLK1_BUF {false}  \
+    CONFIG.PCW_FCLK_CLK2_BUF {false}  \
+    CONFIG.PCW_FCLK_CLK3_BUF {false}  \
+    CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525}  \
+    CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3}  \
+    CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15}  \
+    CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10}  \
+    CONFIG.PCW_UIPARAM_DDR_CL {7}  \
+    CONFIG.PCW_UIPARAM_DDR_CWL {6}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RCD {7}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RP {7}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RC {48.91}  \
+    CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0}  \
+    CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0}  \
+    CONFIG.PCW_UIPARAM_DDR_AL {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085}  \
+    CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160}  \
+    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040}  \
+    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058}  \
+    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009}  \
+    CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033}  \
+    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223}  \
+    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212}  \
+    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085}  \
+    CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092}  \
+    CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667}  \
+    CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650}  \
+    CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200}  \
+    CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666}  \
+    CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1}  \
+    CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1}  \
+    CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25}  \
+    CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333}  \
+    CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200}  \
+    CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200}  \
+    CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100}  \
+    CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000}  \
+    CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000}  \
+    CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154}  \
+    CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000}  \
+    CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60}  \
+    CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000}  \
+    CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000}  \
+    CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000}  \
+    CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095}  \
+    CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095}  \
+    CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336}  \
+    CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50}  \
+    CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000}  \
+    CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000}  \
+    CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {50.000000}  \
+    CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {50.000000}  \
+    CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {50.000000}  \
+    CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336}  \
+    CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336}  \
+    CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336}  \
+    CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336}  \
+    CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336}  \
+    CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336}  \
+    CONFIG.PCW_CLK0_FREQ {100000000}  \
+    CONFIG.PCW_CLK1_FREQ {50000000}  \
+    CONFIG.PCW_CLK2_FREQ {50000000}  \
+    CONFIG.PCW_CLK3_FREQ {50000000}  \
+    CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0}  \
+    CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2}  \
+    CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2}  \
+    CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20}  \
+    CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10}  \
+    CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10}  \
+    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {20}  \
+    CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {20}  \
+    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {20}  \
+    CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1}  \
+    CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52}  \
+    CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2}  \
+    CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5}  \
+    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1}  \
+    CONFIG.PCW_ARMPLL_CTRL_FBDIV {26}  \
+    CONFIG.PCW_IOPLL_CTRL_FBDIV {20}  \
+    CONFIG.PCW_DDRPLL_CTRL_FBDIV {21}  \
+    CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000}  \
+    CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000}  \
+    CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000}  \
+    CONFIG.PCW_SMC_PERIPHERAL_VALID {0}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_VALID {1}  \
+    CONFIG.PCW_SPI_PERIPHERAL_VALID {0}  \
+    CONFIG.PCW_CAN_PERIPHERAL_VALID {0}  \
+    CONFIG.PCW_UART_PERIPHERAL_VALID {1}  \
+    CONFIG.PCW_EN_EMIO_CAN0 {0}  \
+    CONFIG.PCW_EN_EMIO_CAN1 {0}  \
+    CONFIG.PCW_EN_EMIO_ENET0 {0}  \
+    CONFIG.PCW_EN_EMIO_ENET1 {0}  \
+    CONFIG.PCW_EN_PTP_ENET0 {0}  \
+    CONFIG.PCW_EN_PTP_ENET1 {0}  \
+    CONFIG.PCW_EN_EMIO_GPIO {0}  \
+    CONFIG.PCW_EN_EMIO_I2C0 {0}  \
+    CONFIG.PCW_EN_EMIO_I2C1 {0}  \
+    CONFIG.PCW_EN_EMIO_PJTAG {0}  \
+    CONFIG.PCW_EN_EMIO_SDIO0 {0}  \
+    CONFIG.PCW_EN_EMIO_CD_SDIO0 {0}  \
+    CONFIG.PCW_EN_EMIO_WP_SDIO0 {0}  \
+    CONFIG.PCW_EN_EMIO_SDIO1 {0}  \
+    CONFIG.PCW_EN_EMIO_CD_SDIO1 {0}  \
+    CONFIG.PCW_EN_EMIO_WP_SDIO1 {0}  \
+    CONFIG.PCW_EN_EMIO_SPI0 {0}  \
+    CONFIG.PCW_EN_EMIO_SPI1 {0}  \
+    CONFIG.PCW_EN_EMIO_UART0 {0}  \
+    CONFIG.PCW_EN_EMIO_UART1 {0}  \
+    CONFIG.PCW_EN_EMIO_MODEM_UART0 {0}  \
+    CONFIG.PCW_EN_EMIO_MODEM_UART1 {0}  \
+    CONFIG.PCW_EN_EMIO_TTC0 {0}  \
+    CONFIG.PCW_EN_EMIO_TTC1 {0}  \
+    CONFIG.PCW_EN_EMIO_WDT {0}  \
+    CONFIG.PCW_EN_EMIO_TRACE {0}  \
+    CONFIG.PCW_USE_AXI_NONSECURE {0}  \
+    CONFIG.PCW_USE_M_AXI_GP0 {0}  \
+    CONFIG.PCW_USE_M_AXI_GP1 {0}  \
+    CONFIG.PCW_USE_S_AXI_GP0 {0}  \
+    CONFIG.PCW_USE_S_AXI_GP1 {0}  \
+    CONFIG.PCW_USE_S_AXI_ACP {0}  \
+    CONFIG.PCW_USE_S_AXI_HP0 {0}  \
+    CONFIG.PCW_USE_S_AXI_HP1 {0}  \
+    CONFIG.PCW_USE_S_AXI_HP2 {0}  \
+    CONFIG.PCW_USE_S_AXI_HP3 {0}  \
+    CONFIG.PCW_M_AXI_GP0_FREQMHZ {10}  \
+    CONFIG.PCW_M_AXI_GP1_FREQMHZ {10}  \
+    CONFIG.PCW_S_AXI_GP0_FREQMHZ {10}  \
+    CONFIG.PCW_S_AXI_GP1_FREQMHZ {10}  \
+    CONFIG.PCW_S_AXI_ACP_FREQMHZ {10}  \
+    CONFIG.PCW_S_AXI_HP0_FREQMHZ {10}  \
+    CONFIG.PCW_S_AXI_HP1_FREQMHZ {10}  \
+    CONFIG.PCW_S_AXI_HP2_FREQMHZ {10}  \
+    CONFIG.PCW_S_AXI_HP3_FREQMHZ {10}  \
+    CONFIG.PCW_USE_DMA0 {0}  \
+    CONFIG.PCW_USE_DMA1 {0}  \
+    CONFIG.PCW_USE_DMA2 {0}  \
+    CONFIG.PCW_USE_DMA3 {0}  \
+    CONFIG.PCW_USE_TRACE {0}  \
+    CONFIG.PCW_TRACE_PIPELINE_WIDTH {8}  \
+    CONFIG.PCW_INCLUDE_TRACE_BUFFER {0}  \
+    CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128}  \
+    CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0}  \
+    CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12}  \
+    CONFIG.PCW_USE_CROSS_TRIGGER {0}  \
+    CONFIG.PCW_FTM_CTI_IN0 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_IN1 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_IN2 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_IN3 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_OUT0 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_OUT1 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_OUT2 {<Select>}  \
+    CONFIG.PCW_FTM_CTI_OUT3 {<Select>}  \
+    CONFIG.PCW_USE_DEBUG {0}  \
+    CONFIG.PCW_USE_CR_FABRIC {1}  \
+    CONFIG.PCW_USE_AXI_FABRIC_IDLE {0}  \
+    CONFIG.PCW_USE_DDR_BYPASS {0}  \
+    CONFIG.PCW_USE_FABRIC_INTERRUPT {0}  \
+    CONFIG.PCW_USE_PROC_EVENT_BUS {0}  \
+    CONFIG.PCW_USE_EXPANDED_IOP {0}  \
+    CONFIG.PCW_USE_HIGH_OCM {0}  \
+    CONFIG.PCW_USE_PS_SLCR_REGISTERS {0}  \
+    CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0}  \
+    CONFIG.PCW_USE_CORESIGHT {0}  \
+    CONFIG.PCW_EN_EMIO_SRAM_INT {0}  \
+    CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64}  \
+    CONFIG.PCW_UART0_BAUD_RATE {115200}  \
+    CONFIG.PCW_UART1_BAUD_RATE {115200}  \
+    CONFIG.PCW_EN_4K_TIMER {0}  \
+    CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12}  \
+    CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0}  \
+    CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0}  \
+    CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12}  \
+    CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12}  \
+    CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0}  \
+    CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0}  \
+    CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12}  \
+    CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3}  \
+    CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0}  \
+    CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0}  \
+    CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31}  \
+    CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31}  \
+    CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64}  \
+    CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64}  \
+    CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64}  \
+    CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6}  \
+    CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64}  \
+    CONFIG.PCW_EN_DDR {1}  \
+    CONFIG.PCW_EN_SMC {0}  \
+    CONFIG.PCW_EN_QSPI {1}  \
+    CONFIG.PCW_EN_CAN0 {0}  \
+    CONFIG.PCW_EN_CAN1 {0}  \
+    CONFIG.PCW_EN_ENET0 {1}  \
+    CONFIG.PCW_EN_ENET1 {0}  \
+    CONFIG.PCW_EN_GPIO {1}  \
+    CONFIG.PCW_EN_I2C0 {0}  \
+    CONFIG.PCW_EN_I2C1 {0}  \
+    CONFIG.PCW_EN_PJTAG {0}  \
+    CONFIG.PCW_EN_SDIO0 {1}  \
+    CONFIG.PCW_EN_SDIO1 {0}  \
+    CONFIG.PCW_EN_SPI0 {0}  \
+    CONFIG.PCW_EN_SPI1 {0}  \
+    CONFIG.PCW_EN_UART0 {1}  \
+    CONFIG.PCW_EN_UART1 {0}  \
+    CONFIG.PCW_EN_MODEM_UART0 {0}  \
+    CONFIG.PCW_EN_MODEM_UART1 {0}  \
+    CONFIG.PCW_EN_TTC0 {0}  \
+    CONFIG.PCW_EN_TTC1 {0}  \
+    CONFIG.PCW_EN_WDT {0}  \
+    CONFIG.PCW_EN_TRACE {0}  \
+    CONFIG.PCW_EN_USB0 {1}  \
+    CONFIG.PCW_EN_USB1 {0}  \
+    CONFIG.PCW_DQ_WIDTH {32}  \
+    CONFIG.PCW_DQS_WIDTH {4}  \
+    CONFIG.PCW_DM_WIDTH {4}  \
+    CONFIG.PCW_MIO_PRIMITIVE {54}  \
+    CONFIG.PCW_EN_CLK0_PORT {1}  \
+    CONFIG.PCW_EN_CLK1_PORT {0}  \
+    CONFIG.PCW_EN_CLK2_PORT {0}  \
+    CONFIG.PCW_EN_CLK3_PORT {0}  \
+    CONFIG.PCW_EN_RST0_PORT {1}  \
+    CONFIG.PCW_EN_RST1_PORT {0}  \
+    CONFIG.PCW_EN_RST2_PORT {0}  \
+    CONFIG.PCW_EN_RST3_PORT {0}  \
+    CONFIG.PCW_EN_CLKTRIG0_PORT {0}  \
+    CONFIG.PCW_EN_CLKTRIG1_PORT {0}  \
+    CONFIG.PCW_EN_CLKTRIG2_PORT {0}  \
+    CONFIG.PCW_EN_CLKTRIG3_PORT {0}  \
+    CONFIG.PCW_P2F_DMAC_ABORT_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC0_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC1_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC2_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC3_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC4_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC5_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC6_INTR {0}  \
+    CONFIG.PCW_P2F_DMAC7_INTR {0}  \
+    CONFIG.PCW_P2F_SMC_INTR {0}  \
+    CONFIG.PCW_P2F_QSPI_INTR {0}  \
+    CONFIG.PCW_P2F_CTI_INTR {0}  \
+    CONFIG.PCW_P2F_GPIO_INTR {0}  \
+    CONFIG.PCW_P2F_USB0_INTR {0}  \
+    CONFIG.PCW_P2F_ENET0_INTR {0}  \
+    CONFIG.PCW_P2F_SDIO0_INTR {0}  \
+    CONFIG.PCW_P2F_I2C0_INTR {0}  \
+    CONFIG.PCW_P2F_SPI0_INTR {0}  \
+    CONFIG.PCW_P2F_UART0_INTR {0}  \
+    CONFIG.PCW_P2F_CAN0_INTR {0}  \
+    CONFIG.PCW_P2F_USB1_INTR {0}  \
+    CONFIG.PCW_P2F_ENET1_INTR {0}  \
+    CONFIG.PCW_P2F_SDIO1_INTR {0}  \
+    CONFIG.PCW_P2F_I2C1_INTR {0}  \
+    CONFIG.PCW_P2F_SPI1_INTR {0}  \
+    CONFIG.PCW_P2F_UART1_INTR {0}  \
+    CONFIG.PCW_P2F_CAN1_INTR {0}  \
+    CONFIG.PCW_IRQ_F2P_INTR {0}  \
+    CONFIG.PCW_IRQ_F2P_MODE {DIRECT}  \
+    CONFIG.PCW_CORE0_FIQ_INTR {0}  \
+    CONFIG.PCW_CORE0_IRQ_INTR {0}  \
+    CONFIG.PCW_CORE1_FIQ_INTR {0}  \
+    CONFIG.PCW_CORE1_IRQ_INTR {0}  \
+    CONFIG.PCW_VALUE_SILVERSION {3}  \
+    CONFIG.PCW_IMPORT_BOARD_PRESET {None}  \
+    CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None}  \
+    CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}  \
+    CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}  \
+    CONFIG.PCW_UIPARAM_DDR_ENABLE {1}  \
+    CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0}  \
+    CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3}  \
+    CONFIG.PCW_UIPARAM_DDR_ECC {Disabled}  \
+    CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}  \
+    CONFIG.PCW_UIPARAM_DDR_BL {8}  \
+    CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)}  \
+    CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125}  \
+    CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits}  \
+    CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits}  \
+    CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F}  \
+    CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}  \
+    CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}  \
+    CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}  \
+    CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0}  \
+    CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}  \
+    CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {<Select>}  \
+    CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {<Select>}  \
+    CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {<Select>}  \
+    CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {<Select>}  \
+    CONFIG.PCW_DDR_PRIORITY_READPORT_0 {<Select>}  \
+    CONFIG.PCW_DDR_PRIORITY_READPORT_1 {<Select>}  \
+    CONFIG.PCW_DDR_PRIORITY_READPORT_2 {<Select>}  \
+    CONFIG.PCW_DDR_PRIORITY_READPORT_3 {<Select>}  \
+    CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0}  \
+    CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0}  \
+    CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0}  \
+    CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0}  \
+    CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)}  \
+    CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2}  \
+    CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15}  \
+    CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2}  \
+    CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_NAND_NAND_IO {<Select>}  \
+    CONFIG.PCW_NAND_GRP_D8_ENABLE {0}  \
+    CONFIG.PCW_NAND_GRP_D8_IO {<Select>}  \
+    CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_NOR_NOR_IO {<Select>}  \
+    CONFIG.PCW_NOR_GRP_A25_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_A25_IO {<Select>}  \
+    CONFIG.PCW_NOR_GRP_CS0_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_CS0_IO {<Select>}  \
+    CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {<Select>}  \
+    CONFIG.PCW_NOR_GRP_CS1_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_CS1_IO {<Select>}  \
+    CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {<Select>}  \
+    CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0}  \
+    CONFIG.PCW_NOR_GRP_SRAM_INT_IO {<Select>}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6}  \
+    CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}  \
+    CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6}  \
+    CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0}  \
+    CONFIG.PCW_QSPI_GRP_SS1_IO {<Select>}  \
+    CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0}  \
+    CONFIG.PCW_QSPI_GRP_IO1_IO {<Select>}  \
+    CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1}  \
+    CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8}  \
+    CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}  \
+    CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}  \
+    CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}  \
+    CONFIG.PCW_ENET_RESET_ENABLE {1}  \
+    CONFIG.PCW_ENET_RESET_SELECT {Share reset pin}  \
+    CONFIG.PCW_ENET0_RESET_ENABLE {1}  \
+    CONFIG.PCW_ENET0_RESET_IO {MIO 9}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_ENET1_ENET1_IO {<Select>}  \
+    CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0}  \
+    CONFIG.PCW_ENET1_GRP_MDIO_IO {<Select>}  \
+    CONFIG.PCW_ENET1_RESET_ENABLE {0}  \
+    CONFIG.PCW_ENET1_RESET_IO {<Select>}  \
+    CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45}  \
+    CONFIG.PCW_SD0_GRP_CD_ENABLE {1}  \
+    CONFIG.PCW_SD0_GRP_CD_IO {MIO 47}  \
+    CONFIG.PCW_SD0_GRP_WP_ENABLE {0}  \
+    CONFIG.PCW_SD0_GRP_WP_IO {<Select>}  \
+    CONFIG.PCW_SD0_GRP_POW_ENABLE {0}  \
+    CONFIG.PCW_SD0_GRP_POW_IO {<Select>}  \
+    CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_SD1_SD1_IO {<Select>}  \
+    CONFIG.PCW_SD1_GRP_CD_ENABLE {0}  \
+    CONFIG.PCW_SD1_GRP_CD_IO {<Select>}  \
+    CONFIG.PCW_SD1_GRP_WP_ENABLE {0}  \
+    CONFIG.PCW_SD1_GRP_WP_IO {<Select>}  \
+    CONFIG.PCW_SD1_GRP_POW_ENABLE {0}  \
+    CONFIG.PCW_SD1_GRP_POW_IO {<Select>}  \
+    CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15}  \
+    CONFIG.PCW_UART0_GRP_FULL_ENABLE {0}  \
+    CONFIG.PCW_UART0_GRP_FULL_IO {<Select>}  \
+    CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_UART1_UART1_IO {<Select>}  \
+    CONFIG.PCW_UART1_GRP_FULL_ENABLE {0}  \
+    CONFIG.PCW_UART1_GRP_FULL_IO {<Select>}  \
+    CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_SPI0_SPI0_IO {<Select>}  \
+    CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0}  \
+    CONFIG.PCW_SPI0_GRP_SS0_IO {<Select>}  \
+    CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0}  \
+    CONFIG.PCW_SPI0_GRP_SS1_IO {<Select>}  \
+    CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0}  \
+    CONFIG.PCW_SPI0_GRP_SS2_IO {<Select>}  \
+    CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_SPI1_SPI1_IO {<Select>}  \
+    CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0}  \
+    CONFIG.PCW_SPI1_GRP_SS0_IO {<Select>}  \
+    CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0}  \
+    CONFIG.PCW_SPI1_GRP_SS1_IO {<Select>}  \
+    CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0}  \
+    CONFIG.PCW_SPI1_GRP_SS2_IO {<Select>}  \
+    CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_CAN0_CAN0_IO {<Select>}  \
+    CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0}  \
+    CONFIG.PCW_CAN0_GRP_CLK_IO {<Select>}  \
+    CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_CAN1_CAN1_IO {<Select>}  \
+    CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0}  \
+    CONFIG.PCW_CAN1_GRP_CLK_IO {<Select>}  \
+    CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_TRACE_TRACE_IO {<Select>}  \
+    CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_2BIT_IO {<Select>}  \
+    CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_4BIT_IO {<Select>}  \
+    CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_8BIT_IO {<Select>}  \
+    CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_16BIT_IO {<Select>}  \
+    CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0}  \
+    CONFIG.PCW_TRACE_GRP_32BIT_IO {<Select>}  \
+    CONFIG.PCW_TRACE_INTERNAL_WIDTH {2}  \
+    CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_WDT_WDT_IO {<Select>}  \
+    CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_TTC0_TTC0_IO {<Select>}  \
+    CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_TTC1_TTC1_IO {<Select>}  \
+    CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_PJTAG_PJTAG_IO {<Select>}  \
+    CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}  \
+    CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39}  \
+    CONFIG.PCW_USB_RESET_ENABLE {1}  \
+    CONFIG.PCW_USB_RESET_SELECT {Share reset pin}  \
+    CONFIG.PCW_USB0_RESET_ENABLE {1}  \
+    CONFIG.PCW_USB0_RESET_IO {MIO 46}  \
+    CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_USB1_USB1_IO {<Select>}  \
+    CONFIG.PCW_USB1_RESET_ENABLE {0}  \
+    CONFIG.PCW_USB1_RESET_IO {<Select>}  \
+    CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_I2C0_I2C0_IO {<Select>}  \
+    CONFIG.PCW_I2C0_GRP_INT_ENABLE {0}  \
+    CONFIG.PCW_I2C0_GRP_INT_IO {<Select>}  \
+    CONFIG.PCW_I2C0_RESET_ENABLE {0}  \
+    CONFIG.PCW_I2C0_RESET_IO {<Select>}  \
+    CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_I2C1_I2C1_IO {<Select>}  \
+    CONFIG.PCW_I2C1_GRP_INT_ENABLE {0}  \
+    CONFIG.PCW_I2C1_GRP_INT_IO {<Select>}  \
+    CONFIG.PCW_I2C_RESET_ENABLE {1}  \
+    CONFIG.PCW_I2C_RESET_SELECT {<Select>}  \
+    CONFIG.PCW_I2C1_RESET_ENABLE {0}  \
+    CONFIG.PCW_I2C1_RESET_IO {<Select>}  \
+    CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0}  \
+    CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}  \
+    CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}  \
+    CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0}  \
+    CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>}  \
+    CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps}  \
+    CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL}  \
+    CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL}  \
+    CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External}  \
+    CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External}  \
+    CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External}  \
+    CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X}  \
+    CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL}  \
+    CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL}  \
+    CONFIG.PCW_USB_RESET_POLARITY {Active Low}  \
+    CONFIG.PCW_ENET_RESET_POLARITY {Active Low}  \
+    CONFIG.PCW_I2C_RESET_POLARITY {Active Low}  \
+    CONFIG.PCW_MIO_0_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_0_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_0_SLEW {slow}  \
+    CONFIG.PCW_MIO_1_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_1_DIRECTION {out}  \
+    CONFIG.PCW_MIO_1_SLEW {slow}  \
+    CONFIG.PCW_MIO_2_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_2_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_2_SLEW {slow}  \
+    CONFIG.PCW_MIO_3_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_3_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_3_SLEW {slow}  \
+    CONFIG.PCW_MIO_4_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_4_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_4_SLEW {slow}  \
+    CONFIG.PCW_MIO_5_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_5_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_5_SLEW {slow}  \
+    CONFIG.PCW_MIO_6_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_6_DIRECTION {out}  \
+    CONFIG.PCW_MIO_6_SLEW {slow}  \
+    CONFIG.PCW_MIO_7_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_7_DIRECTION {out}  \
+    CONFIG.PCW_MIO_7_SLEW {slow}  \
+    CONFIG.PCW_MIO_8_PULLUP {disabled}  \
+    CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_8_DIRECTION {out}  \
+    CONFIG.PCW_MIO_8_SLEW {slow}  \
+    CONFIG.PCW_MIO_9_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_9_DIRECTION {out}  \
+    CONFIG.PCW_MIO_9_SLEW {slow}  \
+    CONFIG.PCW_MIO_10_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_10_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_10_SLEW {slow}  \
+    CONFIG.PCW_MIO_11_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_11_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_11_SLEW {slow}  \
+    CONFIG.PCW_MIO_12_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_12_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_12_SLEW {slow}  \
+    CONFIG.PCW_MIO_13_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_13_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_13_SLEW {slow}  \
+    CONFIG.PCW_MIO_14_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_14_DIRECTION {in}  \
+    CONFIG.PCW_MIO_14_SLEW {slow}  \
+    CONFIG.PCW_MIO_15_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V}  \
+    CONFIG.PCW_MIO_15_DIRECTION {out}  \
+    CONFIG.PCW_MIO_15_SLEW {slow}  \
+    CONFIG.PCW_MIO_16_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_16_DIRECTION {out}  \
+    CONFIG.PCW_MIO_16_SLEW {slow}  \
+    CONFIG.PCW_MIO_17_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_17_DIRECTION {out}  \
+    CONFIG.PCW_MIO_17_SLEW {slow}  \
+    CONFIG.PCW_MIO_18_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_18_DIRECTION {out}  \
+    CONFIG.PCW_MIO_18_SLEW {slow}  \
+    CONFIG.PCW_MIO_19_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_19_DIRECTION {out}  \
+    CONFIG.PCW_MIO_19_SLEW {slow}  \
+    CONFIG.PCW_MIO_20_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_20_DIRECTION {out}  \
+    CONFIG.PCW_MIO_20_SLEW {slow}  \
+    CONFIG.PCW_MIO_21_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_21_DIRECTION {out}  \
+    CONFIG.PCW_MIO_21_SLEW {slow}  \
+    CONFIG.PCW_MIO_22_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_22_DIRECTION {in}  \
+    CONFIG.PCW_MIO_22_SLEW {slow}  \
+    CONFIG.PCW_MIO_23_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_23_DIRECTION {in}  \
+    CONFIG.PCW_MIO_23_SLEW {slow}  \
+    CONFIG.PCW_MIO_24_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_24_DIRECTION {in}  \
+    CONFIG.PCW_MIO_24_SLEW {slow}  \
+    CONFIG.PCW_MIO_25_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_25_DIRECTION {in}  \
+    CONFIG.PCW_MIO_25_SLEW {slow}  \
+    CONFIG.PCW_MIO_26_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_26_DIRECTION {in}  \
+    CONFIG.PCW_MIO_26_SLEW {slow}  \
+    CONFIG.PCW_MIO_27_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_27_DIRECTION {in}  \
+    CONFIG.PCW_MIO_27_SLEW {slow}  \
+    CONFIG.PCW_MIO_28_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_28_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_28_SLEW {slow}  \
+    CONFIG.PCW_MIO_29_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_29_DIRECTION {in}  \
+    CONFIG.PCW_MIO_29_SLEW {slow}  \
+    CONFIG.PCW_MIO_30_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_30_DIRECTION {out}  \
+    CONFIG.PCW_MIO_30_SLEW {slow}  \
+    CONFIG.PCW_MIO_31_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_31_DIRECTION {in}  \
+    CONFIG.PCW_MIO_31_SLEW {slow}  \
+    CONFIG.PCW_MIO_32_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_32_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_32_SLEW {slow}  \
+    CONFIG.PCW_MIO_33_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_33_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_33_SLEW {slow}  \
+    CONFIG.PCW_MIO_34_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_34_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_34_SLEW {slow}  \
+    CONFIG.PCW_MIO_35_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_35_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_35_SLEW {slow}  \
+    CONFIG.PCW_MIO_36_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_36_DIRECTION {in}  \
+    CONFIG.PCW_MIO_36_SLEW {slow}  \
+    CONFIG.PCW_MIO_37_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_37_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_37_SLEW {slow}  \
+    CONFIG.PCW_MIO_38_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_38_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_38_SLEW {slow}  \
+    CONFIG.PCW_MIO_39_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_39_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_39_SLEW {slow}  \
+    CONFIG.PCW_MIO_40_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_40_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_40_SLEW {slow}  \
+    CONFIG.PCW_MIO_41_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_41_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_41_SLEW {slow}  \
+    CONFIG.PCW_MIO_42_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_42_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_42_SLEW {slow}  \
+    CONFIG.PCW_MIO_43_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_43_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_43_SLEW {slow}  \
+    CONFIG.PCW_MIO_44_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_44_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_44_SLEW {slow}  \
+    CONFIG.PCW_MIO_45_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_45_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_45_SLEW {slow}  \
+    CONFIG.PCW_MIO_46_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_46_DIRECTION {out}  \
+    CONFIG.PCW_MIO_46_SLEW {slow}  \
+    CONFIG.PCW_MIO_47_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_47_DIRECTION {in}  \
+    CONFIG.PCW_MIO_47_SLEW {slow}  \
+    CONFIG.PCW_MIO_48_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_48_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_48_SLEW {slow}  \
+    CONFIG.PCW_MIO_49_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_49_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_49_SLEW {slow}  \
+    CONFIG.PCW_MIO_50_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_50_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_50_SLEW {slow}  \
+    CONFIG.PCW_MIO_51_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_51_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_51_SLEW {slow}  \
+    CONFIG.PCW_MIO_52_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_52_DIRECTION {out}  \
+    CONFIG.PCW_MIO_52_SLEW {slow}  \
+    CONFIG.PCW_MIO_53_PULLUP {enabled}  \
+    CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V}  \
+    CONFIG.PCW_MIO_53_DIRECTION {inout}  \
+    CONFIG.PCW_MIO_53_SLEW {slow}  \
+    CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA}  \
+    CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0}  \
+    CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio}  \
+    CONFIG.PCW_PS7_SI_REV {PRODUCTION}  \
+    CONFIG.PCW_FPGA_FCLK0_ENABLE {1}  \
+    CONFIG.PCW_FPGA_FCLK1_ENABLE {0}  \
+    CONFIG.PCW_FPGA_FCLK2_ENABLE {0}  \
+    CONFIG.PCW_FPGA_FCLK3_ENABLE {0}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_TR {1}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_PC {1}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_WP {1}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_WC {11}  \
+    CONFIG.PCW_NOR_SRAM_CS0_T_RC {11}  \
+    CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_TR {1}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_PC {1}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_WP {1}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_WC {11}  \
+    CONFIG.PCW_NOR_SRAM_CS1_T_RC {11}  \
+    CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0}  \
+    CONFIG.PCW_NOR_CS0_T_TR {1}  \
+    CONFIG.PCW_NOR_CS0_T_PC {1}  \
+    CONFIG.PCW_NOR_CS0_T_WP {1}  \
+    CONFIG.PCW_NOR_CS0_T_CEOE {1}  \
+    CONFIG.PCW_NOR_CS0_T_WC {11}  \
+    CONFIG.PCW_NOR_CS0_T_RC {11}  \
+    CONFIG.PCW_NOR_CS0_WE_TIME {0}  \
+    CONFIG.PCW_NOR_CS1_T_TR {1}  \
+    CONFIG.PCW_NOR_CS1_T_PC {1}  \
+    CONFIG.PCW_NOR_CS1_T_WP {1}  \
+    CONFIG.PCW_NOR_CS1_T_CEOE {1}  \
+    CONFIG.PCW_NOR_CS1_T_WC {11}  \
+    CONFIG.PCW_NOR_CS1_T_RC {11}  \
+    CONFIG.PCW_NOR_CS1_WE_TIME {0}  \
+    CONFIG.PCW_NAND_CYCLES_T_RR {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_AR {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_CLR {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_WP {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_REA {1}  \
+    CONFIG.PCW_NAND_CYCLES_T_WC {11}  \
+    CONFIG.PCW_NAND_CYCLES_T_RC {11}  \
+    CONFIG.PCW_SMC_CYCLE_T0 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T1 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T2 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T3 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T4 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T5 {NA}  \
+    CONFIG.PCW_SMC_CYCLE_T6 {NA}  \
+    CONFIG.PCW_PACKAGE_NAME {clg400}  \
+    CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0}  \
+]
+}
+
+
diff --git a/hardware_design/source_code/param.hpp b/hardware_design/source_code/param.hpp
new file mode 100755
index 0000000..569ef20
--- /dev/null
+++ b/hardware_design/source_code/param.hpp
@@ -0,0 +1,46 @@
+#ifndef __PARAM_HPP__
+#define __PARAM_HPP__
+
+#define MAX_BLOCKS 128
+#define MAX_LINES 256
+#define MAX_PATH 128
+#define MAX_CELLS 16384 // 128x128
+#define MAX_SIZE 128
+#define MAX_SIZE_BIT 7
+#define SLOT_MAX_SIZE 64
+
+
+#define ROUND_LIMIT 4096 //32768 // Max=65534(=2^16-2)
+//#define PRINT_BOARD
+//#define PRINT_SEARCH // for router debug
+
+#define PQ_BIT     12
+#define MAX_PQ   4096
+
+#define PRIO_BIT   16
+#define DATA_BIT   16
+#define ELEM_BIT   32 // ELEM_BIT = PRIO_BIT + DATA_BIT
+
+#define DATA_MASK  65535 // 0000 FFFF
+#define DATA_MAX   65535 // FFFF
+#define PRIO_MAX   65535 // FFFF
+
+#define LE 1
+#define TO 2
+#define RI 3
+#define BO 4
+
+#define SA_O   1000
+#define SA_I   100000
+#define TEMP_S 500
+#define TEMP_E 0.1
+
+#define INTER_BLOCK_MARGIN 2
+
+#define LOOP 50
+#define TRY_LIMIT 500
+#define NO_MOVE 10
+
+#define LFSR_RAND_MAX 4294967295
+
+#endif /* __PARAM_HPP__ */
diff --git a/hardware_design/source_code/solver.cpp b/hardware_design/source_code/solver.cpp
new file mode 100755
index 0000000..a303868
--- /dev/null
+++ b/hardware_design/source_code/solver.cpp
@@ -0,0 +1,1065 @@
+#include "solver.hpp"
+
+static unsigned int lfsr, lfsr_x, lfsr_y;
+
+static void lfsr_random_init(unsigned int seed, unsigned int seed_x, unsigned int seed_y) {
+#pragma HLS INLINE
+	lfsr = seed;
+	lfsr_x = seed_x;
+	lfsr_y = seed_y;
+}
+
+static unsigned int lfsr_random() {
+#pragma HLS INLINE
+	bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
+	if((lfsr >>  0) % 2 == 1) b_32 = true;
+	if((lfsr >> 10) % 2 == 1) b_22 = true;
+	if((lfsr >> 30) % 2 == 1) b_2 = true;
+	if((lfsr >> 31) % 2 == 1) b_1 = true;
+	bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
+	lfsr >>= 1;
+	if(new_bit) lfsr |= 0x80000000;
+	return lfsr;
+}
+static unsigned int lfsr_x_random() {
+#pragma HLS INLINE
+	bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
+	if((lfsr_x >>  0) % 2 == 1) b_32 = true;
+	if((lfsr_x >> 10) % 2 == 1) b_22 = true;
+	if((lfsr_x >> 30) % 2 == 1) b_2 = true;
+	if((lfsr_x >> 31) % 2 == 1) b_1 = true;
+	bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
+	lfsr_x >>= 1;
+	if(new_bit) lfsr_x |= 0x80000000;
+	return lfsr_x;
+}
+static unsigned int lfsr_y_random() {
+#pragma HLS INLINE
+	bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
+	if((lfsr_y >>  0) % 2 == 1) b_32 = true;
+	if((lfsr_y >> 10) % 2 == 1) b_22 = true;
+	if((lfsr_y >> 30) % 2 == 1) b_2 = true;
+	if((lfsr_y >> 31) % 2 == 1) b_1 = true;
+	bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
+	lfsr_y >>= 1;
+	if(new_bit) lfsr_y |= 0x80000000;
+	return lfsr_y;
+}
+
+bool solver(hls::stream<ap_uint<4> >& state, unsigned int seed[3], short int *pbnum, short int *plnum,
+		short int block_info[MAX_BLOCKS+1][5][3], short int *pwi, short int *phi, short int block_place_global[MAX_BLOCKS+1][2], short int opt_result[MAX_CELLS]) {
+#pragma HLS INTERFACE s_axilite port=return
+#pragma HLS INTERFACE ap_hs register port=state
+#pragma HLS INTERFACE m_axi depth=1 port=seed offset=slave bundle=io_data
+#pragma HLS INTERFACE m_axi depth=1 port=pbnum offset=slave bundle=io_data
+#pragma HLS INTERFACE m_axi depth=1 port=plnum offset=slave bundle=io_data
+#pragma HLS INTERFACE m_axi depth=1 port=block_info offset=slave bundle=io_data
+#pragma HLS INTERFACE m_axi depth=1 port=pwi offset=slave bundle=io_data
+#pragma HLS INTERFACE m_axi depth=1 port=phi offset=slave bundle=io_data
+#pragma HLS INTERFACE m_axi depth=1 port=block_place_global offset=slave bundle=io_data
+#pragma HLS INTERFACE m_axi depth=1 port=opt_result offset=slave bundle=io_data
+
+	state.write(0b0000);
+
+	short int blocks = *pbnum;
+	short int line_num = *plnum;
+	short int wi, hi;
+	
+	lfsr_random_init(seed[0], seed[1], seed[2]);
+	
+	bool status;
+	
+	state.write(0b0001);
+
+	status = local_placement_1(line_num, blocks, &wi, &hi, block_info, block_place_global, opt_result);
+	if(!status) { // Cannot route
+		state.write(0b0010);
+		return false;
+	}
+
+	state.write(0b0011);
+
+	status = local_placement_2(line_num, blocks, &wi, &hi, block_info, opt_result);
+	if(!status) {
+		state.write(0b0100);
+		return false;
+	}
+	else {
+		state.write(0b0111);
+	}
+
+	*pwi = wi;
+	*phi = hi;
+
+	return true;
+}
+
+bool local_placement_1(short int line_num, short int blocks, short int *pwi, short int *phi, short int block_info[MAX_BLOCKS+1][5][3], short int block_place_global[MAX_BLOCKS+1][2], short int opt_result[MAX_CELLS]) {
+	
+	short int wi, hi; // board size (w, h)
+	
+	// size of each slot (w, h)
+	short int slot_w[SLOT_MAX_SIZE];
+	short int slot_h[SLOT_MAX_SIZE];
+	// basic position of each slot (x, y)
+	short int slot_w_t[SLOT_MAX_SIZE];
+	short int slot_h_t[SLOT_MAX_SIZE];
+	
+	short int block_place_slack[MAX_BLOCKS+1][2];
+	short int block_place_basis[MAX_BLOCKS+1][2];
+	short int block_place_delta[MAX_BLOCKS+1][2];
+	short int block_place_opt[MAX_BLOCKS+1][2];
+	
+	short int board_str[MAX_CELLS];
+#pragma HLS ARRAY_PARTITION variable=board_str cyclic factor=4 dim=1
+	
+	// load a placement result
+	short int min_x = SLOT_MAX_SIZE, min_y = SLOT_MAX_SIZE, max_x = 0, max_y = 0;
+	PLACE_1_LOAD_1:
+	for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+		short int p = block_place_global[i][0];
+		short int q = block_place_global[i][1];
+		if(p < min_x) { min_x = p; }
+		if(q < min_y) { min_y = q; }
+		if(p > max_x) { max_x = p; }
+		if(q > max_y) { max_y = q; }
+	}
+	PLACE_1_LOAD_2:
+	for(short int p = min_x; p <= max_x; p++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=64
+		slot_w[p] = 0;
+	}
+	PLACE_1_LOAD_3:
+	for(short int q = min_y; q <= max_y; q++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=64
+		slot_h[q] = 0;
+	}
+	PLACE_1_LOAD_4:
+	for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+		short int sx = block_info[i][0][0];
+		short int sy = block_info[i][0][1];
+		short int p = block_place_global[i][0];
+		short int q = block_place_global[i][1];
+		if(sx > slot_w[p]) { slot_w[p] = sx; }
+		if(sy > slot_h[q]) { slot_h[q] = sy; }
+	}
+	wi = INTER_BLOCK_MARGIN;
+	PLACE_1_LOAD_5:
+	for(short int p = min_x; p <= max_x; p++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=64
+		slot_w_t[p] = wi;
+		wi += slot_w[p] + INTER_BLOCK_MARGIN;
+	}
+	hi = INTER_BLOCK_MARGIN;
+	PLACE_1_LOAD_6:
+	for(short int q = min_y; q <= max_y; q++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=64
+		slot_h_t[q] = hi;
+		hi += slot_h[q] + INTER_BLOCK_MARGIN;
+	}
+	
+#ifdef DEBUG_PRINT
+	cout << "== Local placement with routing (1) ==" << endl;
+	cout << "Board size = " << wi << "X" << hi << endl;
+#endif
+	
+	// calculate slack for each block
+	PLACE_1_CALC_SLACK:
+	for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+		short int sx = block_info[i][0][0];
+		short int sy = block_info[i][0][1];
+		short int p = block_place_global[i][0];
+		short int q = block_place_global[i][1];
+		block_place_basis[i][0] = slot_w_t[p];
+		block_place_basis[i][1] = slot_h_t[q];
+		block_place_slack[i][0] = slot_w[p] - sx;
+		block_place_slack[i][1] = slot_h[q] - sy;
+	}
+	
+	bool find_route = false;
+	int min_status = MAX_CELLS;
+	PLACE_1_SEARCH:
+	for(int counter = 0; counter < LOOP; counter++) {
+#ifdef DEBUG_PRINT
+		cout << "."; fflush(stdout);
+#endif
+		PLACE_1_SEARCH_INIT:
+		for(int s = 0; s < MAX_CELLS; s++) {
+#pragma HLS UNROLL factor=8
+			board_str[s] = 0;
+		}
+		PLACE_1_SEARCH_SET:
+		for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+			short int x = block_place_basis[i][0];
+			short int y = block_place_basis[i][1];
+			short int dx = lfsr_x_random() % (block_place_slack[i][0] + 1);
+			short int dy = lfsr_y_random() % (block_place_slack[i][1] + 1);
+			block_place_delta[i][0] = dx;
+			block_place_delta[i][1] = dy;
+			PLACE_1_SEARCH_SET_1:
+			for(int it = 1; it < 5; it++) {
+				short int tx = block_info[i][it][0];
+				short int ty = block_info[i][it][1];
+				short int tn = block_info[i][it][2];
+				if(tn < 0) break;
+				short int p = x + dx + tx;
+				short int q = y + dy + ty;
+				short int idx = q * MAX_SIZE + p;
+				if(tn > 0) { board_str[idx] = tn; }
+				else { board_str[idx] = -1; }
+			}
+		}
+		
+		int status = router(wi, hi, line_num, board_str); // routing
+		
+		if(status >= 0 && status < min_status) {
+			min_status = status;
+			find_route = true;
+			PLACE_1_SEARCH_OUT_1:
+			for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+				block_place_opt[i][0] = block_place_basis[i][0] + block_place_delta[i][0];
+				block_place_opt[i][1] = block_place_basis[i][1] + block_place_delta[i][1];
+			}
+			PLACE_1_SEARCH_OUT_2_Y:
+			for(short int y = 0; y < hi; y++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+				PLACE_1_SEARCH_OUT_2_X:
+				for(short int x = 0; x < wi; x++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+					short int idx = y * MAX_SIZE + x;
+					opt_result[idx] = board_str[idx];
+				}
+			}
+		}
+	}
+#ifdef DEBUG_PRINT
+	cout << endl;
+#endif
+	
+	if(!find_route) return false;
+	
+	// Update
+	PLACE_1_UPDATE_I:
+	for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+		block_place_basis[i][0] = block_place_opt[i][0];
+		block_place_basis[i][1] = block_place_opt[i][1];
+	}
+	
+	/// print for debug ///
+#ifdef DEBUG_PRINT
+	cout << "Min-wire status: " << min_status << endl;
+	show_result(line_num, blocks, wi, hi, opt_result);
+#endif
+	/// print for debug ///
+	
+	//cout << "== Local placement with routing (1+) ==" << endl;
+	bool remove_flag;
+	short int deleted_line_w = 0, deleted_line_h = 0;
+	PLACE_1_UPDATE_Y:
+	for(short int q = hi - 1; q >= 0; q--) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+		remove_flag = true;
+		PLACE_1_UPDATE_Y_X:
+		for(short int p = 0; p < wi; p++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+			short int idx = q * MAX_SIZE + p;
+			if(opt_result[idx] != 0) {
+				remove_flag = false;
+				break;
+			}
+		}
+		if(!remove_flag) continue;
+		PLACE_1_UPDATE_Y_B:
+		for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+			if(block_place_basis[i][1] > q) { block_place_basis[i][1] -= 1; }
+		}
+		deleted_line_h++;
+	}
+	PLACE_1_UPDATE_X:
+	for(short int p = wi - 1; p >= 0; p--) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+		remove_flag = true;
+		PLACE_1_UPDATE_X_Y:
+		for(short int q = 0; q < hi; q++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+			short int idx = q * MAX_SIZE + p;
+			if(opt_result[idx] != 0) {
+				remove_flag = false;
+				break;
+			}
+		}
+		if(!remove_flag) continue;
+		PLACE_1_UPDATE_X_B:
+		for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+			if(block_place_basis[i][0] > p) { block_place_basis[i][0] -= 1; }
+		}
+		deleted_line_w++;
+	}
+	hi -= deleted_line_h;
+	wi -= deleted_line_w;
+	
+	PLACE_1_REROUTE_INIT:
+	for(int s = 0; s < MAX_CELLS; s++) {
+#pragma HLS UNROLL factor=8
+		board_str[s] = 0;
+	}
+	PLACE_1_REROUTE_SET:
+	for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+		short int x = block_place_basis[i][0];
+		short int y = block_place_basis[i][1];
+		PLACE_1_REROUTE_SET_1:
+		for(int it = 1; it < 5; it++) {
+			short int tx = block_info[i][it][0];
+			short int ty = block_info[i][it][1];
+			short int tn = block_info[i][it][2];
+			if(tn < 0) break;
+			short int p = x + tx;
+			short int q = y + ty;
+			short int idx = q * MAX_SIZE + p;
+			if(tn > 0) { board_str[idx] = tn; }
+			else { board_str[idx] = -1; }
+		}
+	}
+	
+	int counter = 0;
+	PLACE_1_REROUTE_LOOP:
+	while(router(wi, hi, line_num, board_str) < 0) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=5
+		if(counter++ >= LOOP) return false;
+	}
+
+	PLACE_1_O_1_Y:
+	for(short int y = 0; y < hi; y++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+		PLACE_1_O_1_X:
+		for(short int x = 0; x < wi; x++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+			short int idx = y * MAX_SIZE + x;
+			opt_result[idx] = board_str[idx];
+		}
+	}
+	PLACE_1_O_2:
+	for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+		block_info[i][0][0] = block_place_basis[i][0];
+		block_info[i][0][1] = block_place_basis[i][1];
+	}
+	
+	*pwi = wi;
+	*phi = hi;
+
+	return true;
+}
+
+bool local_placement_2(short int line_num, short int blocks, short int *pwi, short int *phi, short int block_info[MAX_BLOCKS+1][5][3], short int opt_result[MAX_CELLS]) {
+	
+	short int wi = *pwi, hi = *phi;
+	
+	short int block_place_slack[MAX_BLOCKS+1][2];
+	short int block_place_basis[MAX_BLOCKS+1][2];
+	short int block_place_delta[MAX_BLOCKS+1][2];
+	short int block_place_opt[MAX_BLOCKS+1][2];
+	
+	short int board_str[MAX_CELLS];
+#pragma HLS ARRAY_PARTITION variable=board_str cyclic factor=4 dim=1
+	
+	PLACE_2_I:
+	for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+		block_place_basis[i][0] = block_info[i][0][0];
+		block_place_basis[i][1] = block_info[i][0][1];
+	}
+	
+#ifdef DEBUG_PRINT
+	cout << "== Local placement with routing (2) ==" << endl;
+#endif
+	int direction = 0; // 0: X, 1: Y
+	int try_count = 1;
+	int no_update = 0;
+	
+	if(hi > wi) direction = 1;
+	PLACE_2_BODY:
+	while(try_count <= TRY_LIMIT) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=50
+#ifdef DEBUG_PRINT
+		cout << "Phase " << try_count << ": direction: ";
+		switch(direction) {
+			case 0: cout << "X" << endl; break;
+			case 1: cout << "Y" << endl; break;
+		}
+		cout << "Board size = " << wi << "X" << hi << endl;
+#endif
+		
+		// calculate slack for each block
+		PLACE_2_CALC_SLACK:
+		for(int t = 1; t <= blocks; t++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+			block_place_slack[t][0] = 0;
+			block_place_slack[t][1] = 0;
+			PLACE_2_CALC_SLACK_I:
+			for(int s = 0; s < MAX_CELLS; s++) {
+#pragma HLS UNROLL factor=8
+				board_str[s] = 0;
+			}
+			PLACE_2_CALC_SLACK_1:
+			for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+				if(i == t) continue;
+				short int x = block_place_basis[i][0];
+				short int y = block_place_basis[i][1];
+				PLACE_2_CALC_SLACK_1_1:
+				for(int it = 1; it < 5; it++) {
+					short int tx = block_info[i][it][0];
+					short int ty = block_info[i][it][1];
+					short int tn = block_info[i][it][2];
+					if(tn < 0) break;
+					short int p = x + tx;
+					short int q = y + ty;
+					short int idx = q * MAX_SIZE + p;
+					if(tn > 0) { board_str[idx] = tn; }
+					else { board_str[idx] = -1; }
+				}
+			}
+			bool move_x = true, move_y = true;
+			PLACE_2_CALC_SLACK_2: // X direction
+			while(direction == 0) {
+#pragma HLS LOOP_TRIPCOUNT min=0 max=10
+
+				short int x = block_place_basis[t][0];
+				short int y = block_place_basis[t][1];
+				PLACE_2_CALC_SLACK_2_1:
+				for(int it = 1; it < 5; it++) {
+					short int tx = block_info[t][it][0];
+					short int ty = block_info[t][it][1];
+					short int tn = block_info[t][it][2];
+					if(tn < 0) break;
+					short int p = x + tx - (block_place_slack[t][0]+1);
+					short int q = y + ty;
+					short int idx = q * MAX_SIZE + p;
+					if(p < 0 || board_str[idx] != 0) {
+						move_x = false;
+						break;
+					}
+				}
+				if(move_x) {
+					if(++block_place_slack[t][0] >= 9) break;
+				}
+				else {
+					break;
+				}
+			}
+			PLACE_2_CALC_SLACK_3: // Y direction
+			while(direction == 1) {
+#pragma HLS LOOP_TRIPCOUNT min=0 max=10
+				short int x = block_place_basis[t][0];
+				short int y = block_place_basis[t][1];
+				PLACE_2_CALC_SLACK_3_1:
+				for(int it = 1; it < 5; it++) {
+					short int tx = block_info[t][it][0];
+					short int ty = block_info[t][it][1];
+					short int tn = block_info[t][it][2];
+					if(tn < 0) break;
+					short int p = x + tx;
+					short int q = y + ty - (block_place_slack[t][1]+1);
+					short int idx = q * MAX_SIZE + p;
+					if(q < 0 || board_str[idx] != 0) {
+						move_y = false;
+						break;
+					}
+				}
+				if(move_y) {
+					if(++block_place_slack[t][1] >= 9) break;
+				}
+				else {
+					break;
+				}
+			}
+		}
+		
+		no_update++;
+		bool find_route = false;
+		int d_sum_max = 0;
+		PLACE_2_SEARCH:
+		for(int counter = 0; counter < LOOP; counter++) {
+#ifdef DEBUG_PRINT
+			cout << "."; fflush(stdout);
+#endif
+			PLACE_2_SEARCH_INIT:
+			for(int s = 0; s < MAX_CELLS; s++) {
+#pragma HLS UNROLL factor=8
+				board_str[s] = 0;
+			}
+			int d_sum = 0;
+			PLACE_2_SEARCH_SET:
+			for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+				short int x = block_place_basis[i][0];
+				short int y = block_place_basis[i][1];
+				short int dx = 0;
+				short int dy = 0;
+				switch(direction) {
+					case 0: dx = lfsr_x_random() % (block_place_slack[i][0] + 1); break;
+					case 1: dy = lfsr_y_random() % (block_place_slack[i][1] + 1); break;
+				}
+				if(lfsr_random() % 16 >= 2) {
+					dx = 0;
+					dy = 0;
+				}
+				block_place_delta[i][0] = dx;
+				block_place_delta[i][1] = dy;
+				d_sum += dx + dy;
+				PLACE_2_SEARCH_SET_1:
+				for(int it = 1; it < 5; it++) {
+					short int tx = block_info[i][it][0];
+					short int ty = block_info[i][it][1];
+					short int tn = block_info[i][it][2];
+					if(tn < 0) break;
+					short int p = x - dx + tx;
+					short int q = y - dy + ty;
+					short int idx = q * MAX_SIZE + p;
+					if(tn > 0) { board_str[idx] = tn; }
+					else{ board_str[idx] = -1; }
+				}
+			}
+			
+			int status = router(wi, hi, line_num, board_str);
+			
+			if(status >= 0 && d_sum > d_sum_max) {
+				d_sum_max = d_sum;
+				find_route = true;
+				PLACE_2_SEARCH_OUT_1:
+				for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+					block_place_opt[i][0] = block_place_basis[i][0] - block_place_delta[i][0];
+					block_place_opt[i][1] = block_place_basis[i][1] - block_place_delta[i][1];
+				}
+				PLACE_2_SEARCH_OUT_2_Y:
+				for(short int y = 0; y < hi; y++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+					PLACE_2_SEARCH_OUT_2_X:
+					for(short int x = 0; x < wi; x++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+						short int idx = y * MAX_SIZE + x;
+						opt_result[idx] = board_str[idx];
+					}
+				}
+			}
+		}
+#ifdef DEBUG_PRINT
+		cout << endl;
+#endif
+		
+		if(find_route) {
+			
+			no_update = 0; // reset
+			
+			// Update
+			PLACE_2_UPDATE_I:
+			for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+				block_place_basis[i][0] = block_place_opt[i][0];
+				block_place_basis[i][1] = block_place_opt[i][1];
+			}
+			
+			/// print for debug ///
+#ifdef DEBUG_PRINT
+			cout << "Max dSum: " << d_sum_max << endl;
+			show_result(line_num, blocks, wi, hi, opt_result);
+#endif
+			/// print for debug ///
+			
+			bool remove_flag;
+			short int deleted_line_w = 0, deleted_line_h = 0;
+			PLACE_2_UPDATE_Y:
+			for(short int q = hi - 1; q >= 0; q--) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+				remove_flag = true;
+				PLACE_2_UPDATE_Y_X:
+				for(short int p = 0; p < wi; p++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+					short int idx = q * MAX_SIZE + p;
+					if(opt_result[idx] != 0) {
+						remove_flag = false;
+						break;
+					}
+				}
+				if(!remove_flag) continue;
+				PLACE_2_UPDATE_Y_B:
+				for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+					if(block_place_basis[i][1] > q) { block_place_basis[i][1] -= 1; }
+				}
+				deleted_line_h++;
+			}
+			PLACE_2_UPDATE_X:
+			for(short int p = wi - 1; p >= 0; p--) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+				remove_flag = true;
+				PLACE_2_UPDATE_X_Y:
+				for(short int q = 0; q < hi; q++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+					short int idx = q * MAX_SIZE + p;
+					if(opt_result[idx] != 0) {
+						remove_flag = false;
+						break;
+					}
+				}
+				if(!remove_flag) continue;
+				PLACE_2_UPDATE_X_B:
+				for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+					if(block_place_basis[i][0] > p) { block_place_basis[i][0] -= 1; }
+				}
+				deleted_line_w++;
+			}
+			hi -= deleted_line_h;
+			wi -= deleted_line_w;
+			
+			PLACE_2_REROUTE_INIT:
+			for(int s = 0; s < MAX_CELLS; s++) {
+#pragma HLS UNROLL factor=8
+				board_str[s] = 0;
+			}
+			PLACE_2_REROUTE_SET:
+			for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+				short int x = block_place_basis[i][0];
+				short int y = block_place_basis[i][1];
+				PLACE_2_REROUTE_SET_1:
+				for(int it = 1; it < 5; it++) {
+					short int tx = block_info[i][it][0];
+					short int ty = block_info[i][it][1];
+					short int tn = block_info[i][it][2];
+					if(tn < 0) break;
+					short int p = x + tx;
+					short int q = y + ty;
+					short int idx = q * MAX_SIZE + p;
+					if(tn > 0) { board_str[idx] = tn; }
+					else { board_str[idx] = -1; }
+				}
+			}
+			
+			int counter = 0;
+			PLACE_2_REROUTE_LOOP:
+			while(router(wi, hi, line_num, board_str) < 0) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=5
+				if(counter++ >= LOOP) return false;
+			}
+			PLACE_2_REROUTE_OUT_Y:
+			for(short int y = 0; y < hi; y++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+				PLACE_2_REROUTE_OUT_X:
+				for(short int x = 0; x < wi; x++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+					short int idx = y * MAX_SIZE + x;
+					opt_result[idx] = board_str[idx];
+				}
+			}
+		} // End update
+		
+		if(no_update >= NO_MOVE) break;
+		
+		try_count++;
+		switch(direction) {
+			case 0: direction = 1; break;
+			case 1: direction = 0; break;
+		}
+	}
+#ifdef DEBUG_PRINT
+	cout << "#Tries: " << try_count << endl;
+#endif
+
+	PLACE_2_O_2:
+	for(int i = 1; i <= blocks; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+		block_info[i][0][0] = block_place_basis[i][0];
+		block_info[i][0][1] = block_place_basis[i][1];
+	}
+	
+	*pwi = wi;
+	*phi = hi;
+
+	return true;
+}
+
+
+
+
+
+
+
+unsigned short int new_weight(unsigned short int x) {
+#pragma HLS INLINE
+	unsigned short int y = (x & 0x00FF) + 1;
+	return y;
+}
+
+unsigned short int my_abs(short int x) {
+#pragma HLS INLINE
+	if(x < 0) x *= -1;
+	return x;
+}
+
+// DATA_BIT: bit length of cell idx
+// PRIO_BIT: bit length of cost(priority)
+int router(short int size_x, short int size_y, short int line_num, short int board_str[MAX_CELLS]) {
+	
+	if(line_num == 0) return 0;
+	
+	short int terminals[MAX_LINES][2];
+	short int paths_size[MAX_LINES];
+	unsigned short int paths[MAX_LINES][MAX_PATH];
+	bool adjacents[MAX_LINES];
+	
+	unsigned short int weights[MAX_CELLS];
+	
+	SET_LOOP_1:
+	for(int i = 0; i < line_num; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+		terminals[i][0] = -1;
+		terminals[i][1] = -1;
+		paths_size[i] = 0;
+		adjacents[i] = false;
+	}
+	SET_LOOP_2_Y:
+	for(short int y = 0; y < size_y; y++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+		SET_LOOP_2_X:
+		for(short int x = 0; x < size_x; x++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+			short int j = y * MAX_SIZE + x;
+			short int num = board_str[j];
+			switch(num) {
+			case 0:
+				weights[j] = 1;
+				break;
+			case -1:
+				weights[j] = PRIO_MAX;
+				break;
+			default:
+				weights[j] = PRIO_MAX;
+				if(terminals[num-1][0] >= 0) { terminals[num-1][1] = j; }
+				else { terminals[num-1][0] = j; }
+				break;
+			}
+		}
+	}
+	
+#ifdef PRINT_BOARD
+	cout << "== Print board ==" << endl;
+	for(short int y = 0; y < size_y; y++) {
+		for(short int x = 0; x < size_x; x++) {
+			short int j = y * MAX_SIZE + x;
+			short int num = board_str[j];
+			if(num == 0) { cout << "--"; }
+			else if(num == -1) { cout << "XX"; }
+			else{ cout << setfill('0') << setw(2) << hex << num; }
+			if(x != size_x-1) { cout << " "; }
+		}
+		cout << endl;
+	}
+	cout << setfill(' ');
+	cout << dec;
+#endif
+	
+	SET_LOOP_3:
+	for(int i = 0; i < line_num; i++) {
+#pragma HLS UNROLL factor=2
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+		short int t1 = terminals[i][0];
+		short int t2 = terminals[i][1];
+		short int t1_y = t1 / MAX_SIZE;
+		short int t1_x = t1 - MAX_SIZE * t1_y;
+		short int t2_y = t2 / MAX_SIZE;
+		short int t2_x = t2 - MAX_SIZE * t2_y;
+		unsigned short int dist = my_abs(t1_x - t2_x) + my_abs(t1_y - t2_y);
+		if(dist == 1) {
+			adjacents[i] = true;
+#ifdef PRINT_BOARD
+			cout << "Line #" << i + 1 << " needs no routing" << endl;
+#endif
+		}
+	}
+	
+	// Step 1 //
+	ROUTING_1:
+	for(int i = 0; i < line_num; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+		if(adjacents[i]) continue;
+#ifdef PRINT_SEARCH
+		cout << "Line #" << i + 1 << endl;
+#endif
+		short int t1 = terminals[i][0];
+		short int t2 = terminals[i][1];
+		weights[t1] = 1;
+		if(search(size_x, size_y, &paths_size[i], paths[i], t1, t2, weights) < 0) { return -1; }
+		weights[t1] = PRIO_MAX;
+	}
+	
+	bool has_overlap;
+	short int overlap_checks[MAX_CELLS];
+	short int last_target = -1;
+	
+	// Step 2 //
+	ROUTING_2:
+	for(int round = 1; round <= ROUND_LIMIT; round++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=4096
+		short int target = lfsr_random() % line_num;
+		if(adjacents[target]) continue;
+		if(target == last_target) continue;
+		last_target = target;
+		unsigned short int round_weight = new_weight(round);
+
+#ifdef PRINT_SEARCH		
+		cout << "Line #" << target + 1 << "(round: " << round << ", weight: " << round_weight << ")" << endl;
+#endif
+		
+		short int t1 = terminals[target][0];
+		short int t2 = terminals[target][1];
+		
+		WEIGHT_UPDATE_1:
+		for(short int p = 0; p < paths_size[target]; p++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+			weights[paths[target][p]] = 1;
+		}
+		WEIGHT_UPDATE_2:
+		for(int i = 0; i < line_num; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+			if(i == target) continue;
+			WEIGHT_UPDATE_2_1:
+			for(short int p = 0; p < paths_size[i]; p++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+				weights[paths[i][p]] = round_weight;
+			}
+		}
+		weights[t1] = 1;
+		search(size_x, size_y, &paths_size[target], paths[target], t1, t2, weights);
+		weights[t1] = PRIO_MAX;
+		
+		has_overlap = false;
+		OVERLAP_CHECK_1:
+		for(short int y = 0; y < size_y; y++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+			OVERLAP_CHECK_1_1:
+			for(short int x = 0; x < size_x; x++) {
+#pragma HLS LOOP_TRIPCOUNT min=10 max=128
+				short int j = y * MAX_SIZE + x;
+				overlap_checks[j] = 0;
+			}
+		}
+		OVERLAP_CHECK_2:
+		for(int i = 0; i < line_num && !has_overlap; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+			OVERLAP_CHECK_2_1:
+			for(short int p = 0; p < paths_size[i]; p++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+				short int cell_id = paths[i][p];
+				if(overlap_checks[cell_id] == 1) {
+					has_overlap = true;
+					break;
+				}
+				overlap_checks[cell_id] = 1;
+			}
+		}
+		if(!has_overlap) break;
+	}
+	
+	if(has_overlap) { // Cannot solve
+		return -1;
+	}
+	
+	int total_wire_length = 0;
+	OUTPUT_1:
+	for(short int i = 0; i < line_num; i++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+		total_wire_length += paths_size[i];
+		OUTPUT_1_1:
+		for(short int p = 0; p < paths_size[i]; p++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+			short int cell_id = paths[i][p];
+			board_str[cell_id] = i + 1;
+		}
+	}
+	
+#ifdef PRINT_BOARD
+	cout << "== Print answer ==" << endl;
+	for(short int y = 0; y < size_y; y++) {
+		for(short int x = 0; x < size_x; x++) {
+			short int j = y * MAX_SIZE + x;
+			short int num = board_str[j];
+			if(num == 0) { cout << "--"; }
+			else if(num == -1) { cout << "XX"; }
+			else{ cout << setfill('0') << setw(2) << hex << num; }
+			if(x != size_x-1) { cout << " "; }
+		}
+		cout << endl;
+	}
+	cout << setfill(' ');
+	cout << dec;
+#endif
+	
+	return total_wire_length;
+}
+
+int search(short int size_x, short int size_y, short int *path_size, unsigned short int path[MAX_PATH], unsigned short int start, unsigned short int goal, unsigned short int w[MAX_CELLS]) {
+	
+	unsigned short int dist[MAX_CELLS];
+#pragma HLS ARRAY_PARTITION variable=dist cyclic factor=16 dim=1
+	unsigned short int prev[MAX_CELLS];
+#pragma HLS ARRAY_PARTITION variable=prev cyclic factor=16 dim=1
+
+	SEARCH_INIT_DIST:
+	for(int j = 0; j < MAX_CELLS; j++) {
+#pragma HLS UNROLL factor=32
+		dist[j] = PRIO_MAX;
+	}
+	
+	ap_uint<PQ_BIT> pq_len = 0;
+    bool is_empty = true;
+    unsigned int pq_nodes[MAX_PQ];
+	
+	short int goal_y = goal / MAX_SIZE;
+	short int goal_x = goal - MAX_SIZE * goal_y;
+	
+	dist[start] = 0;
+	enqueue(pq_nodes, 0, start, &pq_len, &is_empty);
+	
+	bool find_path = false;
+	SEARCH_BODY:
+	while(!is_empty) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=1000
+		
+		unsigned short int prev_cost;
+		unsigned short int s;
+		dequeue(pq_nodes, &prev_cost, &s, &pq_len, &is_empty);
+		
+		if(s == goal) {
+			find_path = true;
+			break;
+		}
+		
+		unsigned short int dist_s = dist[s];
+		unsigned short int cost = w[s];
+		unsigned short int dist_d = dist_s + cost;
+		
+		short int s_y = s / MAX_SIZE;
+		short int s_x = s - MAX_SIZE * s_y;
+
+		SEARCH_ADJACENTS:
+		for(int a = 0; a < 4; a++) {
+#pragma HLS UNROLL
+			short int d_x = s_x;
+			short int d_y = s_y;
+			switch(a) {
+			case 0: d_x -= 1; break;
+			case 1: d_x += 1; break;
+			case 2: d_y -= 1; break;
+			case 3: d_y += 1; break;
+			}
+			if(d_x >= 0 && d_x < size_x && d_y >= 0 && d_y < size_y) {
+				unsigned short int d = d_y * MAX_SIZE + d_x;
+				if(w[d] == PRIO_MAX && d != goal) continue;
+				if(dist_d < dist[d]) {
+					dist[d] = dist_d;
+					prev[d] = s;
+					unsigned short int new_dist = dist_d + my_abs(d_x - goal_x) + my_abs(d_y - goal_y);
+					enqueue(pq_nodes, new_dist, d, &pq_len, &is_empty);
+				}
+			}
+		}
+	}
+	if(!find_path){ return -1; }
+	
+	unsigned short int t = prev[goal];
+	short int p = 0;
+#ifdef PRINT_SEARCH
+	cout << "Path: ";
+#endif
+	SEARCH_BACKTRACK:
+	while(t != start) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=128
+#ifdef PRINT_SEARCH
+		cout << "(" << t % MAX_SIZE << ", " << t / MAX_SIZE << ")";
+#endif
+		path[p] = t;
+		p++;
+		t = prev[t];
+	}
+#ifdef PRINT_SEARCH
+	cout << endl;
+#endif
+	*path_size = p;
+	
+	return 0;
+}
+
+// Enqueue (Insert an element)
+void enqueue(unsigned int pq_nodes[MAX_PQ], unsigned short int queue_priority, unsigned short int queue_data, ap_uint<PQ_BIT> *pq_len, bool *is_empty) {
+#pragma HLS INLINE
+
+	(*pq_len)++;
+	if ((*pq_len) == 0) { (*pq_len)--; } // Queue is full -> Last element is automatically removed
+	// Note that last element is not always the lowest priority one. //
+
+	ap_uint<PQ_BIT> i = (*pq_len);
+	ap_uint<PQ_BIT> p = (*pq_len) >> 1; // parent node
+	
+	ENQUEUE_LOOP:
+	while (i > 1 && (unsigned short int)(pq_nodes[p] >> DATA_BIT) >= queue_priority) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=12
+		pq_nodes[i] = pq_nodes[p];
+		i = p;
+		p = p >> 1; // parent node
+	}
+	pq_nodes[i] = ((unsigned int)queue_priority << DATA_BIT) | (unsigned int)queue_data;
+	*is_empty = false;
+}
+
+// Dequeue (Extract and remove the top element)
+void dequeue(unsigned int pq_nodes[MAX_PQ], unsigned short int *ret_priority, unsigned short int *ret_data, ap_uint<PQ_BIT> *pq_len, bool *is_empty) {
+#pragma HLS INLINE
+
+	*ret_priority = (unsigned short int)(pq_nodes[1] >> DATA_BIT);
+	*ret_data     = (unsigned short int)(pq_nodes[1] & DATA_MASK);
+	
+	ap_uint<PQ_BIT> i = 1; // root node
+	unsigned short int last_priority = (unsigned short int)(pq_nodes[*pq_len] >> DATA_BIT); // Priority of last element
+
+	DEQUEUE_LOOP:
+	while (!(i >> (PQ_BIT-1))) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=12
+		ap_uint<PQ_BIT> c1 = i << 1; // child node (L)
+		ap_uint<PQ_BIT> c2 = c1 + 1; // child node (R)
+		if (c1 < *pq_len && (unsigned short int)(pq_nodes[c1] >> DATA_BIT) <= last_priority) {
+			if (c2 < *pq_len && (unsigned short int)(pq_nodes[c2] >> DATA_BIT) <= (unsigned short int)(pq_nodes[c1] >> DATA_BIT)) {
+				pq_nodes[i] = pq_nodes[c2];
+				i = c2;
+			}
+			else {
+				pq_nodes[i] = pq_nodes[c1];
+				i = c1;
+			}
+		}
+		else {
+			if (c2 < *pq_len && (unsigned short int)(pq_nodes[c2] >> DATA_BIT) <= last_priority) {
+				pq_nodes[i] = pq_nodes[c2];
+				i = c2;
+			}
+			else {
+				break;
+			}
+		}
+	}
+	pq_nodes[i] = pq_nodes[*pq_len];
+	(*pq_len)--;
+	if ((*pq_len) == 0) { *is_empty = true; }
+}
diff --git a/hardware_design/source_code/solver.hpp b/hardware_design/source_code/solver.hpp
new file mode 100755
index 0000000..303650d
--- /dev/null
+++ b/hardware_design/source_code/solver.hpp
@@ -0,0 +1,28 @@
+#ifndef __SOLVER_HPP__
+#define __SOLVER_HPP__
+
+//#define DEBUG_PRINT
+
+#include <iostream>
+
+#include "param.hpp"
+#include <ap_int.h>
+#include <hls_stream.h>
+#ifdef DEBUG_PRINT
+	#include "tools.hpp"
+#endif
+
+using namespace std;
+
+bool solver(hls::stream<ap_uint<4> >& state, unsigned int seed[3], short int *pbnum, short int *plnum, short int block_info[MAX_BLOCKS+1][5][3], short int *pwi, short int *phi, short int block_place_global[MAX_BLOCKS+1][2], short int opt_result[MAX_CELLS]);
+
+bool local_placement_1(short int line_num, short int blocks, short int *pwi, short int *phi, short int block_info[MAX_BLOCKS+1][5][3], short int block_place_global[MAX_BLOCKS+1][2], short int opt_result[MAX_CELLS]);
+bool local_placement_2(short int line_num, short int blocks, short int *pwi, short int *phi, short int block_info[MAX_BLOCKS+1][5][3], short int opt_result[MAX_CELLS]);
+
+int router(short int size_x, short int size_y, short int line_num, short int board_str[MAX_CELLS]);
+
+int search(short int size_x, short int size_y, short int *path_size, unsigned short int path[MAX_PATH], unsigned short int start, unsigned short int goal, unsigned short int w[MAX_CELLS]);
+void enqueue(unsigned int pq_nodes[MAX_PQ], unsigned short int queue_priority, unsigned short int queue_data, ap_uint<PQ_BIT> *pq_len, bool *is_empty);
+void dequeue(unsigned int pq_nodes[MAX_PQ], unsigned short int *ret_priority, unsigned short int *ret_data, ap_uint<PQ_BIT> *pq_len, bool *is_empty);
+
+#endif /* __SOLVER_HPP__ */
diff --git a/hardware_design/test_bench/io.cpp b/hardware_design/test_bench/io.cpp
new file mode 100755
index 0000000..e3c7af1
--- /dev/null
+++ b/hardware_design/test_bench/io.cpp
@@ -0,0 +1,485 @@
+#include "io.hpp"
+
+void read_problem(short int *W, short int *H, short int *blocks, short int *line_num, short int block_info[][5][3], short int line_info[][2][5]) {
+	
+	for(int i = 0; i < MAX_BLOCKS+1; i++) {
+		for(int j = 0; j < 5; j++) {
+			for(int k = 0; k < 3; k++) {
+				block_info[i][j][k] = -1;
+			}
+		}
+	}
+	for(int i = 0; i < MAX_LINES+1; i++) {
+		for(int j = 0; j < 2; j++) {
+			for(int k = 0; k < 5; k++) {
+				line_info[i][j][k] = -1;
+			}
+		}
+	}
+	*line_num = 0;
+	
+	int now_block = 0, count;
+	short int size_x = -1, size_y = -1, now_x, now_y, num;
+	while(1) {
+		string line, tmp;
+		string::size_type pos;
+		
+		if(!getline(cin,line)) break; // stdin
+		if(line.find("\n") != string::npos || line.find("\r") != string::npos) {
+			line.replace(line.length()-1, 1, ""); // Remove '\n' or '\r'
+		}
+		
+		int len = line.length();
+		if(len == 0) continue;
+		
+		if(line.find("SIZE") != string::npos) {
+			replace(line.begin(), line.end(), 'X', ' ');
+			istringstream iss(line);
+			iss >> tmp >> *W >> *H;
+			continue;
+		}
+		else if(line.find("BLOCK_NUM") != string::npos) {
+			istringstream iss(line);
+			iss >> tmp >> *blocks;
+			continue;
+		}
+		else if(line.find("BLOCK") != string::npos) {
+			now_block++;
+			replace(line.begin(), line.end(), 'X', ' ');
+			istringstream iss(line);
+			iss >> tmp >> size_x >> size_y;
+			now_y = 0;
+			count = 1;
+			block_info[now_block][0][0] = size_x;
+			block_info[now_block][0][1] = size_y;
+			continue;
+		}
+		
+		// Replace ' ' -> ""
+		pos = 0;
+		while((pos = line.find(' ', pos)) != string::npos) {
+			line.replace(pos, 1, "");
+		}
+		// Replace '+' -> "-1"
+		pos = 0;
+		while((pos = line.find('+', pos)) != string::npos) {
+			line.replace(pos, 1, "-1");
+		}
+		// Replace ',' -> " "
+		pos = 0;
+		while((pos = line.find(',', pos)) != string::npos) {
+			line.replace(pos, 1, " ");
+		}
+		
+		istringstream iss(line);
+		for(now_x = 0; now_x < size_x; now_x++) {
+			iss >> num;
+			if(num > 0) {
+				block_info[now_block][count][0] = now_x;
+				block_info[now_block][count][1] = now_y;
+				block_info[now_block][count][2] = num;
+				if(line_info[num][0][0] == -1) { line_info[num][0][0] = now_block; }
+				else if(line_info[num][1][0] == -1) { line_info[num][1][0] = now_block; }
+				else { cout << "Error(RE0): Line#" << num << endl; exit(1); }
+				if(num > *line_num) { *line_num = num; }
+				count++;
+			}
+			else if(num < 0) {
+				block_info[now_block][count][0] = now_x;
+				block_info[now_block][count][1] = now_y;
+				block_info[now_block][count][2] = 0;
+				count++;
+			}
+		}
+		now_y++;
+	}
+	cout << "W: " << *W << ", H: " << *H << endl;
+	
+	/// Print block information ///
+	cout << "== Block information ==" << endl;
+	cout << "#Blocks = " << *blocks << endl;
+	for(int i = 1; i <= *blocks; i++) {
+		short int sx = block_info[i][0][0];
+		short int sy = block_info[i][0][1];
+		cout << "Block#" << i << ": (" << sx << ", " << sy << ")" << endl;
+		
+		if(sx == 1 && sy == 1) { // monomino
+			short int tx = block_info[i][1][0];
+			short int ty = block_info[i][1][1];
+			short int tn = block_info[i][1][2];
+			cout << "- (" << tx << ", " << ty << ") " << tn << endl;
+		}
+		else {
+			for(int it = 1; it < 5; it++) {
+				short int tx = block_info[i][it][0];
+				short int ty = block_info[i][it][1];
+				short int tn = block_info[i][it][2];
+				cout << "- (" << tx << ", " << ty << ") " << tn << endl;
+			}
+		}
+	}
+	/// Print block information ///
+}
+
+void extract_line_info(short int line_num, short int blocks, short int block_info[][5][3], short int line_info[][2][5]) {
+	
+	short int lines_x[4], lines_y[4]; // # of nums in a block for X- & Y- axes
+	for(int i = 1; i <= blocks; i++) {
+		short int sx = block_info[i][0][0];
+		short int sy = block_info[i][0][1];
+		
+		if(sx == 1 && sy == 1) { // monomino
+			short int tx = block_info[i][1][0];
+			short int ty = block_info[i][1][1];
+			short int tn = block_info[i][1][2];
+			
+			if(tn == 0) continue;
+			
+			short int n_idx = 0;
+			while(line_info[tn][n_idx][1] != -1) {
+				n_idx++;
+				if(n_idx >= 2) { cout << "Error(EL0): Line#" << tn << endl; exit(1); }
+			}
+			line_info[tn][n_idx][LE] = 2;
+			line_info[tn][n_idx][TO] = 2;
+			line_info[tn][n_idx][RI] = 2;
+			line_info[tn][n_idx][BO] = 2;
+			
+			continue;
+		}
+		
+		for(short int p = 0; p < 4; p++) lines_x[p] = 0;
+		for(short int q = 0; q < 4; q++) lines_y[q] = 0;
+		
+		for(int it = 1; it < 5; it++) {
+			short int tx = block_info[i][it][0];
+			short int ty = block_info[i][it][1];
+			short int tn = block_info[i][it][2];
+			if(tn > 0) {
+				lines_x[tx] += 1;
+				lines_y[ty] += 1;
+			}
+		}
+		
+		for(int it = 1; it < 5; it++) {
+			short int tx = block_info[i][it][0];
+			short int ty = block_info[i][it][1];
+			short int tn = block_info[i][it][2];
+			
+			if(tn == 0) continue;
+			
+			short int n_idx = 0;
+			while(line_info[tn][n_idx][1] != -1) {
+				n_idx++;
+				if(n_idx >= 2) { cout << "Error(EL1): Line#" << tn << endl; exit(1); }
+			}
+			
+			short int compe_cost, wall_cost;
+			// Map to left
+			compe_cost = 2;
+			compe_cost += lines_x[tx] - 1;
+			for(short int p = tx - 1; p >= 0; p--) { compe_cost += lines_x[p] * 2; }
+			wall_cost = 1;
+			for(int it2 = 1; it2 < 5; it2++) {
+				short int cx = block_info[i][it2][0];
+				short int cy = block_info[i][it2][1];
+				if(cx == tx && cy == ty) continue;
+				if(cy == ty && cx < tx) {
+					if(sx == 2 && sy == 3 && ty == 1) {
+						wall_cost = 4;
+					}
+					else {
+						wall_cost = 2;
+					}
+				}
+			}
+			line_info[tn][n_idx][LE] = compe_cost * wall_cost;
+			
+			// Map to top
+			compe_cost = 2;
+			compe_cost += lines_y[ty] - 1;
+			for(short int q = ty - 1; q >= 0; q--) { compe_cost += lines_y[q] * 2; }
+			wall_cost = 1;
+			for(int it2 = 1; it2 < 5; it2++) {
+				short int cx = block_info[i][it2][0];
+				short int cy = block_info[i][it2][1];
+				if(cx == tx && cy == ty) continue;
+				if(cx == tx && cy < ty) {
+					if(sx == 3 && sy == 2 && tx == 1) {
+						wall_cost = 4;
+					}
+					else {
+						wall_cost = 2;
+					}
+				}
+			}
+			line_info[tn][n_idx][TO] = compe_cost * wall_cost;
+			
+			// Map to right
+			compe_cost = 2;
+			compe_cost += lines_x[tx] - 1;
+			for(short int p = tx + 1; p < sx; p++) { compe_cost += lines_x[p] * 2; }
+			wall_cost = 1;
+			for(int it2 = 1; it2 < 5; it2++) {
+				short int cx = block_info[i][it2][0];
+				short int cy = block_info[i][it2][1];
+				if(cx == tx && cy == ty) continue;
+				if(cy == ty && cx > tx) {
+					if(sx == 2 && sy == 3 && ty == 1) {
+						wall_cost = 4;
+					}
+					else {
+						wall_cost = 2;
+					}
+				}
+			}
+			line_info[tn][n_idx][RI] = compe_cost * wall_cost;
+			
+			// Map to bottom
+			compe_cost = 2;
+			compe_cost += lines_y[ty] - 1;
+			for(short int q = ty + 1; q < sy; q++) { compe_cost += lines_y[q] * 2; }
+			wall_cost = 1;
+			for(int it2 = 1; it2 < 5; it2++) {
+				short int cx = block_info[i][it2][0];
+				short int cy = block_info[i][it2][1];
+				if(cx == tx && cy == ty) continue;
+				if(cx == tx && cy > ty) {
+					if(sx == 3 && sy == 2 && tx == 1) {
+						wall_cost = 4;
+					}
+					else {
+						wall_cost = 2;
+					}
+				}
+			}
+			line_info[tn][n_idx][BO] = compe_cost * wall_cost;
+		}
+	}
+	
+	/// Print line information ///
+	cout << "== Line information ==" << endl;
+	cout << "#Lines = " << line_num << endl;
+	for(int l = 1; l <= line_num; l++) {
+		short int block1 = line_info[l][0][0];
+		short int block2 = line_info[l][1][0];
+		cout << "Line#" << l << ": ";
+		cout << "Block#" << block1 << "(";
+		for(int i = 1; i < 5; i++) {
+			cout << (float)line_info[l][0][i] / 2;
+			if(i != 4) { cout << ", "; }
+		}
+		cout << "), ";
+		cout << "Block#" << block2 << "(";
+		for(int i = 1; i < 5; i++) {
+			cout << (float)line_info[l][1][i] / 2;
+			if(i != 4) { cout << ", "; }
+		}
+		cout << ")" << endl;
+	}
+	/// Print line information ///
+}
+
+static unsigned int lfsr, lfsr_x, lfsr_y;
+
+static void lfsr_random_init(unsigned int seed, unsigned int seed_x, unsigned int seed_y) {
+	lfsr = seed;
+	lfsr_x = seed_x;
+	lfsr_y = seed_y;
+}
+
+static unsigned int lfsr_random() {
+	bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
+	if((lfsr >>  0) % 2 == 1) b_32 = true;
+	if((lfsr >> 10) % 2 == 1) b_22 = true;
+	if((lfsr >> 30) % 2 == 1) b_2 = true;
+	if((lfsr >> 31) % 2 == 1) b_1 = true;
+	bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
+	lfsr >>= 1;
+	if(new_bit) lfsr |= 0x80000000;
+	return lfsr;
+}
+static unsigned int lfsr_x_random() {
+	bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
+	if((lfsr_x >>  0) % 2 == 1) b_32 = true;
+	if((lfsr_x >> 10) % 2 == 1) b_22 = true;
+	if((lfsr_x >> 30) % 2 == 1) b_2 = true;
+	if((lfsr_x >> 31) % 2 == 1) b_1 = true;
+	bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
+	lfsr_x >>= 1;
+	if(new_bit) lfsr_x |= 0x80000000;
+	return lfsr_x;
+}
+static unsigned int lfsr_y_random() {
+	bool b_32 = false, b_22 = false, b_2 = false, b_1 = false;
+	if((lfsr_y >>  0) % 2 == 1) b_32 = true;
+	if((lfsr_y >> 10) % 2 == 1) b_22 = true;
+	if((lfsr_y >> 30) % 2 == 1) b_2 = true;
+	if((lfsr_y >> 31) % 2 == 1) b_1 = true;
+	bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
+	lfsr_y >>= 1;
+	if(new_bit) lfsr_y |= 0x80000000;
+	return lfsr_y;
+}
+
+float calcPlaceCost(short int line_num, short int line_info[MAX_LINES+1][2][5], short int block_place_global[MAX_BLOCKS+1][2]) {
+
+	short int block1, block2; // block idx
+	short int x1, y1; // 1st block
+	short int x2, y2; // 2nd block
+	short int delta_x, delta_y;
+	// delta_x > 0: 1st block is located in the East of 2nd block
+	// delta_x < 0: 1st block is located in the West of 2nd block
+	// delta_y > 0: 1st block is located in the South of 2nd block
+	// delta_y < 0: 1st block is located in the North of 2nd block
+	short int dist_x, dist_y; // distance between 2 blocks
+	short int dir_x1, dir_x2; // X-direction from 1st block to 2nd block and ...
+	short int dir_y1, dir_y2; // Y-direction from 1st block to 2nd block and ...
+
+	int cost = 0;
+	for(int l = 1; l <= line_num; l++) {
+		block1 = line_info[l][0][0]; // 1st block including line#L
+		block2 = line_info[l][1][0]; // 2nd block including line#L
+		x1 = block_place_global[block1][0];
+		y1 = block_place_global[block1][1];
+		x2 = block_place_global[block2][0];
+		y2 = block_place_global[block2][1];
+		delta_x = x1 - x2;
+		delta_y = y1 - y2;
+		//dist_x = abs(delta_x);
+		//dist_y = abs(delta_y);
+
+		dir_x1 = 0;
+		dir_x2 = 0;
+		dist_x = 0;
+		if(delta_x > 0) {
+			dist_x = delta_x;
+			dir_x1 = line_info[l][0][1];
+			dir_x2 = line_info[l][1][3];
+		}
+		else if(delta_x < 0) {
+			dist_x = delta_x * (-1);
+			dir_x1 = line_info[l][0][3];
+			dir_x2 = line_info[l][1][1];
+		}
+		dir_y1 = 0;
+		dir_y2 = 0;
+		dist_y = 0;
+		if(delta_y > 0) {
+			dist_y = delta_y;
+			dir_y1 = line_info[l][0][2];
+			dir_y2 = line_info[l][1][4];
+		}
+		else if(delta_y < 0) {
+			dist_y = delta_y * (-1);
+			dir_y1 = line_info[l][0][4];
+			dir_y2 = line_info[l][1][2];
+		}
+		cost += (dist_x * dir_x1 * dir_x2 + dist_y * dir_y1 * dir_y2);
+	}
+
+	return (float)cost / 4;
+}
+
+void global_placement(unsigned int seed[3], short int W, short int H, short int line_num, short int blocks, short int block_info[MAX_BLOCKS+1][5][3], short int line_info[MAX_LINES+1][2][5], short int block_place_global[MAX_BLOCKS+1][2]) {
+
+	lfsr_random_init(seed[0], seed[1], seed[2]);
+
+	cout << "== Global placement ==" << endl;
+	short int sx_sum = 0, sy_sum = 0;
+	for(int i = 1; i <= blocks; i++) {
+		sx_sum += block_info[i][0][0]; // block size (x)
+		sy_sum += block_info[i][0][1]; // block size (y)
+	}
+	// define #slots
+	short int max_x = W * blocks / sx_sum - 1;
+	short int max_y = H * blocks / sy_sum - 1;
+	while(((max_x + 1) * (max_y + 1)) < blocks) {
+		max_x += 1;
+		max_y += 1;
+	}
+	cout << "#Slots for X-axis: " << max_x + 1 << endl;
+	cout << "#Slots for Y-axis: " << max_y + 1 << endl;
+
+	// init. placement on global slot
+	short int global_slot[SLOT_MAX_SIZE][SLOT_MAX_SIZE];
+	short int i = 1;
+	for(short int q = 0; q <= max_y; q++) {
+		for(short int p = 0; p <= max_x; p++) {
+			if(i <= blocks) {
+				block_place_global[i][0] = p;
+				block_place_global[i][1] = q;
+				global_slot[q][p] = i;
+				i++;
+			}
+			else {
+				global_slot[q][p] = 0;
+			}
+		}
+	}
+
+	short int line_info_buf[MAX_LINES+1][2][5];
+	for(int l = 1; l <= line_num; l++) {
+		line_info_buf[l][0][0] = line_info[l][0][0];
+		line_info_buf[l][0][1] = line_info[l][0][1];
+		line_info_buf[l][0][2] = line_info[l][0][2];
+		line_info_buf[l][0][3] = line_info[l][0][3];
+		line_info_buf[l][0][4] = line_info[l][0][4];
+		line_info_buf[l][1][0] = line_info[l][1][0];
+		line_info_buf[l][1][1] = line_info[l][1][1];
+		line_info_buf[l][1][2] = line_info[l][1][2];
+		line_info_buf[l][1][3] = line_info[l][1][3];
+		line_info_buf[l][1][4] = line_info[l][1][4];
+	}
+
+	// cost calculation (may be inefficient)
+	float cost = calcPlaceCost(line_num, line_info_buf, block_place_global);
+	float init_cost = cost;
+	cout << "Cost = " << cost << " -> ";
+
+	// SA setup
+	float temperature = TEMP_S;
+	float delta = powf(((float)(TEMP_E)/(float)(TEMP_S)), (1./(float)(SA_O)));
+
+	// SA
+	for(int counter = 0; counter < SA_O; counter++) {
+		temperature *= delta; // Update temperature
+
+		// trgt_i, trgt_j: moved block idx (trgt_j == 0, no block is placed on slot(j_x,j_y))
+		// i_x, i_y, j_x, j_y
+		for(int counter_in = 0; counter_in < SA_I; counter_in++) {
+			short int trgt_i = lfsr_random() % blocks + 1;
+			short int i_x = block_place_global[trgt_i][0];
+			short int i_y = block_place_global[trgt_i][1];
+			short int j_x = lfsr_x_random() % SLOT_MAX_SIZE;
+			short int j_y = lfsr_y_random() % SLOT_MAX_SIZE;
+			if(j_x > max_x || j_y > max_y) continue;
+			short int trgt_j = global_slot[j_y][j_x]; // slot -> block
+
+			block_place_global[trgt_i][0] = j_x;
+			block_place_global[trgt_i][1] = j_y;
+			global_slot[j_y][j_x] = trgt_i;
+			block_place_global[trgt_j][0] = i_x;
+			block_place_global[trgt_j][1] = i_y;
+			global_slot[i_y][i_x] = trgt_j;
+
+			float new_cost = calcPlaceCost(line_num, line_info_buf, block_place_global);
+
+			if(new_cost > cost && (float)lfsr_random()/LFSR_RAND_MAX > expf(-(new_cost-cost)/temperature)) {
+				block_place_global[trgt_i][0] = i_x;
+				block_place_global[trgt_i][1] = i_y;
+				global_slot[i_y][i_x] = trgt_i;
+				block_place_global[trgt_j][0] = j_x;
+				block_place_global[trgt_j][1] = j_y;
+				global_slot[j_y][j_x] = trgt_j;
+			}
+			else if(new_cost != cost) { cost = new_cost; }
+		}
+	}
+
+	cout << cost << endl;
+
+	seed[0] = lfsr;
+	seed[1] = lfsr_x;
+	seed[2] = lfsr_y;
+}
diff --git a/hardware_design/test_bench/io.hpp b/hardware_design/test_bench/io.hpp
new file mode 100755
index 0000000..19651fa
--- /dev/null
+++ b/hardware_design/test_bench/io.hpp
@@ -0,0 +1,19 @@
+#ifndef __IO_HPP__
+#define __IO_HPP__
+
+#include <iostream>
+#include <sstream>   // for istringstream
+#include <algorithm> // for replace
+#include <math.h>
+
+#include "param.hpp"
+
+using namespace std;
+
+void read_problem(short int *W, short int *H, short int *blocks, short int *line_num, short int block_info[][5][3], short int line_info[][2][5]);
+void extract_line_info(short int line_num, short int blocks, short int block_info[][5][3], short int line_info[][2][5]);
+
+float calcPlaceCost(short int line_num, short int line_info[MAX_LINES+1][2][5], pair<short int,short int> block_place_global[MAX_BLOCKS+1]);
+void global_placement(unsigned int seed[3], short int W, short int H, short int line_num, short int blocks, short int block_info[MAX_BLOCKS+1][5][3], short int line_info[MAX_LINES+1][2][5], short int block_place_global[MAX_BLOCKS+1][2]);
+
+#endif /* __IO_HPP__ */
diff --git a/hardware_design/test_bench/main.cpp b/hardware_design/test_bench/main.cpp
new file mode 100755
index 0000000..354bf4f
--- /dev/null
+++ b/hardware_design/test_bench/main.cpp
@@ -0,0 +1,103 @@
+#include <iostream>
+#include <getopt.h>
+
+#include "param.hpp"
+#include "io.hpp"
+#include "solver.hpp"
+#include "tools.hpp"
+
+using namespace std;
+
+void usage() {
+	cout << "Usage: ./sim.exe [--output output-file] [--seed seed-value] < input-file" << endl;
+	exit(-1);
+}
+
+int main(int argc, char *argv[]) {
+	
+	char *out_filename = NULL;
+	uint32_t seed_v = 214;
+	
+	// Get options
+	struct option longopts[] = {
+		{"output", required_argument, NULL, 'o'},
+		{"seed", required_argument, NULL, 's'},
+		{0, 0, 0, 0}
+	};
+	int opt, optidx;
+	while((opt = getopt_long(argc, argv, "o:s:", longopts, &optidx)) != -1) {
+		switch(opt) {
+		case 'o':
+			out_filename = optarg;
+			break;
+		case 's':
+			sscanf(optarg, "%u", &seed_v);
+			break;
+		default:
+			usage();
+		}
+	}
+	
+	// Init seed value
+	uint32_t seed[3];
+	srand(seed_v);
+	seed[0] = rand();
+	seed[1] = rand();
+	seed[2] = rand();
+	
+	// W: Max width of a board (specified in a problem file)
+	// H: Max height of a board (specified in a problem file)
+	// blocks: # of blocks (specified in a problem file)
+	short int W, H, blocks, line_num;
+	// W_ext: Width of a current solution
+	// H_ext: Height of a current solution
+	short int W_ext, H_ext;
+	
+	// block data
+	short int block_info[MAX_BLOCKS+1][5][3];
+	
+	// line data
+	short int line_info[MAX_LINES+1][2][5];
+	
+	// block positions on slot matrix
+	short int block_place_global[MAX_BLOCKS+1][2];
+
+	// An opt. result will be stored in the array
+	short int opt_result[MAX_CELLS];
+	
+	// Check problem
+	read_problem(&W, &H, &blocks, &line_num, block_info, line_info);
+	extract_line_info(line_num, blocks, block_info, line_info);
+
+	// Solver body
+	global_placement(seed, W, H, line_num, blocks, block_info, line_info, block_place_global);
+
+	hls::stream<ap_uint<4> > state;
+	bool solved = solver(state, seed, &blocks, &line_num, block_info, &W_ext, &H_ext, block_place_global, opt_result);
+	
+	// Check answer
+	if(!solved) {
+		cout << "Fail re-routing" << endl;
+	}
+	else {
+		cout << "== Answer ==" << endl;
+		cout << "SIZE " << W_ext << "X" << H_ext << endl;
+		show_result(line_num, blocks, W_ext, H_ext, opt_result);
+	}
+	if(W_ext > W || H_ext > H) {
+		cout << "Fail satisfying constraint T_T" << endl;
+	}
+	else {
+		cout << "Satisfy constraint ^_^" << endl;
+		if(out_filename == NULL) return 0;
+		cout << "Output to " << out_filename << endl;
+		short int block_place_basis[MAX_BLOCKS+1][2];
+		for(int i = 1; i <= blocks; i++) {
+			block_place_basis[i][0] = block_info[i][0][0];
+			block_place_basis[i][1] = block_info[i][0][1];
+		}
+		output_to_file(out_filename, line_num, blocks, W_ext, H_ext, opt_result, block_place_basis);
+	}
+	
+	return 0;
+}
diff --git a/hardware_design/test_bench/sample_Q.txt b/hardware_design/test_bench/sample_Q.txt
new file mode 100755
index 0000000..f99ce86
--- /dev/null
+++ b/hardware_design/test_bench/sample_Q.txt
@@ -0,0 +1,37 @@
+SIZE 10X10
+BLOCK_NUM 8
+
+BLOCK#1 1X4
+1
++
+8
+7
+
+BLOCK#2 3X2
+0,8,0
+7,6,+
+
+BLOCK#3 2X3
+10,0
+ +,0
+ 3,9
+
+BLOCK#4 2X2
+1,2
+4,+
+
+BLOCK#5 3X2
+11,+,+
+ 0,0,3
+
+BLOCK#6 3X2
+0, +,2
+5,11,0
+
+BLOCK#7 3X2
+0,10,6
+9, 5,0
+
+BLOCK#8 3X2
++,+,0
+0,+,4
\ No newline at end of file
diff --git a/hardware_design/test_bench/tools.cpp b/hardware_design/test_bench/tools.cpp
new file mode 100755
index 0000000..3165ab1
--- /dev/null
+++ b/hardware_design/test_bench/tools.cpp
@@ -0,0 +1,42 @@
+#include "tools.hpp"
+
+void output_to_file(char *f_name, short int line_num, short int blocks, short int wi, short int hi, short int board[], short int block_place[][2]) {
+	
+	ofstream outputfile(f_name);
+	
+	outputfile << "SIZE " << wi << "X" << hi << endl;
+	for(short int q = 0; q < hi; q++) {
+		for(short int p = 0; p < wi; p++) {
+			short int n = board[q*MAX_SIZE+p];
+			if(n == 0) { outputfile << 0; }
+			else if(n == -1) { outputfile << 0; }
+			else{ outputfile << n; }
+			if(p != wi-1) { outputfile << ", "; }
+		}
+		outputfile << endl;
+	}
+	outputfile << setfill(' ');
+	outputfile << dec;
+	for(int i = 1; i <= blocks; i++) {
+		outputfile << "BLOCK#" << i << " @(" << block_place[i][0] << "," << block_place[i][1] << ")" << endl;
+	}
+	
+	outputfile.close();
+}
+
+void show_result(short int line_num, short int blocks, short int wi, short int hi, short int board[]) {
+	
+	// This shows a number from 1 to 255
+	for(short int q = 0; q < hi; q++) {
+		for(short int p = 0; p < wi; p++) {
+			short int n = board[q*MAX_SIZE+p];
+			if(n == 0) { cout << "--"; }
+			else if(n == -1) { cout << "XX"; }
+			else{ cout << setfill('0') << setw(2) << hex << n; }
+			if(p != wi-1) { cout << " "; }
+		}
+		cout << endl;
+	}
+	cout << setfill(' ');
+	cout << dec;
+}
diff --git a/hardware_design/test_bench/tools.hpp b/hardware_design/test_bench/tools.hpp
new file mode 100755
index 0000000..f339d11
--- /dev/null
+++ b/hardware_design/test_bench/tools.hpp
@@ -0,0 +1,16 @@
+#ifndef __TOOLS_HPP__
+#define __TOOLS_HPP__
+
+using namespace std;
+
+#include <iostream>
+#include <iomanip>   // for setw
+#include <fstream>
+
+#include "param.hpp"
+
+void usage();
+void output_to_file(char *f_name, short int line_num, short int blocks, short int wi, short int hi, short int board[], short int block_place[][2]);
+void show_result(short int line_num, short int blocks, short int wi, short int hi, short int board[]);
+
+#endif /* __TOOLS_HPP__ */
-- 
2.22.0