Next-generation SoC design and applications to image and communication processing

Our research focuses on next-generation system-on-a-chip (SoC) designs, including low-power, secure, and reconfigurable system designs, as well as design methods and applications to image processing and communication processing from the perspective of system design.


We are currently examining system-on-a-chip (SoC) designs and design methods, which are some of the most challenging areas of research in electrical and electronic engineering.

professor's portrait
Togawa, Nozomu
Doctor of Engineering


DrEng, Graduate School of Science and Engineering, Waseda University
Associate Professor, Dept. of Information and Media Sciences, University of Kitakyushu
Associate Professor, Dept. of Computer Science and Engineering, Waseda University
Professor, Dept. of Computer Science and Engineering, Waseda University


  • SoC design
  • SoC design methodology
  • Image and communication processing related to SoC design


Best Paper Award, IEEE ASP-DAC 1995
Azusa Ono Award, Waseda University
2006 IEEE DAC/ISSCC Student Design Contest 1st Place


  • "Floorplan-driven high-level synthesis for distributed/shared-register architectures, " IPSJ Trans. on System LSI Design Methodology, vol. 1, pp. 78-90, 2008.
  • "Low-power LDPC code decoder architecture based on intermediate message compression technique, " IEICE Trans. Fundamentals, vol. E91-A, no. 4, pp. 1054-1061, 2008.
  • "A secure test technique for pipelined advanced encryption standard, " IEICE Trans. Information and Systems, vol. E91-D, no. 3, pp. 776-780, 2008.


Our research topics generally involve (1) SoC design; (2) SoC design methods; and (3) applications to image/communication processing

(1) SoC design:

Research topics within this field include signal processor design, network processor design, and security processor design. We have developed MPEG-4 and H.264/AVC processors, which offer dedicated hardware for adaptive motion estimates, low-powered LDPC (Low Density Parity check Codes) decoders with improved message-passing schedules, and elliptic curve cryptosystems with our word-based Montgomery multipliers. We also examine reconfigurable computing, including reconfigurable LDPC decoders that select optimal coding rates for the communication environment.

LDPC decoder chip (1st Place, 2006 IEEE DAC/ISSCC Student Design Contest).

(2) SoC design methodology:

Our research efforts in this area include floorplan-aware high-level synthesis, processor synthesis, and test design. In the deep submicron era, interconnection delays have emerged as the dominant factor for total circuit delays. Because this trend expected to continue over the next few years, interconnection delays are a critical issue, even in high-level or architecture-level SoC designs. we investigate floorplan-aware high-level syntheses in which module-floorplan strategies are integrated into high-level syntheses. We previously proposed a general register-/controller-distributed SoC model and are currently developing the corresponding dedicated synthesis systems. Our emphasis on processor synthesis should automatically synthesize and generate an energy-efficient and application-specific instruction set processor from a given application description. For example, we have optimized the SIMD functions in image processing based on the given application characteristics.

(3) Applications to image/communication processing:

An example of a system application design includes developing a pedestrian navigation system using mobile devices, such as PDAs and mobile phones. We are developing interactive pedestrian map generation, position detection, dedicated database designs, and route navigation algorithms.