Although the degree of integration in LSIs is exponentially increasing, what one designer can do it limited. Consequently, the design ability of each designer cannot keep pace with the increased size of design projects. One effective approach to mitigate this design productivity crisis is to increase the degree of abstraction in design. Our approach uses an easy-to-understand programming language and a small level of description.
High-Level Synthesis (or behavioral synthesis) is a method to design a dedicated hardware. In this method, a register transfer level (RTL) description is automatically synthesized upon considering hardware-specific concepts such as the register and clock synchronization based on a behavioral description that directly describes the algorithm of the target process.
Until the 1990s, most designs were manually performed. The introduction of a behavioral description drastically reduced the amount of design description compared to that of the RTL design and decreased the design errors, significantly improving design productivity. Additionally, depending on the application or constraints in the automatic synthesis, designing with behavioral descriptions may generate complex circuits, which were impossible with manual RTL design. Another advantage of the high-level synthesis is that the range of possible architecture can be expanded. The high-level synthesis technology will surely play an important role in the LSI design in the near future. (It already has some limited commercial cases such as NEC's high-level synthesis system, Cyber).
Although the fundamental theories for the high-level synthesis have already been established and research efforts are shifting toward commercial uses, circuits generated by a high-level synthesis are inferior to those designed manually in terms of their footprint, power consumption, etc. One reason is that the classical high-level synthesis method does not sufficiently consider other processes such as module layout, the computing unit, and logic synthesis. Other reasons for inferior characteristics include increasing the design scale and miniaturizing processes greatly impact the circuit performance due to control circuit and routing delays. This means that it is increasingly important to consider the final circuit generated at the high-level synthesis stage.
The High-Level Synthesis Group is currently conducting research in the following areas:
- High-level synthesis considering the floorplan (module layout)
- High-level synthesis design methodology that considers low-level processes
such as logic synthesis
Togawa Laboratory