# pynq-router (sw)

PYNQ-router for Vivado-HLS (2018 ver.)

## Types of router

|Name|Operation name|Description|
|:---|:---|:---|
|01|TBD|*Line-number-free* router for "PYNQ-Z1". Priority queue is implemented with circular array(non-parallel)|
|02|TBD|*Line-number-free* router for "PYNQ-Z1". Priority queue is implemented with circular array(parallel)|
|03|TBD|*Line-number-free* router for "PYNQ-Z1". Priority queue is implemented with heap(size:$`2^{15}`$)|
|04|TBD|*Line-number-free* router for "AVNET-Ultra96". Priority queue is implemented with heap(size:$`2^{16}`$)|
|05|TBD|*Low-memory-usage* router. No BRAMs are used for storing route information of each line.|

## Memo

* Vivado HLS 2018.2
* Vivado 2018.2

Options:
* Part: xc7z020clg400-1 (PYNQ-Z1), xczu3eg-sbva484-1-e (AVNET-Ultra96)
* Clock Period: 10.0 ns
* Clock Uncertainty: 3.0 ns (--> 3.25 ns)
* Synthesis strategy: ~~Vivado Synthesis Defaults~~ Flow_PerfOptimized_high
* Implementation strategy: ~~Vivado Implementation Defaults~~ Performance_ExplorePostRoutePhysOpt

## I/O 
* Input/Output: boardstr(8bit\*41472), seed(32bit), &status(32bit), return(1bit)

## Results
|Q|heap(seed:0)|c-array(seed:0)|OR|
|:---|:---|:---|:---|
|01|1|1|1|
|02|1|1|1|
|03|1|1|1|
|04|1|1|1|
|05|1|1|1|
|06|1|1|1|
|07|1|1|1|
|08|0|1|1|
|09|1|1|1|
|10|1|1|1|
|11|1|1|1|
|12|1|1|1|
|13|1|1|1|
|14|0|1|1|
|15|1|1|1|
|16|1|1|1|
|17|0|0|0|
|18|1|1|1|
|19|0|0|0|
|20|1|1|1|
|21|0|0|0|
|22|1|1|1|
|23|1|0|1|
|24|0|0|0|
|25|0|0|0|
|26|1|1|1|
|27|1|0|1|
|28|1|1|1|
|29|0|0|0|
|30|0|0|0|
|31|0|0|0|
|32|1|1|1|
|33|0|0|0|
|34|0|0|0|
|Total|22|22|24|