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hls_2018/router_02_boardstr/Makefile

+TARGET = sim
+OBJS = $(CPPS:.cpp=.o)
+CPPS = $(wildcard *.cpp)
+CXX = g++
+CXXFLAGS = -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -DSOFTWARE -DCALCTIME
+
+all: $(TARGET)
+
+$(TARGET): $(OBJS)
+	$(CXX) -O3 -o $@ $(OBJS)
+
+run:
+	python3 ../NLGenerator.py -x 20 -y 20 -z 6 -l 100;\
+	python3 ./gen_boardstr.py Q-20x20x5_100_10.txt |\
+	./$(TARGET) -
+
+
+clean:
+	rm *.o
+	rm $(TARGET)

hls_2018/router_02_boardstr/Makefile.cygwin

+TARGET = sim
+OBJS = $(CPPS:.cpp=.o)
+CPPS = $(wildcard *.cpp)
+CXX = g++
+CXXFLAGS = -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -DSOFTWARE -DCALCTIME
+
+all: $(TARGET)
+
+$(TARGET): $(OBJS)
+	$(CXX) -O3 -Wl,--stack,33554432 -o $@ $(OBJS)
+
+clean:
+	rm *.o
+	rm $(TARGET)

hls_2018/router_02_boardstr/README.md

+# 並列度の変更 (変更箇所)
+優先度キューに要素を挿入する際，要素の移動を並列して実行できる
+
+コードにいくつかの変更を加えることで並列度を変更可能
+
+## router.hpp
+以下の2箇所を変更する
+* #define PP **32** <-- 並列度
+* #define LOG_PP **5** <-- 並列度のlog2
+
+## router.cpp
+以下の5箇所を変更する
+* (in search func.) #pragma HLS ARRAY_PARTITION variable=pq_nodes cyclic factor=**32** dim=1 <-- 並列度
+* (in pq_push func.) #pragma HLS LOOP_TRIPCOUNT min=0 max=**31** <-- 並列度-1 (計3箇所)
+* (in pq_push func.) #pragma HLS LOOP_TRIPCOUNT min=0 max=**255** <-- キューの最大要素数/並列度-1
+

hls_2018/router_02_boardstr/ap_int.h

+/*
+ * Copyright 2012 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AESL_AP_SIM_H__
+#define __AESL_AP_SIM_H__
+
+#ifndef __cplusplus
+#error C++ is required to include this header file
+#else
+
+#include "etc/ap_int_sim.h"
+#include "etc/ap_fixed_sim.h"
+
+//Forward declaration
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N> class ap_fixed;
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N> class ap_ufixed;
+template<int _AP_W> class ap_int;
+template<int _AP_W> class ap_uint;
+
+//AP_INT
+//--------------------------------------------------------
+template<int _AP_W>
+class ap_int : public ap_private<_AP_W, true> {
+#ifdef _MSC_VER
+#pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+public:
+    typedef ap_private<_AP_W, true> Base;
+
+    //Constructor
+    INLINE ap_int(): Base() {}
+    template<int _AP_W2>
+    INLINE ap_int(const volatile ap_int<_AP_W2> &op):Base((const ap_private<_AP_W2,true> &)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_int(const ap_int<_AP_W2> &op):Base((const ap_private<_AP_W2,true> &)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_int(const ap_uint<_AP_W2> &op):Base((const ap_private<_AP_W2,false> &)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_int(const volatile ap_uint<_AP_W2> &op):Base((const ap_private<_AP_W2,false> &)(op)) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_int(const ap_range_ref<_AP_W2, _AP_S2>& ref):Base(ref) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_int(const ap_bit_ref<_AP_W2, _AP_S2>& ref):Base(ref) {}
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_int(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref):Base(ref) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                 :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                  :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                 :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                  :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_int(const ap_private<_AP_W2, _AP_S2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+                  _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+                  _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op):Base(op.to_ap_private()) {}
+
+#define CTOR(TYPE) \
+    INLINE ap_int(TYPE v):Base(v) {}
+    CTOR(bool)
+    CTOR(signed char)
+    CTOR(unsigned char)
+    CTOR(short)
+    CTOR(unsigned short)
+    CTOR(int)
+    CTOR(unsigned int)
+    CTOR(long)
+    CTOR(unsigned long)
+    CTOR(unsigned long long)
+    CTOR(long long)
+    CTOR(float)
+    CTOR(double)
+    CTOR(const char*)
+    CTOR(const std::string&)
+#undef CTOR
+    INLINE ap_int(const char* str, signed char rd):Base(str, rd) {}
+     //Assignment
+     //Another form of "write"
+    INLINE void operator = (const ap_int<_AP_W>& op2) volatile {
+      const_cast<ap_int*>(this)->operator = (op2);
+    }
+
+    INLINE void operator = (const volatile ap_int<_AP_W>& op2) volatile {
+      const_cast<Base*>(this)->operator = (op2);
+    }
+
+    INLINE ap_int<_AP_W>& operator = (const volatile ap_int<_AP_W>& op2) {
+      Base::operator = (const_cast<ap_int<_AP_W>& >(op2));
+        return *this;
+    }
+
+    INLINE ap_int<_AP_W>& operator = (const ap_int<_AP_W>& op2) {
+      Base::operator = ((const ap_private<_AP_W, true>&)op2);
+        return *this;
+    }
+};
+
+//AP_UINT
+//---------------------------------------------------------------
+template<int _AP_W>
+class ap_uint: public ap_private<_AP_W, false> {
+#ifdef _MSC_VER
+#pragma warning( disable : 4521 4522 )
+#endif
+public:
+    typedef ap_private<_AP_W, false> Base;
+    //Constructor
+    INLINE ap_uint(): Base() {}
+  INLINE ap_uint(const ap_uint<_AP_W>& op) :Base(dynamic_cast<const ap_private<_AP_W, false>&>(op)) {}
+  INLINE ap_uint(const volatile ap_uint<_AP_W>& op):Base(dynamic_cast<const volatile ap_private<_AP_W, false>&>(op)){}
+    template<int _AP_W2>
+    INLINE ap_uint(const volatile ap_uint<_AP_W2> &op):Base((const ap_private<_AP_W2, false>&)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_uint(const ap_uint<_AP_W2> &op) : Base((const ap_private<_AP_W2, false>&)(op)){}
+
+    template<int _AP_W2>
+    INLINE ap_uint(const ap_int<_AP_W2> &op) : Base((const ap_private<_AP_W2, true>&)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_uint(const volatile ap_int<_AP_W2> &op) : Base((const ap_private<_AP_W2, false>&)(op)) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_uint(const ap_range_ref<_AP_W2, _AP_S2>& ref):Base(ref) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_uint(const ap_bit_ref<_AP_W2, _AP_S2>& ref):Base(ref) {}
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_uint(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref):Base(ref) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                   :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                   :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                   :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                   :Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_uint(const ap_private<_AP_W2, _AP_S2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+                  _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+                  _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op):Base(op.to_ap_private()) {}
+
+#define CTOR(TYPE) \
+    INLINE ap_uint(TYPE v):Base(v) {}
+    CTOR(bool)
+    CTOR(signed char)
+    CTOR(unsigned char)
+    CTOR(short)
+    CTOR(unsigned short)
+    CTOR(int)
+    CTOR(unsigned int)
+    CTOR(long)
+    CTOR(unsigned long)
+    CTOR(unsigned long long)
+    CTOR(long long)
+    CTOR(float)
+    CTOR(double)
+    CTOR(const char*)
+    CTOR(const std::string&)
+#undef CTOR
+    INLINE ap_uint(const char* str, signed char rd):Base(str, rd) {}
+     //Assignment
+     //Another form of "write"
+    INLINE void operator = (const ap_uint<_AP_W>& op2) volatile {
+      Base::operator = (op2);
+    }
+
+    INLINE void operator = (const volatile ap_uint<_AP_W>& op2) volatile {
+      Base::operator = (op2);
+    }
+
+    INLINE ap_uint<_AP_W>& operator = (const volatile ap_uint<_AP_W>& op2) {
+      Base::operator = (op2);
+        return *this;
+    }
+
+    INLINE ap_uint<_AP_W>& operator = (const ap_uint<_AP_W>& op2) {
+      Base::operator = ((const ap_private<_AP_W, false>&)(op2));
+        return *this;
+    }
+};
+
+#define ap_bigint ap_int
+#define ap_biguint ap_uint
+
+//AP_FIXED
+//---------------------------------------------------------------------
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q = AP_TRN,
+         ap_o_mode _AP_O = AP_WRAP, int _AP_N = 0>
+class ap_fixed: public ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> {
+#ifdef _MSC_VER
+#pragma warning( disable : 4521 4522 )
+#endif
+public:
+    typedef ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> Base;
+     //Constructor
+    INLINE ap_fixed():Base() {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const ap_fixed<_AP_W2, _AP_I2,  _AP_Q2, _AP_O2,
+                    _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2,
+                    _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                   false, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_fixed(const ap_int<_AP_W2>& op):
+                   Base(ap_private<_AP_W2, true>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_fixed(const ap_uint<_AP_W2>& op):Base(ap_private<_AP_W2, false>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const volatile ap_fixed<_AP_W2, _AP_I2,  _AP_Q2, _AP_O2,
+                    _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                    true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2,
+                    _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                   false, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_fixed(const volatile ap_int<_AP_W2>& op):
+                   Base(ap_private<_AP_W2, true>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_fixed(const volatile ap_uint<_AP_W2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed(const ap_bit_ref<_AP_W2, _AP_S2>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed(const ap_range_ref<_AP_W2, _AP_S2>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_fixed(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed(const ap_private<_AP_W2, _AP_S2>& op):Base(op) {}
+
+ #define CTOR(TYPE) \
+    INLINE ap_fixed(TYPE v):Base(v) {}
+    CTOR(bool)
+    CTOR(signed char)
+    CTOR(unsigned char)
+    CTOR(short)
+    CTOR(unsigned short)
+    CTOR(int)
+    CTOR(unsigned int)
+    CTOR(long)
+    CTOR(unsigned long)
+    CTOR(unsigned long long)
+    CTOR(long long)
+    CTOR(float)
+    CTOR(double)
+    CTOR(const char*)
+    CTOR(const std::string&)
+#undef CTOR
+    INLINE ap_fixed(const char* str, signed char rd):Base(str, rd) {}
+
+    //Assignment
+    INLINE ap_fixed& operator = (const ap_fixed<_AP_W, _AP_I,
+                    _AP_Q, _AP_O, _AP_N>& op) {
+      Base::operator = (op);
+        return *this;
+    }
+
+  INLINE ap_fixed& operator = (const volatile ap_fixed<_AP_W, _AP_I,
+                    _AP_Q, _AP_O, _AP_N>& op) {
+        Base::operator = (op);
+        return *this;
+    }
+};
+
+//AP_ UFIXED
+//--- ----------------------------------------------------------------
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q = AP_TRN,
+         ap_o_mode _AP_O = AP_WRAP, int _AP_N = 0>
+class ap_ufixed : public ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> {
+#ifdef _MSC_VER
+#pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+public:
+    typedef ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> Base;
+
+     //Constructor
+    INLINE ap_ufixed():Base() {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2,
+                     _AP_O2, _AP_N2>& op) : Base(ap_fixed_base<_AP_W2,
+                     _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const ap_ufixed<_AP_W2, _AP_I2,  _AP_Q2,
+                     _AP_O2, _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                      false, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_ufixed(const ap_int<_AP_W2>& op):
+      Base((const ap_private<_AP_W2, true>&)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_ufixed(const ap_uint<_AP_W2>& op):
+      Base((const ap_private<_AP_W2, false>&)(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2,
+                     _AP_O2, _AP_N2>& op) : Base(ap_fixed_base<_AP_W2,
+                     _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const volatile ap_ufixed<_AP_W2, _AP_I2,  _AP_Q2,
+                     _AP_O2, _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                      false, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_ufixed(const volatile ap_int<_AP_W2>& op):
+                     Base(ap_private<_AP_W2, true>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_ufixed(const volatile ap_uint<_AP_W2>& op):
+                     Base(ap_private<_AP_W2, false>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+                     _AP_O2, _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_ufixed(const ap_bit_ref<_AP_W2, _AP_S2>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_ufixed(const ap_range_ref<_AP_W2, _AP_S2>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_ufixed(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_ufixed(const ap_private<_AP_W2, _AP_S2>& op):Base(op) {}
+
+ #define CTOR(TYPE) \
+    INLINE ap_ufixed(TYPE v):Base(v) {}
+    CTOR(bool)
+    CTOR(signed char)
+    CTOR(unsigned char)
+    CTOR(short)
+    CTOR(unsigned short)
+    CTOR(int)
+    CTOR(unsigned int)
+    CTOR(long)
+    CTOR(unsigned long)
+    CTOR(unsigned long long)
+    CTOR(long long)
+    CTOR(float)
+    CTOR(double)
+    CTOR(const char*)
+    CTOR(const std::string&)
+#undef CTOR
+    INLINE ap_ufixed(const char* str, signed char rd):Base(str, rd) {}
+
+    //Assignment
+    INLINE ap_ufixed& operator = (const ap_ufixed<_AP_W, _AP_I,
+                    _AP_Q, _AP_O, _AP_N>& op) {
+      Base::operator = (op);
+        return *this;
+    }
+
+    INLINE ap_ufixed& operator = (const volatile ap_ufixed<_AP_W, _AP_I,
+                    _AP_Q, _AP_O, _AP_N>& op) {
+        Base::V = const_cast<ap_ufixed&>(op);
+        return *this;
+    }
+};
+
+#if defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED)
+template<int _AP_W>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_int<_AP_W> &op,
+                     const std::string &name) {
+    if (tf)
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+
+template<int _AP_W>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_uint<_AP_W> &op,
+                     const std::string &name) {
+    if (tf)
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N >&op, const std::string &name) {
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N >&op, const std::string &name) {
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+#endif /* #if defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED) */
+#endif /* #ifndef __cplusplus */
+#endif /* #ifndef __AESL_AP_SIM_H__ */
\ No newline at end of file

hls_2018/router_02_boardstr/bitstream/04/router_design.tcl

+
+################################################################
+# This is a generated script based on design: router_design
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2018.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source router_design_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z020clg400-1
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name router_design
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_gpio:2.0\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:hls:pynqrouter:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+  # Create ports
+  set LD [ create_bd_port -dir O -from 3 -to 0 LD ]
+
+  # Create instance: axi_gpio_0, and set properties
+  set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+  set_property -dict [ list \
+   CONFIG.C_GPIO_WIDTH {4} \
+ ] $axi_gpio_0
+
+  # Create instance: processing_system7_0, and set properties
+  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+  set_property -dict [ list \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \
+   CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \
+   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
+   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+   CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \
+   CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
+   CONFIG.PCW_CAN0_CAN0_IO {<Select>} \
+   CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
+   CONFIG.PCW_CAN0_GRP_CLK_IO {<Select>} \
+   CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
+   CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
+   CONFIG.PCW_CAN1_CAN1_IO {<Select>} \
+   CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
+   CONFIG.PCW_CAN1_GRP_CLK_IO {<Select>} \
+   CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
+   CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_CLK0_FREQ {100000000} \
+   CONFIG.PCW_CLK1_FREQ {10000000} \
+   CONFIG.PCW_CLK2_FREQ {10000000} \
+   CONFIG.PCW_CLK3_FREQ {10000000} \
+   CONFIG.PCW_CORE0_FIQ_INTR {0} \
+   CONFIG.PCW_CORE0_IRQ_INTR {0} \
+   CONFIG.PCW_CORE1_FIQ_INTR {0} \
+   CONFIG.PCW_CORE1_IRQ_INTR {0} \
+   CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \
+   CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
+   CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \
+   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \
+   CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
+   CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
+   CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_0 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_1 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_2 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_3 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {<Select>} \
+   CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
+   CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+   CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DM_WIDTH {4} \
+   CONFIG.PCW_DQS_WIDTH {4} \
+   CONFIG.PCW_DQ_WIDTH {32} \
+   CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
+   CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+   CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+   CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
+   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET0_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET0_RESET_IO {MIO 9} \
+   CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
+   CONFIG.PCW_ENET1_ENET1_IO {<Select>} \
+   CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
+   CONFIG.PCW_ENET1_GRP_MDIO_IO {<Select>} \
+   CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
+   CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET1_RESET_IO {<Select>} \
+   CONFIG.PCW_ENET_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_EN_4K_TIMER {0} \
+   CONFIG.PCW_EN_CAN0 {0} \
+   CONFIG.PCW_EN_CAN1 {0} \
+   CONFIG.PCW_EN_CLK0_PORT {1} \
+   CONFIG.PCW_EN_CLK1_PORT {0} \
+   CONFIG.PCW_EN_CLK2_PORT {0} \
+   CONFIG.PCW_EN_CLK3_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
+   CONFIG.PCW_EN_DDR {1} \
+   CONFIG.PCW_EN_EMIO_CAN0 {0} \
+   CONFIG.PCW_EN_EMIO_CAN1 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_ENET0 {0} \
+   CONFIG.PCW_EN_EMIO_ENET1 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {0} \
+   CONFIG.PCW_EN_EMIO_I2C0 {0} \
+   CONFIG.PCW_EN_EMIO_I2C1 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_PJTAG {0} \
+   CONFIG.PCW_EN_EMIO_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_SPI0 {0} \
+   CONFIG.PCW_EN_EMIO_SPI1 {0} \
+   CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
+   CONFIG.PCW_EN_EMIO_TRACE {0} \
+   CONFIG.PCW_EN_EMIO_TTC0 {0} \
+   CONFIG.PCW_EN_EMIO_TTC1 {0} \
+   CONFIG.PCW_EN_EMIO_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_WDT {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+   CONFIG.PCW_EN_ENET0 {1} \
+   CONFIG.PCW_EN_ENET1 {0} \
+   CONFIG.PCW_EN_GPIO {1} \
+   CONFIG.PCW_EN_I2C0 {0} \
+   CONFIG.PCW_EN_I2C1 {0} \
+   CONFIG.PCW_EN_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_PJTAG {0} \
+   CONFIG.PCW_EN_PTP_ENET0 {0} \
+   CONFIG.PCW_EN_PTP_ENET1 {0} \
+   CONFIG.PCW_EN_QSPI {1} \
+   CONFIG.PCW_EN_RST0_PORT {1} \
+   CONFIG.PCW_EN_RST1_PORT {0} \
+   CONFIG.PCW_EN_RST2_PORT {0} \
+   CONFIG.PCW_EN_RST3_PORT {0} \
+   CONFIG.PCW_EN_SDIO0 {1} \
+   CONFIG.PCW_EN_SDIO1 {0} \
+   CONFIG.PCW_EN_SMC {0} \
+   CONFIG.PCW_EN_SPI0 {0} \
+   CONFIG.PCW_EN_SPI1 {0} \
+   CONFIG.PCW_EN_TRACE {0} \
+   CONFIG.PCW_EN_TTC0 {0} \
+   CONFIG.PCW_EN_TTC1 {0} \
+   CONFIG.PCW_EN_UART0 {1} \
+   CONFIG.PCW_EN_UART1 {0} \
+   CONFIG.PCW_EN_USB0 {1} \
+   CONFIG.PCW_EN_USB1 {0} \
+   CONFIG.PCW_EN_WDT {0} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+   CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+   CONFIG.PCW_FTM_CTI_IN0 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN1 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN2 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN3 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT0 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT1 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT2 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT3 {<Select>} \
+   CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
+   CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
+   CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+   CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
+   CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C0_GRP_INT_IO {<Select>} \
+   CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
+   CONFIG.PCW_I2C0_I2C0_IO {<Select>} \
+   CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C0_RESET_IO {<Select>} \
+   CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
+   CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C1_GRP_INT_IO {<Select>} \
+   CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
+   CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
+   CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C1_RESET_IO {<Select>} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+   CONFIG.PCW_I2C_RESET_ENABLE {1} \
+   CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
+   CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
+   CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
+   CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+   CONFIG.PCW_IRQ_F2P_INTR {0} \
+   CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
+   CONFIG.PCW_MIO_0_DIRECTION {inout} \
+   CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_0_PULLUP {enabled} \
+   CONFIG.PCW_MIO_0_SLEW {slow} \
+   CONFIG.PCW_MIO_10_DIRECTION {inout} \
+   CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_10_PULLUP {enabled} \
+   CONFIG.PCW_MIO_10_SLEW {slow} \
+   CONFIG.PCW_MIO_11_DIRECTION {inout} \
+   CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_11_PULLUP {enabled} \
+   CONFIG.PCW_MIO_11_SLEW {slow} \
+   CONFIG.PCW_MIO_12_DIRECTION {inout} \
+   CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_12_PULLUP {enabled} \
+   CONFIG.PCW_MIO_12_SLEW {slow} \
+   CONFIG.PCW_MIO_13_DIRECTION {inout} \
+   CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_13_PULLUP {enabled} \
+   CONFIG.PCW_MIO_13_SLEW {slow} \
+   CONFIG.PCW_MIO_14_DIRECTION {in} \
+   CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_14_PULLUP {enabled} \
+   CONFIG.PCW_MIO_14_SLEW {slow} \
+   CONFIG.PCW_MIO_15_DIRECTION {out} \
+   CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_15_PULLUP {enabled} \
+   CONFIG.PCW_MIO_15_SLEW {slow} \
+   CONFIG.PCW_MIO_16_DIRECTION {out} \
+   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_16_PULLUP {enabled} \
+   CONFIG.PCW_MIO_16_SLEW {slow} \
+   CONFIG.PCW_MIO_17_DIRECTION {out} \
+   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_17_PULLUP {enabled} \
+   CONFIG.PCW_MIO_17_SLEW {slow} \
+   CONFIG.PCW_MIO_18_DIRECTION {out} \
+   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_18_PULLUP {enabled} \
+   CONFIG.PCW_MIO_18_SLEW {slow} \
+   CONFIG.PCW_MIO_19_DIRECTION {out} \
+   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_19_PULLUP {enabled} \
+   CONFIG.PCW_MIO_19_SLEW {slow} \
+   CONFIG.PCW_MIO_1_DIRECTION {out} \
+   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_1_PULLUP {enabled} \
+   CONFIG.PCW_MIO_1_SLEW {slow} \
+   CONFIG.PCW_MIO_20_DIRECTION {out} \
+   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_20_PULLUP {enabled} \
+   CONFIG.PCW_MIO_20_SLEW {slow} \
+   CONFIG.PCW_MIO_21_DIRECTION {out} \
+   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_21_PULLUP {enabled} \
+   CONFIG.PCW_MIO_21_SLEW {slow} \
+   CONFIG.PCW_MIO_22_DIRECTION {in} \
+   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_22_PULLUP {enabled} \
+   CONFIG.PCW_MIO_22_SLEW {slow} \
+   CONFIG.PCW_MIO_23_DIRECTION {in} \
+   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_23_PULLUP {enabled} \
+   CONFIG.PCW_MIO_23_SLEW {slow} \
+   CONFIG.PCW_MIO_24_DIRECTION {in} \
+   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_24_PULLUP {enabled} \
+   CONFIG.PCW_MIO_24_SLEW {slow} \
+   CONFIG.PCW_MIO_25_DIRECTION {in} \
+   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_25_PULLUP {enabled} \
+   CONFIG.PCW_MIO_25_SLEW {slow} \
+   CONFIG.PCW_MIO_26_DIRECTION {in} \
+   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_26_PULLUP {enabled} \
+   CONFIG.PCW_MIO_26_SLEW {slow} \
+   CONFIG.PCW_MIO_27_DIRECTION {in} \
+   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_27_PULLUP {enabled} \
+   CONFIG.PCW_MIO_27_SLEW {slow} \
+   CONFIG.PCW_MIO_28_DIRECTION {inout} \
+   CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_28_PULLUP {enabled} \
+   CONFIG.PCW_MIO_28_SLEW {slow} \
+   CONFIG.PCW_MIO_29_DIRECTION {in} \
+   CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_29_PULLUP {enabled} \
+   CONFIG.PCW_MIO_29_SLEW {slow} \
+   CONFIG.PCW_MIO_2_DIRECTION {inout} \
+   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_2_PULLUP {disabled} \
+   CONFIG.PCW_MIO_2_SLEW {slow} \
+   CONFIG.PCW_MIO_30_DIRECTION {out} \
+   CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_30_PULLUP {enabled} \
+   CONFIG.PCW_MIO_30_SLEW {slow} \
+   CONFIG.PCW_MIO_31_DIRECTION {in} \
+   CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_31_PULLUP {enabled} \
+   CONFIG.PCW_MIO_31_SLEW {slow} \
+   CONFIG.PCW_MIO_32_DIRECTION {inout} \
+   CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_32_PULLUP {enabled} \
+   CONFIG.PCW_MIO_32_SLEW {slow} \
+   CONFIG.PCW_MIO_33_DIRECTION {inout} \
+   CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_33_PULLUP {enabled} \
+   CONFIG.PCW_MIO_33_SLEW {slow} \
+   CONFIG.PCW_MIO_34_DIRECTION {inout} \
+   CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_34_PULLUP {enabled} \
+   CONFIG.PCW_MIO_34_SLEW {slow} \
+   CONFIG.PCW_MIO_35_DIRECTION {inout} \
+   CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_35_PULLUP {enabled} \
+   CONFIG.PCW_MIO_35_SLEW {slow} \
+   CONFIG.PCW_MIO_36_DIRECTION {in} \
+   CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_36_PULLUP {enabled} \
+   CONFIG.PCW_MIO_36_SLEW {slow} \
+   CONFIG.PCW_MIO_37_DIRECTION {inout} \
+   CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_37_PULLUP {enabled} \
+   CONFIG.PCW_MIO_37_SLEW {slow} \
+   CONFIG.PCW_MIO_38_DIRECTION {inout} \
+   CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_38_PULLUP {enabled} \
+   CONFIG.PCW_MIO_38_SLEW {slow} \
+   CONFIG.PCW_MIO_39_DIRECTION {inout} \
+   CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_39_PULLUP {enabled} \
+   CONFIG.PCW_MIO_39_SLEW {slow} \
+   CONFIG.PCW_MIO_3_DIRECTION {inout} \
+   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_3_PULLUP {disabled} \
+   CONFIG.PCW_MIO_3_SLEW {slow} \
+   CONFIG.PCW_MIO_40_DIRECTION {inout} \
+   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_40_PULLUP {enabled} \
+   CONFIG.PCW_MIO_40_SLEW {slow} \
+   CONFIG.PCW_MIO_41_DIRECTION {inout} \
+   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_41_PULLUP {enabled} \
+   CONFIG.PCW_MIO_41_SLEW {slow} \
+   CONFIG.PCW_MIO_42_DIRECTION {inout} \
+   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_42_PULLUP {enabled} \
+   CONFIG.PCW_MIO_42_SLEW {slow} \
+   CONFIG.PCW_MIO_43_DIRECTION {inout} \
+   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_43_PULLUP {enabled} \
+   CONFIG.PCW_MIO_43_SLEW {slow} \
+   CONFIG.PCW_MIO_44_DIRECTION {inout} \
+   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_44_PULLUP {enabled} \
+   CONFIG.PCW_MIO_44_SLEW {slow} \
+   CONFIG.PCW_MIO_45_DIRECTION {inout} \
+   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_45_PULLUP {enabled} \
+   CONFIG.PCW_MIO_45_SLEW {slow} \
+   CONFIG.PCW_MIO_46_DIRECTION {out} \
+   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_46_PULLUP {enabled} \
+   CONFIG.PCW_MIO_46_SLEW {slow} \
+   CONFIG.PCW_MIO_47_DIRECTION {in} \
+   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_47_PULLUP {enabled} \
+   CONFIG.PCW_MIO_47_SLEW {slow} \
+   CONFIG.PCW_MIO_48_DIRECTION {inout} \
+   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_48_PULLUP {enabled} \
+   CONFIG.PCW_MIO_48_SLEW {slow} \
+   CONFIG.PCW_MIO_49_DIRECTION {inout} \
+   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_49_PULLUP {enabled} \
+   CONFIG.PCW_MIO_49_SLEW {slow} \
+   CONFIG.PCW_MIO_4_DIRECTION {inout} \
+   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_4_PULLUP {disabled} \
+   CONFIG.PCW_MIO_4_SLEW {slow} \
+   CONFIG.PCW_MIO_50_DIRECTION {inout} \
+   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_50_PULLUP {enabled} \
+   CONFIG.PCW_MIO_50_SLEW {slow} \
+   CONFIG.PCW_MIO_51_DIRECTION {inout} \
+   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_51_PULLUP {enabled} \
+   CONFIG.PCW_MIO_51_SLEW {slow} \
+   CONFIG.PCW_MIO_52_DIRECTION {out} \
+   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_52_PULLUP {enabled} \
+   CONFIG.PCW_MIO_52_SLEW {slow} \
+   CONFIG.PCW_MIO_53_DIRECTION {inout} \
+   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_53_PULLUP {enabled} \
+   CONFIG.PCW_MIO_53_SLEW {slow} \
+   CONFIG.PCW_MIO_5_DIRECTION {inout} \
+   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_5_PULLUP {disabled} \
+   CONFIG.PCW_MIO_5_SLEW {slow} \
+   CONFIG.PCW_MIO_6_DIRECTION {out} \
+   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_6_PULLUP {disabled} \
+   CONFIG.PCW_MIO_6_SLEW {slow} \
+   CONFIG.PCW_MIO_7_DIRECTION {out} \
+   CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_7_PULLUP {disabled} \
+   CONFIG.PCW_MIO_7_SLEW {slow} \
+   CONFIG.PCW_MIO_8_DIRECTION {out} \
+   CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_8_PULLUP {disabled} \
+   CONFIG.PCW_MIO_8_SLEW {slow} \
+   CONFIG.PCW_MIO_9_DIRECTION {out} \
+   CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_9_PULLUP {enabled} \
+   CONFIG.PCW_MIO_9_SLEW {slow} \
+   CONFIG.PCW_MIO_PRIMITIVE {54} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \
+   CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_NAND_CYCLES_T_AR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_REA {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_WC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_WP {1} \
+   CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+   CONFIG.PCW_NAND_GRP_D8_IO {<Select>} \
+   CONFIG.PCW_NAND_NAND_IO {<Select>} \
+   CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_CS1_WE_TIME {0} \
+   CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_A25_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS0_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS1_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_IO {<Select>} \
+   CONFIG.PCW_NOR_NOR_IO {<Select>} \
+   CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
+   CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
+   CONFIG.PCW_P2F_CAN0_INTR {0} \
+   CONFIG.PCW_P2F_CAN1_INTR {0} \
+   CONFIG.PCW_P2F_CTI_INTR {0} \
+   CONFIG.PCW_P2F_DMAC0_INTR {0} \
+   CONFIG.PCW_P2F_DMAC1_INTR {0} \
+   CONFIG.PCW_P2F_DMAC2_INTR {0} \
+   CONFIG.PCW_P2F_DMAC3_INTR {0} \
+   CONFIG.PCW_P2F_DMAC4_INTR {0} \
+   CONFIG.PCW_P2F_DMAC5_INTR {0} \
+   CONFIG.PCW_P2F_DMAC6_INTR {0} \
+   CONFIG.PCW_P2F_DMAC7_INTR {0} \
+   CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
+   CONFIG.PCW_P2F_ENET0_INTR {0} \
+   CONFIG.PCW_P2F_ENET1_INTR {0} \
+   CONFIG.PCW_P2F_GPIO_INTR {0} \
+   CONFIG.PCW_P2F_I2C0_INTR {0} \
+   CONFIG.PCW_P2F_I2C1_INTR {0} \
+   CONFIG.PCW_P2F_QSPI_INTR {0} \
+   CONFIG.PCW_P2F_SDIO0_INTR {0} \
+   CONFIG.PCW_P2F_SDIO1_INTR {0} \
+   CONFIG.PCW_P2F_SMC_INTR {0} \
+   CONFIG.PCW_P2F_SPI0_INTR {0} \
+   CONFIG.PCW_P2F_SPI1_INTR {0} \
+   CONFIG.PCW_P2F_UART0_INTR {0} \
+   CONFIG.PCW_P2F_UART1_INTR {0} \
+   CONFIG.PCW_P2F_USB0_INTR {0} \
+   CONFIG.PCW_P2F_USB1_INTR {0} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
+   CONFIG.PCW_PACKAGE_NAME {clg400} \
+   CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
+   CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
+   CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
+   CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
+   CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_IO1_IO {<Select>} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+   CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
+   CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+   CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+   CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
+   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_POW_IO {<Select>} \
+   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_WP_IO {<Select>} \
+   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+   CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_CD_IO {<Select>} \
+   CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_POW_IO {<Select>} \
+   CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_WP_IO {<Select>} \
+   CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SD1_SD1_IO {<Select>} \
+   CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
+   CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
+   CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
+   CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
+   CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
+   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+   CONFIG.PCW_SMC_CYCLE_T0 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T1 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T2 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T3 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T4 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T5 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T6 {NA} \
+   CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
+   CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS0_IO {<Select>} \
+   CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS2_IO {<Select>} \
+   CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
+   CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI0_SPI0_IO {<Select>} \
+   CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
+   CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS0_IO {<Select>} \
+   CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS2_IO {<Select>} \
+   CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
+   CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI1_SPI1_IO {<Select>} \
+   CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+   CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
+   CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
+   CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
+   CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
+   CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_16BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_2BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_32BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_4BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_8BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
+   CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
+   CONFIG.PCW_TRACE_TRACE_IO {<Select>} \
+   CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
+   CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TTC0_TTC0_IO {<Select>} \
+   CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
+   CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TTC1_TTC1_IO {<Select>} \
+   CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
+   CONFIG.PCW_UART0_BAUD_RATE {115200} \
+   CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART0_GRP_FULL_IO {<Select>} \
+   CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
+   CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
+   CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
+   CONFIG.PCW_UART1_BAUD_RATE {115200} \
+   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART1_GRP_FULL_IO {<Select>} \
+   CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
+   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_UART1_UART1_IO {<Select>} \
+   CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \
+   CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
+   CONFIG.PCW_UIPARAM_DDR_AL {0} \
+   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+   CONFIG.PCW_UIPARAM_DDR_BL {8} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \
+   CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+   CONFIG.PCW_UIPARAM_DDR_CL {7} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
+   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+   CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+   CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
+   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \
+   CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
+   CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
+   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
+   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+   CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+   CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
+   CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
+   CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
+   CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB0_RESET_ENABLE {1} \
+   CONFIG.PCW_USB0_RESET_IO {MIO 46} \
+   CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+   CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
+   CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
+   CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB1_RESET_ENABLE {0} \
+   CONFIG.PCW_USB1_RESET_IO {<Select>} \
+   CONFIG.PCW_USB1_USB1_IO {<Select>} \
+   CONFIG.PCW_USB_RESET_ENABLE {1} \
+   CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
+   CONFIG.PCW_USE_AXI_NONSECURE {0} \
+   CONFIG.PCW_USE_CORESIGHT {0} \
+   CONFIG.PCW_USE_CROSS_TRIGGER {0} \
+   CONFIG.PCW_USE_CR_FABRIC {1} \
+   CONFIG.PCW_USE_DDR_BYPASS {0} \
+   CONFIG.PCW_USE_DEBUG {0} \
+   CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
+   CONFIG.PCW_USE_DMA0 {0} \
+   CONFIG.PCW_USE_DMA1 {0} \
+   CONFIG.PCW_USE_DMA2 {0} \
+   CONFIG.PCW_USE_DMA3 {0} \
+   CONFIG.PCW_USE_EXPANDED_IOP {0} \
+   CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
+   CONFIG.PCW_USE_HIGH_OCM {0} \
+   CONFIG.PCW_USE_M_AXI_GP0 {1} \
+   CONFIG.PCW_USE_M_AXI_GP1 {0} \
+   CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
+   CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_S_AXI_ACP {0} \
+   CONFIG.PCW_USE_S_AXI_GP0 {0} \
+   CONFIG.PCW_USE_S_AXI_GP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {0} \
+   CONFIG.PCW_USE_S_AXI_HP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP2 {0} \
+   CONFIG.PCW_USE_S_AXI_HP3 {0} \
+   CONFIG.PCW_USE_TRACE {0} \
+   CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
+   CONFIG.PCW_VALUE_SILVERSION {3} \
+   CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_WDT_WDT_IO {<Select>} \
+ ] $processing_system7_0
+
+  # Create instance: ps7_0_axi_periph, and set properties
+  set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps7_0_axi_periph
+
+  # Create instance: pynqrouter_0, and set properties
+  set pynqrouter_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:pynqrouter:1.0 pynqrouter_0 ]
+
+  # Create instance: rst_ps7_0_100M, and set properties
+  set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ]
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins pynqrouter_0/s_axi_AXI4LS]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+
+  # Create port connections
+  connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports LD] [get_bd_pins axi_gpio_0/gpio_io_o]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pynqrouter_0/ap_clk] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk]
+  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
+  connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn]
+  connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pynqrouter_0/ap_rst_n] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
+  create_bd_addr_seg -range 0x00040000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pynqrouter_0/s_axi_AXI4LS/Reg] SEG_pynqrouter_0_Reg
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls_2018/router_02_boardstr/bitstream/16/router_design.tcl

+
+################################################################
+# This is a generated script based on design: router_design
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2018.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source router_design_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z020clg400-1
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name router_design
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_gpio:2.0\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:hls:pynqrouter:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+  # Create ports
+  set LD [ create_bd_port -dir O -from 3 -to 0 LD ]
+
+  # Create instance: axi_gpio_0, and set properties
+  set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+  set_property -dict [ list \
+   CONFIG.C_GPIO_WIDTH {4} \
+ ] $axi_gpio_0
+
+  # Create instance: processing_system7_0, and set properties
+  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+  set_property -dict [ list \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \
+   CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \
+   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
+   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+   CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \
+   CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
+   CONFIG.PCW_CAN0_CAN0_IO {<Select>} \
+   CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
+   CONFIG.PCW_CAN0_GRP_CLK_IO {<Select>} \
+   CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
+   CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
+   CONFIG.PCW_CAN1_CAN1_IO {<Select>} \
+   CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
+   CONFIG.PCW_CAN1_GRP_CLK_IO {<Select>} \
+   CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
+   CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_CLK0_FREQ {100000000} \
+   CONFIG.PCW_CLK1_FREQ {10000000} \
+   CONFIG.PCW_CLK2_FREQ {10000000} \
+   CONFIG.PCW_CLK3_FREQ {10000000} \
+   CONFIG.PCW_CORE0_FIQ_INTR {0} \
+   CONFIG.PCW_CORE0_IRQ_INTR {0} \
+   CONFIG.PCW_CORE1_FIQ_INTR {0} \
+   CONFIG.PCW_CORE1_IRQ_INTR {0} \
+   CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \
+   CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
+   CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \
+   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \
+   CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
+   CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
+   CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_0 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_1 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_2 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_3 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {<Select>} \
+   CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
+   CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+   CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DM_WIDTH {4} \
+   CONFIG.PCW_DQS_WIDTH {4} \
+   CONFIG.PCW_DQ_WIDTH {32} \
+   CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
+   CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+   CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+   CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
+   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET0_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET0_RESET_IO {MIO 9} \
+   CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
+   CONFIG.PCW_ENET1_ENET1_IO {<Select>} \
+   CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
+   CONFIG.PCW_ENET1_GRP_MDIO_IO {<Select>} \
+   CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
+   CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET1_RESET_IO {<Select>} \
+   CONFIG.PCW_ENET_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_EN_4K_TIMER {0} \
+   CONFIG.PCW_EN_CAN0 {0} \
+   CONFIG.PCW_EN_CAN1 {0} \
+   CONFIG.PCW_EN_CLK0_PORT {1} \
+   CONFIG.PCW_EN_CLK1_PORT {0} \
+   CONFIG.PCW_EN_CLK2_PORT {0} \
+   CONFIG.PCW_EN_CLK3_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
+   CONFIG.PCW_EN_DDR {1} \
+   CONFIG.PCW_EN_EMIO_CAN0 {0} \
+   CONFIG.PCW_EN_EMIO_CAN1 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_ENET0 {0} \
+   CONFIG.PCW_EN_EMIO_ENET1 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {0} \
+   CONFIG.PCW_EN_EMIO_I2C0 {0} \
+   CONFIG.PCW_EN_EMIO_I2C1 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_PJTAG {0} \
+   CONFIG.PCW_EN_EMIO_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_SPI0 {0} \
+   CONFIG.PCW_EN_EMIO_SPI1 {0} \
+   CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
+   CONFIG.PCW_EN_EMIO_TRACE {0} \
+   CONFIG.PCW_EN_EMIO_TTC0 {0} \
+   CONFIG.PCW_EN_EMIO_TTC1 {0} \
+   CONFIG.PCW_EN_EMIO_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_WDT {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+   CONFIG.PCW_EN_ENET0 {1} \
+   CONFIG.PCW_EN_ENET1 {0} \
+   CONFIG.PCW_EN_GPIO {1} \
+   CONFIG.PCW_EN_I2C0 {0} \
+   CONFIG.PCW_EN_I2C1 {0} \
+   CONFIG.PCW_EN_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_PJTAG {0} \
+   CONFIG.PCW_EN_PTP_ENET0 {0} \
+   CONFIG.PCW_EN_PTP_ENET1 {0} \
+   CONFIG.PCW_EN_QSPI {1} \
+   CONFIG.PCW_EN_RST0_PORT {1} \
+   CONFIG.PCW_EN_RST1_PORT {0} \
+   CONFIG.PCW_EN_RST2_PORT {0} \
+   CONFIG.PCW_EN_RST3_PORT {0} \
+   CONFIG.PCW_EN_SDIO0 {1} \
+   CONFIG.PCW_EN_SDIO1 {0} \
+   CONFIG.PCW_EN_SMC {0} \
+   CONFIG.PCW_EN_SPI0 {0} \
+   CONFIG.PCW_EN_SPI1 {0} \
+   CONFIG.PCW_EN_TRACE {0} \
+   CONFIG.PCW_EN_TTC0 {0} \
+   CONFIG.PCW_EN_TTC1 {0} \
+   CONFIG.PCW_EN_UART0 {1} \
+   CONFIG.PCW_EN_UART1 {0} \
+   CONFIG.PCW_EN_USB0 {1} \
+   CONFIG.PCW_EN_USB1 {0} \
+   CONFIG.PCW_EN_WDT {0} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+   CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+   CONFIG.PCW_FTM_CTI_IN0 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN1 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN2 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN3 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT0 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT1 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT2 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT3 {<Select>} \
+   CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
+   CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
+   CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+   CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
+   CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C0_GRP_INT_IO {<Select>} \
+   CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
+   CONFIG.PCW_I2C0_I2C0_IO {<Select>} \
+   CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C0_RESET_IO {<Select>} \
+   CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
+   CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C1_GRP_INT_IO {<Select>} \
+   CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
+   CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
+   CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C1_RESET_IO {<Select>} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+   CONFIG.PCW_I2C_RESET_ENABLE {1} \
+   CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
+   CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
+   CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
+   CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+   CONFIG.PCW_IRQ_F2P_INTR {0} \
+   CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
+   CONFIG.PCW_MIO_0_DIRECTION {inout} \
+   CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_0_PULLUP {enabled} \
+   CONFIG.PCW_MIO_0_SLEW {slow} \
+   CONFIG.PCW_MIO_10_DIRECTION {inout} \
+   CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_10_PULLUP {enabled} \
+   CONFIG.PCW_MIO_10_SLEW {slow} \
+   CONFIG.PCW_MIO_11_DIRECTION {inout} \
+   CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_11_PULLUP {enabled} \
+   CONFIG.PCW_MIO_11_SLEW {slow} \
+   CONFIG.PCW_MIO_12_DIRECTION {inout} \
+   CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_12_PULLUP {enabled} \
+   CONFIG.PCW_MIO_12_SLEW {slow} \
+   CONFIG.PCW_MIO_13_DIRECTION {inout} \
+   CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_13_PULLUP {enabled} \
+   CONFIG.PCW_MIO_13_SLEW {slow} \
+   CONFIG.PCW_MIO_14_DIRECTION {in} \
+   CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_14_PULLUP {enabled} \
+   CONFIG.PCW_MIO_14_SLEW {slow} \
+   CONFIG.PCW_MIO_15_DIRECTION {out} \
+   CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_15_PULLUP {enabled} \
+   CONFIG.PCW_MIO_15_SLEW {slow} \
+   CONFIG.PCW_MIO_16_DIRECTION {out} \
+   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_16_PULLUP {enabled} \
+   CONFIG.PCW_MIO_16_SLEW {slow} \
+   CONFIG.PCW_MIO_17_DIRECTION {out} \
+   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_17_PULLUP {enabled} \
+   CONFIG.PCW_MIO_17_SLEW {slow} \
+   CONFIG.PCW_MIO_18_DIRECTION {out} \
+   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_18_PULLUP {enabled} \
+   CONFIG.PCW_MIO_18_SLEW {slow} \
+   CONFIG.PCW_MIO_19_DIRECTION {out} \
+   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_19_PULLUP {enabled} \
+   CONFIG.PCW_MIO_19_SLEW {slow} \
+   CONFIG.PCW_MIO_1_DIRECTION {out} \
+   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_1_PULLUP {enabled} \
+   CONFIG.PCW_MIO_1_SLEW {slow} \
+   CONFIG.PCW_MIO_20_DIRECTION {out} \
+   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_20_PULLUP {enabled} \
+   CONFIG.PCW_MIO_20_SLEW {slow} \
+   CONFIG.PCW_MIO_21_DIRECTION {out} \
+   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_21_PULLUP {enabled} \
+   CONFIG.PCW_MIO_21_SLEW {slow} \
+   CONFIG.PCW_MIO_22_DIRECTION {in} \
+   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_22_PULLUP {enabled} \
+   CONFIG.PCW_MIO_22_SLEW {slow} \
+   CONFIG.PCW_MIO_23_DIRECTION {in} \
+   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_23_PULLUP {enabled} \
+   CONFIG.PCW_MIO_23_SLEW {slow} \
+   CONFIG.PCW_MIO_24_DIRECTION {in} \
+   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_24_PULLUP {enabled} \
+   CONFIG.PCW_MIO_24_SLEW {slow} \
+   CONFIG.PCW_MIO_25_DIRECTION {in} \
+   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_25_PULLUP {enabled} \
+   CONFIG.PCW_MIO_25_SLEW {slow} \
+   CONFIG.PCW_MIO_26_DIRECTION {in} \
+   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_26_PULLUP {enabled} \
+   CONFIG.PCW_MIO_26_SLEW {slow} \
+   CONFIG.PCW_MIO_27_DIRECTION {in} \
+   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_27_PULLUP {enabled} \
+   CONFIG.PCW_MIO_27_SLEW {slow} \
+   CONFIG.PCW_MIO_28_DIRECTION {inout} \
+   CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_28_PULLUP {enabled} \
+   CONFIG.PCW_MIO_28_SLEW {slow} \
+   CONFIG.PCW_MIO_29_DIRECTION {in} \
+   CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_29_PULLUP {enabled} \
+   CONFIG.PCW_MIO_29_SLEW {slow} \
+   CONFIG.PCW_MIO_2_DIRECTION {inout} \
+   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_2_PULLUP {disabled} \
+   CONFIG.PCW_MIO_2_SLEW {slow} \
+   CONFIG.PCW_MIO_30_DIRECTION {out} \
+   CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_30_PULLUP {enabled} \
+   CONFIG.PCW_MIO_30_SLEW {slow} \
+   CONFIG.PCW_MIO_31_DIRECTION {in} \
+   CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_31_PULLUP {enabled} \
+   CONFIG.PCW_MIO_31_SLEW {slow} \
+   CONFIG.PCW_MIO_32_DIRECTION {inout} \
+   CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_32_PULLUP {enabled} \
+   CONFIG.PCW_MIO_32_SLEW {slow} \
+   CONFIG.PCW_MIO_33_DIRECTION {inout} \
+   CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_33_PULLUP {enabled} \
+   CONFIG.PCW_MIO_33_SLEW {slow} \
+   CONFIG.PCW_MIO_34_DIRECTION {inout} \
+   CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_34_PULLUP {enabled} \
+   CONFIG.PCW_MIO_34_SLEW {slow} \
+   CONFIG.PCW_MIO_35_DIRECTION {inout} \
+   CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_35_PULLUP {enabled} \
+   CONFIG.PCW_MIO_35_SLEW {slow} \
+   CONFIG.PCW_MIO_36_DIRECTION {in} \
+   CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_36_PULLUP {enabled} \
+   CONFIG.PCW_MIO_36_SLEW {slow} \
+   CONFIG.PCW_MIO_37_DIRECTION {inout} \
+   CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_37_PULLUP {enabled} \
+   CONFIG.PCW_MIO_37_SLEW {slow} \
+   CONFIG.PCW_MIO_38_DIRECTION {inout} \
+   CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_38_PULLUP {enabled} \
+   CONFIG.PCW_MIO_38_SLEW {slow} \
+   CONFIG.PCW_MIO_39_DIRECTION {inout} \
+   CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_39_PULLUP {enabled} \
+   CONFIG.PCW_MIO_39_SLEW {slow} \
+   CONFIG.PCW_MIO_3_DIRECTION {inout} \
+   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_3_PULLUP {disabled} \
+   CONFIG.PCW_MIO_3_SLEW {slow} \
+   CONFIG.PCW_MIO_40_DIRECTION {inout} \
+   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_40_PULLUP {enabled} \
+   CONFIG.PCW_MIO_40_SLEW {slow} \
+   CONFIG.PCW_MIO_41_DIRECTION {inout} \
+   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_41_PULLUP {enabled} \
+   CONFIG.PCW_MIO_41_SLEW {slow} \
+   CONFIG.PCW_MIO_42_DIRECTION {inout} \
+   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_42_PULLUP {enabled} \
+   CONFIG.PCW_MIO_42_SLEW {slow} \
+   CONFIG.PCW_MIO_43_DIRECTION {inout} \
+   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_43_PULLUP {enabled} \
+   CONFIG.PCW_MIO_43_SLEW {slow} \
+   CONFIG.PCW_MIO_44_DIRECTION {inout} \
+   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_44_PULLUP {enabled} \
+   CONFIG.PCW_MIO_44_SLEW {slow} \
+   CONFIG.PCW_MIO_45_DIRECTION {inout} \
+   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_45_PULLUP {enabled} \
+   CONFIG.PCW_MIO_45_SLEW {slow} \
+   CONFIG.PCW_MIO_46_DIRECTION {out} \
+   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_46_PULLUP {enabled} \
+   CONFIG.PCW_MIO_46_SLEW {slow} \
+   CONFIG.PCW_MIO_47_DIRECTION {in} \
+   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_47_PULLUP {enabled} \
+   CONFIG.PCW_MIO_47_SLEW {slow} \
+   CONFIG.PCW_MIO_48_DIRECTION {inout} \
+   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_48_PULLUP {enabled} \
+   CONFIG.PCW_MIO_48_SLEW {slow} \
+   CONFIG.PCW_MIO_49_DIRECTION {inout} \
+   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_49_PULLUP {enabled} \
+   CONFIG.PCW_MIO_49_SLEW {slow} \
+   CONFIG.PCW_MIO_4_DIRECTION {inout} \
+   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_4_PULLUP {disabled} \
+   CONFIG.PCW_MIO_4_SLEW {slow} \
+   CONFIG.PCW_MIO_50_DIRECTION {inout} \
+   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_50_PULLUP {enabled} \
+   CONFIG.PCW_MIO_50_SLEW {slow} \
+   CONFIG.PCW_MIO_51_DIRECTION {inout} \
+   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_51_PULLUP {enabled} \
+   CONFIG.PCW_MIO_51_SLEW {slow} \
+   CONFIG.PCW_MIO_52_DIRECTION {out} \
+   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_52_PULLUP {enabled} \
+   CONFIG.PCW_MIO_52_SLEW {slow} \
+   CONFIG.PCW_MIO_53_DIRECTION {inout} \
+   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_53_PULLUP {enabled} \
+   CONFIG.PCW_MIO_53_SLEW {slow} \
+   CONFIG.PCW_MIO_5_DIRECTION {inout} \
+   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_5_PULLUP {disabled} \
+   CONFIG.PCW_MIO_5_SLEW {slow} \
+   CONFIG.PCW_MIO_6_DIRECTION {out} \
+   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_6_PULLUP {disabled} \
+   CONFIG.PCW_MIO_6_SLEW {slow} \
+   CONFIG.PCW_MIO_7_DIRECTION {out} \
+   CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_7_PULLUP {disabled} \
+   CONFIG.PCW_MIO_7_SLEW {slow} \
+   CONFIG.PCW_MIO_8_DIRECTION {out} \
+   CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_8_PULLUP {disabled} \
+   CONFIG.PCW_MIO_8_SLEW {slow} \
+   CONFIG.PCW_MIO_9_DIRECTION {out} \
+   CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_9_PULLUP {enabled} \
+   CONFIG.PCW_MIO_9_SLEW {slow} \
+   CONFIG.PCW_MIO_PRIMITIVE {54} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \
+   CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_NAND_CYCLES_T_AR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_REA {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_WC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_WP {1} \
+   CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+   CONFIG.PCW_NAND_GRP_D8_IO {<Select>} \
+   CONFIG.PCW_NAND_NAND_IO {<Select>} \
+   CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_CS1_WE_TIME {0} \
+   CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_A25_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS0_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS1_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_IO {<Select>} \
+   CONFIG.PCW_NOR_NOR_IO {<Select>} \
+   CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
+   CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
+   CONFIG.PCW_P2F_CAN0_INTR {0} \
+   CONFIG.PCW_P2F_CAN1_INTR {0} \
+   CONFIG.PCW_P2F_CTI_INTR {0} \
+   CONFIG.PCW_P2F_DMAC0_INTR {0} \
+   CONFIG.PCW_P2F_DMAC1_INTR {0} \
+   CONFIG.PCW_P2F_DMAC2_INTR {0} \
+   CONFIG.PCW_P2F_DMAC3_INTR {0} \
+   CONFIG.PCW_P2F_DMAC4_INTR {0} \
+   CONFIG.PCW_P2F_DMAC5_INTR {0} \
+   CONFIG.PCW_P2F_DMAC6_INTR {0} \
+   CONFIG.PCW_P2F_DMAC7_INTR {0} \
+   CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
+   CONFIG.PCW_P2F_ENET0_INTR {0} \
+   CONFIG.PCW_P2F_ENET1_INTR {0} \
+   CONFIG.PCW_P2F_GPIO_INTR {0} \
+   CONFIG.PCW_P2F_I2C0_INTR {0} \
+   CONFIG.PCW_P2F_I2C1_INTR {0} \
+   CONFIG.PCW_P2F_QSPI_INTR {0} \
+   CONFIG.PCW_P2F_SDIO0_INTR {0} \
+   CONFIG.PCW_P2F_SDIO1_INTR {0} \
+   CONFIG.PCW_P2F_SMC_INTR {0} \
+   CONFIG.PCW_P2F_SPI0_INTR {0} \
+   CONFIG.PCW_P2F_SPI1_INTR {0} \
+   CONFIG.PCW_P2F_UART0_INTR {0} \
+   CONFIG.PCW_P2F_UART1_INTR {0} \
+   CONFIG.PCW_P2F_USB0_INTR {0} \
+   CONFIG.PCW_P2F_USB1_INTR {0} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
+   CONFIG.PCW_PACKAGE_NAME {clg400} \
+   CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
+   CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
+   CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
+   CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
+   CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_IO1_IO {<Select>} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+   CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
+   CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+   CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+   CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
+   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_POW_IO {<Select>} \
+   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_WP_IO {<Select>} \
+   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+   CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_CD_IO {<Select>} \
+   CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_POW_IO {<Select>} \
+   CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_WP_IO {<Select>} \
+   CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SD1_SD1_IO {<Select>} \
+   CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
+   CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
+   CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
+   CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
+   CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
+   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+   CONFIG.PCW_SMC_CYCLE_T0 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T1 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T2 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T3 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T4 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T5 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T6 {NA} \
+   CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
+   CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS0_IO {<Select>} \
+   CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS2_IO {<Select>} \
+   CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
+   CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI0_SPI0_IO {<Select>} \
+   CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
+   CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS0_IO {<Select>} \
+   CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS2_IO {<Select>} \
+   CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
+   CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI1_SPI1_IO {<Select>} \
+   CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+   CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
+   CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
+   CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
+   CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
+   CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_16BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_2BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_32BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_4BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_8BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
+   CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
+   CONFIG.PCW_TRACE_TRACE_IO {<Select>} \
+   CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
+   CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TTC0_TTC0_IO {<Select>} \
+   CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
+   CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TTC1_TTC1_IO {<Select>} \
+   CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
+   CONFIG.PCW_UART0_BAUD_RATE {115200} \
+   CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART0_GRP_FULL_IO {<Select>} \
+   CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
+   CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
+   CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
+   CONFIG.PCW_UART1_BAUD_RATE {115200} \
+   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART1_GRP_FULL_IO {<Select>} \
+   CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
+   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_UART1_UART1_IO {<Select>} \
+   CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \
+   CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
+   CONFIG.PCW_UIPARAM_DDR_AL {0} \
+   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+   CONFIG.PCW_UIPARAM_DDR_BL {8} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \
+   CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+   CONFIG.PCW_UIPARAM_DDR_CL {7} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
+   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+   CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+   CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
+   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \
+   CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
+   CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
+   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
+   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+   CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+   CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
+   CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
+   CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
+   CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB0_RESET_ENABLE {1} \
+   CONFIG.PCW_USB0_RESET_IO {MIO 46} \
+   CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+   CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
+   CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
+   CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB1_RESET_ENABLE {0} \
+   CONFIG.PCW_USB1_RESET_IO {<Select>} \
+   CONFIG.PCW_USB1_USB1_IO {<Select>} \
+   CONFIG.PCW_USB_RESET_ENABLE {1} \
+   CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
+   CONFIG.PCW_USE_AXI_NONSECURE {0} \
+   CONFIG.PCW_USE_CORESIGHT {0} \
+   CONFIG.PCW_USE_CROSS_TRIGGER {0} \
+   CONFIG.PCW_USE_CR_FABRIC {1} \
+   CONFIG.PCW_USE_DDR_BYPASS {0} \
+   CONFIG.PCW_USE_DEBUG {0} \
+   CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
+   CONFIG.PCW_USE_DMA0 {0} \
+   CONFIG.PCW_USE_DMA1 {0} \
+   CONFIG.PCW_USE_DMA2 {0} \
+   CONFIG.PCW_USE_DMA3 {0} \
+   CONFIG.PCW_USE_EXPANDED_IOP {0} \
+   CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
+   CONFIG.PCW_USE_HIGH_OCM {0} \
+   CONFIG.PCW_USE_M_AXI_GP0 {1} \
+   CONFIG.PCW_USE_M_AXI_GP1 {0} \
+   CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
+   CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_S_AXI_ACP {0} \
+   CONFIG.PCW_USE_S_AXI_GP0 {0} \
+   CONFIG.PCW_USE_S_AXI_GP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {0} \
+   CONFIG.PCW_USE_S_AXI_HP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP2 {0} \
+   CONFIG.PCW_USE_S_AXI_HP3 {0} \
+   CONFIG.PCW_USE_TRACE {0} \
+   CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
+   CONFIG.PCW_VALUE_SILVERSION {3} \
+   CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_WDT_WDT_IO {<Select>} \
+ ] $processing_system7_0
+
+  # Create instance: ps7_0_axi_periph, and set properties
+  set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps7_0_axi_periph
+
+  # Create instance: pynqrouter_0, and set properties
+  set pynqrouter_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:pynqrouter:1.0 pynqrouter_0 ]
+
+  # Create instance: rst_ps7_0_100M, and set properties
+  set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ]
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins pynqrouter_0/s_axi_AXI4LS]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+
+  # Create port connections
+  connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports LD] [get_bd_pins axi_gpio_0/gpio_io_o]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pynqrouter_0/ap_clk] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk]
+  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
+  connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn]
+  connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pynqrouter_0/ap_rst_n] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
+  create_bd_addr_seg -range 0x00040000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pynqrouter_0/s_axi_AXI4LS/Reg] SEG_pynqrouter_0_Reg
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls_2018/router_02_boardstr/etc/ap_fixed_sim.h

+/*
+ * Copyright 2012 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AESL_GCC_AP_FIXED_H__
+#define __AESL_GCC_AP_FIXED_H__
+
+#ifndef __cplusplus
+    #error C++ is required to include this header file
+#endif /* #ifndef __cplusplus */
+
+
+#include <math.h>
+#ifndef __AESL_APDT_IN_SCFLOW__
+    #include "etc/ap_int_sim.h"
+#else
+    #include "../etc/ap_private.h"
+#endif /* #ifndef __AESL_APDT_IN_SCFLOW__ */
+
+#define FLOAT_MAN 23
+#define FLOAT_EXP 8
+#define DOUBLE_MAN 52
+#define DOUBLE_EXP 11
+// #define DOUBLE_MAN_MASK (~0ULL >> (64-DOUBLE_MAN-2))
+#define DOUBLE_MAN_MASK 0x3fffffffffffffULL
+#define BIAS(e) ((1ULL<<(e-1))-1)
+#define FLOAT_BIAS BIAS(FLOAT_EXP)
+#define DOUBLE_BIAS BIAS(DOUBLE_EXP)
+
+/// Forward declaration.
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> struct ap_fixed_base;
+
+///Proxy class, which allows bit selection  to be used as both rvalue(for reading) and
+//lvalue(for writing)
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+struct af_bit_ref {
+#ifdef _MSC_VER
+    #pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+    ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& d_bv;
+    int d_index;
+public:
+    INLINE af_bit_ref(const af_bit_ref<_AP_W, _AP_I, _AP_S,
+                                        _AP_Q, _AP_O, _AP_N>& ref):
+           d_bv(ref.d_bv), d_index(ref.d_index) {}
+
+    INLINE af_bit_ref(ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>* bv, int index=0):
+    d_bv(*bv),d_index(index) {}
+
+    INLINE operator bool() const {
+        return d_bv.V[d_index];
+    }
+
+    INLINE af_bit_ref& operator=(unsigned long long val) {
+        if (val)
+            d_bv.V.set(d_index);
+        else
+            d_bv.V.clear(d_index);
+        return *this;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE af_bit_ref& operator =(const ap_private<_AP_W2,_AP_S2>& val) {
+        return operator=(val!=0);
+    }
+
+    INLINE af_bit_ref& operator =(const af_bit_ref<_AP_W, _AP_I, _AP_S,
+                                        _AP_Q, _AP_O, _AP_N>& val) {
+        return operator=((unsigned long long)(bool)val);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE af_bit_ref operator=(const af_bit_ref<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& val) {
+        return operator=((unsigned long long)(bool)val);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE af_bit_ref& operator = ( const ap_bit_ref<_AP_W2, _AP_S2> &val) {
+        return operator =((unsigned long long) (bool) val);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE af_bit_ref& operator = ( const ap_range_ref<_AP_W2,_AP_S2>& val) {
+        return operator =((const ap_private<_AP_W2, false>) val);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE af_bit_ref& operator= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((const ap_private<_AP_W2, false>)(val));
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE af_bit_ref& operator= (const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) {
+        return operator=((const ap_private<_AP_W2 + _AP_W3, false>)(val));
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<1, af_bit_ref, _AP_W2, ap_private<_AP_W2, _AP_S2> >
+    operator, (ap_private<_AP_W2, _AP_S2>& op) {
+        return ap_concat_ref<1, af_bit_ref, _AP_W2,
+               ap_private<_AP_W2, _AP_S2> >(*this, op);
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<1, af_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >
+    operator, (const ap_bit_ref<_AP_W2, _AP_S2> &op) {
+        return ap_concat_ref<1, af_bit_ref, 1,
+               ap_bit_ref<_AP_W2, _AP_S2> >(*this,
+               const_cast<ap_bit_ref<_AP_W2, _AP_S2>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<1, af_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+    operator, (const ap_range_ref<_AP_W2, _AP_S2> &op) {
+        return ap_concat_ref<1, af_bit_ref, _AP_W2,
+               ap_range_ref<_AP_W2, _AP_S2> >(*this,
+               const_cast<ap_range_ref<_AP_W2, _AP_S2>& >(op));
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_concat_ref<1, af_bit_ref, _AP_W2 + _AP_W3,
+                        ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+    operator, (const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &op) {
+        return ap_concat_ref<1, af_bit_ref, _AP_W2 + _AP_W3,
+                 ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this,
+                 const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_concat_ref<1, af_bit_ref, _AP_W2,
+             af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &op) {
+       return ap_concat_ref<1, af_bit_ref,  _AP_W2,
+             af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+             _AP_N2> >(*this, const_cast<af_range_ref<_AP_W2, _AP_I2,
+             _AP_S2, _AP_Q2, _AP_O2,_AP_N2>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_concat_ref<1, af_bit_ref, 1,
+             af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &op) {
+       return ap_concat_ref<1, af_bit_ref, 1,
+             af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+             const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+              _AP_O2, _AP_N2>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator == (const af_bit_ref<_AP_W2, _AP_I2,
+                             _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+        return get() == op.get();
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator != (const af_bit_ref<_AP_W2, _AP_I2,
+                             _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+        return get() != op.get();
+    }
+
+    INLINE bool operator ~ () const {
+        bool bit = (d_bv.V)[d_index];
+        return bit ? false : true;
+    }
+
+    INLINE int length() const {
+        return 1;
+    }
+
+    INLINE bool get() {
+        return d_bv.V[d_index];
+    }
+
+    INLINE bool get() const {
+        return d_bv.V[d_index];
+    }
+
+    INLINE std::string to_string() const {
+        return d_bv.V[d_index] ? "1" : "0";
+    }
+};
+
+///Range(slice)  reference
+//------------------------------------------------------------
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+struct af_range_ref {
+#ifdef _MSC_VER
+    #pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &d_bv;
+    int l_index;
+    int h_index;
+
+public:
+    INLINE af_range_ref(const af_range_ref<_AP_W, _AP_I, _AP_S,
+                                        _AP_Q, _AP_O, _AP_N>& ref):
+           d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {}
+
+    INLINE af_range_ref(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>* bv, int h, int l):
+        d_bv(*bv),l_index(l),h_index(h) {
+        //if (h < l)
+          // fprintf(stderr,
+           //"Warning! The bits selected will be returned in reverse order\n");
+    }
+
+    INLINE operator ap_private<_AP_W, false> () const {
+        if (h_index >= l_index) {
+          ap_private<_AP_W, false> val(d_bv.V);
+          ap_private<_AP_W,false> mask(-1);
+          mask>>=_AP_W-(h_index-l_index+1);
+          val>>=l_index;
+          return val&=mask;
+        } else {
+          ap_private<_AP_W, false> val = 0;
+          for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+            if ((d_bv.V)[j]) val.set(i);
+          return val;
+        }
+    }
+
+    INLINE operator unsigned long long() const {
+        return get().to_uint64();
+    }
+
+    template<int _AP_W2,bool _AP_S2>
+    INLINE af_range_ref& operator =(const ap_private<_AP_W2,_AP_S2>& val) {
+      ap_private<_AP_W, false> vval= ap_private<_AP_W, false>(val);
+        if (l_index > h_index) {
+            for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+                    vval[i]? d_bv.V.set(j):d_bv.V.clear(j);
+        } else {
+          ap_private<_AP_W,false> mask(-1);
+            if (l_index>0) {
+                mask<<=l_index;
+                vval<<=l_index;
+            }
+            if (h_index<_AP_W-1) {
+              ap_private<_AP_W,false> mask2(-1);
+              mask2>>=_AP_W-h_index-1;
+              mask&=mask2;
+              vval&=mask2;
+            }
+            mask.flip();
+            d_bv.V &= mask;
+            d_bv.V |= vval;
+        }
+        return *this;
+    }
+
+    INLINE af_range_ref& operator = (unsigned long long val) {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template<int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+    INLINE af_range_ref& operator =
+        (const ap_concat_ref <_AP_W3, _AP_T3, _AP_W4, _AP_T4>& val) {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref& operator =(const ap_bit_ref<_AP_W3, _AP_S3>& val) {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref& operator =(const ap_range_ref<_AP_W3,_AP_S3>& val) {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator =(tmpVal);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE af_range_ref& operator= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+        const ap_private<_AP_W2, false> tmp= val.get();
+        return operator = (tmp);
+    }
+
+    INLINE af_range_ref& operator= (const af_range_ref<_AP_W, _AP_I, _AP_S,
+                                        _AP_Q, _AP_O, _AP_N>& val) {
+        const ap_private<_AP_W, false> tmp= val.get();
+        return operator = (tmp);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE af_range_ref& operator= (const ap_fixed_base<_AP_W2,
+                          _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=(val.to_ap_private());
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator == (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs==rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator != (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs!=rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator > (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator >= (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>=rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator < (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator <= (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<=rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator == (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs==rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator != (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs!=rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator > (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator >= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>=rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator < (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator <= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<=rhs;
+    }
+
+    template<int _AP_W2>
+    INLINE void set(const ap_private<_AP_W2,false>& val) {
+        ap_private<_AP_W,_AP_S> vval=val;
+        if (l_index>h_index) {
+            for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+                    vval[i]? d_bv.V.set(j):d_bv.V.clear(j);
+        } else {
+          ap_private<_AP_W,_AP_S> mask(-1);
+            if (l_index>0) {
+                ap_private<_AP_W,false> mask1(-1);
+                mask1>>=_AP_W-l_index;
+                mask1.flip();
+                mask=mask1;
+                //vval&=mask1;
+                vval<<=l_index;
+            }
+            if (h_index<_AP_W-1) {
+                ap_private<_AP_W,false> mask2(-1);
+                mask2<<=h_index+1;
+                mask2.flip();
+                mask&=mask2;
+                vval&=mask2;
+            }
+            mask.flip();
+            d_bv&=mask;
+            d_bv|=vval;
+        }
+
+    }
+
+    INLINE ap_private<_AP_W,false> get() const {
+        if (h_index<l_index) {
+          ap_private<_AP_W, false> val(0);
+          for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+            if ((d_bv.V)[j]) val.set(i);
+          return val;
+        } else {
+          ap_private<_AP_W, false> val = ap_private<_AP_W,false>(d_bv.V);
+          val>>= l_index;
+          if (h_index<_AP_W-1)
+            {
+              ap_private<_AP_W,false> mask(-1);
+              mask>>=_AP_W-(h_index-l_index+1);
+              val&=mask;
+            }
+          return val;
+        }
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2, ap_private<_AP_W2, _AP_S2> >
+    operator, (ap_private<_AP_W2, _AP_S2>& op) {
+        return ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+               ap_private<_AP_W2, _AP_S2> >(*this, op);
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >
+    operator, (const ap_bit_ref<_AP_W2, _AP_S2> &op) {
+        return ap_concat_ref<_AP_W, af_range_ref, 1,
+               ap_bit_ref<_AP_W2, _AP_S2> >(*this,
+               const_cast<ap_bit_ref<_AP_W2, _AP_S2>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+    operator, (const ap_range_ref<_AP_W2, _AP_S2> &op) {
+        return ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+               ap_range_ref<_AP_W2, _AP_S2> >(*this,
+               const_cast<ap_range_ref<_AP_W2, _AP_S2>& >(op));
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2 + _AP_W3,
+                        ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+    operator, (const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &op) {
+        return ap_concat_ref<_AP_W, af_range_ref, _AP_W2 + _AP_W3,
+                 ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this,
+                 const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3,
+                  _AP_T3>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+             af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &op) {
+       return ap_concat_ref<_AP_W, af_range_ref,  _AP_W2,
+             af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+             const_cast<af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+             _AP_N2>& > (op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, 1,
+             af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &op) {
+       return ap_concat_ref<_AP_W, af_range_ref, 1,
+             af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+             const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+             _AP_O2, _AP_N2>& >(op));
+    }
+
+    INLINE int length() const {
+        return h_index>=l_index?h_index-l_index+1:l_index-h_index+1;
+    }
+
+    INLINE int to_int() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_int();
+    }
+
+    INLINE unsigned int to_uint() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_uint();
+    }
+
+    INLINE long to_long() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_long();
+    }
+
+    INLINE unsigned long to_ulong() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_ulong();
+    }
+
+    INLINE ap_slong to_int64() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_int64();
+    }
+
+    INLINE ap_ulong to_uint64() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_uint64();
+    }
+
+    INLINE std::string to_string(uint8_t radix) const {
+        return get().to_string(radix);
+    }
+
+};
+
+//-----------------------------------------------------------------------------
+///ap_fixed_base: AutoPilot fixed point
+//-----------------------------------------------------------------------------
+template<int _AP_W, int _AP_I, bool _AP_S=true, ap_q_mode _AP_Q=AP_TRN,
+         ap_o_mode _AP_O=AP_WRAP, int _AP_N=0>
+struct ap_fixed_base {
+#ifdef _MSC_VER
+    #pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+public:
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> friend struct
+ap_fixed_base;
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> friend struct
+af_bit_ref;
+
+    INLINE void overflow_adjust(bool underflow, bool overflow,
+                                bool lD, bool sign) {
+        if (!overflow && !underflow) return;
+        switch (_AP_O) {
+            case AP_WRAP:
+                if (_AP_N == 0)
+                    return;
+                if (_AP_S) {
+                    //signed SC_WRAP
+                    //n_bits == 1;
+                    if (_AP_N > 1) {
+                        ap_private<_AP_W, _AP_S>  mask(-1);
+                        if (_AP_N >= _AP_W) mask = 0;
+                        else mask.lshr(_AP_N);
+                        if (sign)
+                            V &= mask;
+                        else
+                            V |= ~mask;
+                    }
+                    sign ? V.set(_AP_W - 1) : V.clear(_AP_W - 1);
+                } else {
+                    //unsigned SC_WRAP
+                    ap_private<_AP_W, _AP_S> mask(-1);
+                    if (_AP_N >= _AP_W) mask = 0;
+                    else mask.lshr(_AP_N);
+                    mask.flip();
+                    V |= mask;
+                }
+                break;
+            case AP_SAT_ZERO:
+                V.clear();
+                break;
+            case AP_WRAP_SM:
+                {
+                bool Ro = ap_private_ops::get<_AP_W, _AP_S, _AP_W -1>(V); // V[_AP_W -1];
+                if (_AP_N == 0) {
+                    if (lD != Ro) {
+                        V.flip();
+                        lD ? ap_private_ops::set<_AP_W, _AP_S, _AP_W - 1>(V) :
+                            ap_private_ops::clear<_AP_W, _AP_S, _AP_W - 1>(V);
+                    }
+                } else {
+                    if (_AP_N == 1 && sign != Ro) {
+                        V.flip();
+                    } else if (_AP_N > 1) {
+                        bool lNo = ap_private_ops::get<_AP_W, _AP_S, _AP_W - _AP_N> (V); // V[_AP_W - _AP_N];
+                        if (lNo == sign)
+                            V.flip();
+                        ap_private<_AP_W, false> mask(-1);
+                        if (_AP_N >= _AP_W) mask = 0;
+                        else mask.lshr(_AP_N);
+                        if (sign)
+                            V &= mask;
+                        else
+                            V |= mask.flip();
+                        sign ? ap_private_ops::set<_AP_W, _AP_S, _AP_W - 1>(V) : ap_private_ops::clear<_AP_W, _AP_S, _AP_W - 1>(V);
+                    }
+                }
+                }
+                break;
+            default:
+                if (_AP_S) {
+                    if (overflow) {
+                        V.set(); ap_private_ops::clear<_AP_W, _AP_S, _AP_W-1>(V);
+                    } else if (underflow) {
+                        V.clear();
+                        ap_private_ops::set<_AP_W, _AP_S, _AP_W-1>(V);
+                        if (_AP_O == AP_SAT_SYM)
+                            ap_private_ops::set<_AP_W, _AP_S, 0>(V);
+                    }
+                } else {
+                    if (overflow)
+                        V.set();
+                    else if (underflow)
+                        V.clear();
+                }
+        }
+    }
+
+    INLINE bool quantization_adjust(bool qb, bool r, bool s) {
+    	bool carry=ap_private_ops::get<_AP_W, _AP_S, _AP_W-1>(V);
+    	switch (_AP_Q) {
+    	    case AP_TRN:
+    		return false;
+    	    case AP_RND_ZERO:
+    		qb &= s || r;
+    		break;
+    	    case AP_RND_MIN_INF:
+    		qb &= r;
+    		break;
+    	    case AP_RND_INF:
+    		qb &= !s || r;
+    		break;
+    	    case AP_RND_CONV:
+    		qb &= ap_private_ops::get<_AP_W, _AP_S, 0>(V) || r;
+    		break;
+    	    case AP_TRN_ZERO:
+    		qb = s && ( qb || r );
+    		break;
+    	    default:;
+
+    	}
+    	if (qb) ++V;
+    	//only when old V[_AP_W-1]==1 && new V[_AP_W-1]==0
+    	return carry && !(ap_private_ops::get<_AP_W, _AP_S, _AP_W-1>(V)); //(!V[_AP_W-1]);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2>
+    struct RType {
+        enum {
+            _AP_F=_AP_W-_AP_I,
+            F2=_AP_W2-_AP_I2,
+            mult_w = _AP_W+_AP_W2,
+            mult_i = _AP_I+_AP_I2,
+            mult_s = _AP_S||_AP_S2,
+            plus_w = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+1+AP_MAX(_AP_F,F2),
+            plus_i = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+1,
+            plus_s = _AP_S||_AP_S2,
+            minus_w = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+1+AP_MAX(_AP_F,F2),
+            minus_i = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+1,
+            minus_s = true,
+#ifndef __SC_COMPATIBLE__
+            div_w = _AP_W + AP_MAX(_AP_W2 - _AP_I2, 0) + _AP_S2,
+#else
+            div_w = _AP_W + AP_MAX(_AP_W2 - _AP_I2, 0) + _AP_S2 + AP_MAX(_AP_I2, 0),
+#endif /* #ifndef __SC_COMPATIBLE__ */
+            div_i = _AP_I + (_AP_W2-_AP_I2) + _AP_S2,
+            div_s = _AP_S||_AP_S2,
+            logic_w = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+AP_MAX(_AP_F,F2),
+            logic_i = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2)),
+            logic_s = _AP_S||_AP_S2
+        };
+
+        typedef ap_fixed_base<mult_w, mult_i, mult_s> mult;
+        typedef ap_fixed_base<plus_w, plus_i, plus_s> plus;
+        typedef ap_fixed_base<minus_w, minus_i, minus_s> minus;
+        typedef ap_fixed_base<logic_w, logic_i, logic_s> logic;
+        typedef ap_fixed_base<div_w, div_i, div_s> div;
+        typedef ap_fixed_base<_AP_W, _AP_I, _AP_S> arg1;
+    };
+    INLINE void report() {
+#if 0
+        if (_AP_W > 1024 && _AP_W <= 4096) {
+            fprintf(stderr, "[W] W=%d is out of bound (1<=W<=1024):"
+                            " for synthesis, please define macro AP_INT_TYPE_EXT(N) to"
+                            " extend the valid range.\n", _AP_W);
+        } else
+#endif /* #if 0 */
+        if (_AP_W > MAX_MODE(AP_INT_MAX_W) * 1024) {
+            fprintf(stderr, "[E] ap_%sfixed<%d, ...>: Bitwidth exceeds the "
+                   "default max value %d. Please use macro "
+                   "AP_INT_MAX_W to set a larger max value.\n",
+                            _AP_S?"":"u", _AP_W,
+                            MAX_MODE(AP_INT_MAX_W) * 1024);
+            exit(1);
+        }
+    }
+
+    /// Constructors.
+    // -------------------------------------------------------------------------
+#if 0
+    #ifdef __SC_COMPATIBLE__
+    INLINE ap_fixed_base():V(uint32_t(_AP_W), uint64_t(0)) {}
+    #else
+    INLINE ap_fixed_base():V(uint32_t(_AP_W)) {}
+    #endif /* #ifdef __SC_COMPATIBLE__ */
+#else
+    INLINE ap_fixed_base():V(0) {}
+#endif /* #if 0 */
+    //  INLINE ap_fixed_base():V() {}
+    //  INLINE  explicit ap_fixed_base(const ap_private<_AP_W+_AP_I, _AP_S>& _V):V(_V) {}
+    INLINE ap_fixed_base(const ap_fixed_base& op):V(op.V) {}
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed_base(const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op):V(0) {
+	enum {N2=_AP_W2,_AP_F=_AP_W-_AP_I,F2=_AP_W2-_AP_I2,QUAN_INC=F2>_AP_F && !(_AP_Q==AP_TRN ||
+		(_AP_Q==AP_TRN_ZERO && !_AP_S2))};
+	if (!op) return;
+	bool carry=false;
+	//handle quantization
+	enum { sh_amt =(F2>_AP_F)?F2-_AP_F:_AP_F-F2};
+	const ap_private<_AP_W2, _AP_S2>& val = op.V;
+	bool neg_src=val.isNegative();
+	if (F2==_AP_F)
+	    V=val;
+
+	else if (F2>_AP_F) {
+	    if (sh_amt >= _AP_W2)
+		V = neg_src ? -1 : 0;
+	    else
+		V = _AP_S2?val.ashr(sh_amt):val.lshr(sh_amt);
+	    if (_AP_Q!=AP_TRN && !(_AP_Q==AP_TRN_ZERO && !_AP_S2)) {
+		bool qb = false;
+		if (F2-_AP_F>_AP_W2)
+		    qb = neg_src;
+		else
+		    qb = ap_private_ops::get<_AP_W2, _AP_S2, F2-_AP_F-1>(val);
+
+		bool r=false;
+		enum { pos3 = F2-_AP_F-2};
+		if (pos3>=_AP_W2-1)
+		    r=val!=0;
+		else if (pos3>=0)
+		r = (val<<(_AP_W2-1-pos3))!=0;
+		carry = quantization_adjust(qb,r,neg_src);
+	    }
+	} else { //no quantization
+	    if (sh_amt < _AP_W) {
+		V=val;
+		V <<= sh_amt;
+	    }
+	}
+	//hanle overflow/underflow
+	if ((_AP_O!=AP_WRAP || _AP_N != 0) &&
+		((!_AP_S && _AP_S2) || _AP_I-_AP_S <
+		 _AP_I2 - _AP_S2 + (QUAN_INC|| (_AP_S2 &&
+		     _AP_O==AP_SAT_SYM)))) {//saturation
+	    bool deleted_zeros = _AP_S2?true:!carry,
+		 deleted_ones = true;
+	    bool lD=(_AP_I2>_AP_I && _AP_W2-_AP_I2+_AP_I>=0) &&
+		ap_private_ops::get<_AP_W2, _AP_S2, _AP_W2-_AP_I2+_AP_I>(val);
+	    enum { pos1=F2-_AP_F+_AP_W, pos2=F2-_AP_F+_AP_W+1};
+	    if (pos1 < _AP_W2) {
+		bool Range1_all_ones= true;
+		bool Range1_all_zeros= true;
+		if (pos1 >= 0) {
+		    enum { __W = (_AP_W2-pos1) > 0 ? (_AP_W2-pos1) : 1 };
+		    const ap_private<__W, _AP_S2> Range1=ap_private<__W, _AP_S2>(val.lshr(pos1));
+		    Range1_all_ones=Range1.isAllOnesValue();
+		    Range1_all_zeros=Range1.isMinValue();
+		} else {
+		    Range1_all_ones=false;
+		    Range1_all_zeros=val.isMinValue();
+		}
+		bool Range2_all_ones=true;
+		if (pos2<_AP_W2 && pos2>=0) {
+		    enum { __W = (_AP_W2-pos2)>0 ? (_AP_W2-pos2) : 1};
+		    ap_private<__W, true> Range2=ap_private<__W, true>(val.lshr(pos2));
+		    Range2_all_ones=Range2.isAllOnesValue();
+		} else if (pos2<0)
+		    Range2_all_ones=false;
+
+		deleted_zeros=deleted_zeros && (carry?Range1_all_ones:Range1_all_zeros);
+		deleted_ones=carry?Range2_all_ones&&(F2-_AP_F+_AP_W<0||!lD)
+		    :Range1_all_ones;
+		neg_src= neg_src&&!(carry && Range1_all_ones);
+	    } else
+		neg_src = neg_src && V[_AP_W-1];
+
+	    bool neg_trg= V.isNegative();
+	    bool overflow=(neg_trg||!deleted_zeros) && !val.isNegative();
+	    bool underflow=(!neg_trg||!deleted_ones)&&neg_src;
+	    //printf("neg_src = %d, neg_trg = %d, deleted_zeros = %d,
+	    //         deleted_ones = %d, overflow = %d, underflow = %d\n",
+	    //         neg_src, neg_trg, deleted_zeros, deleted_ones,
+	    //         overflow, underflow);
+	    if (_AP_O==AP_SAT_SYM && _AP_S2 && _AP_S)
+		underflow |= neg_src && (_AP_W>1?V.isMinSignedValue():true);
+	    overflow_adjust(underflow, overflow, lD, neg_src);
+	}
+	report();
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed_base(const volatile ap_fixed_base<_AP_W2,_AP_I2,
+		_AP_S2,_AP_Q2,_AP_O2, _AP_N2> &op) : V(op.V) {
+	*this = const_cast<ap_fixed_base<_AP_W2,_AP_I2,
+	_AP_S2,_AP_Q2,_AP_O2, _AP_N2>&>(op);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed_base(const ap_private<_AP_W2,_AP_S2>& op) {
+	ap_fixed_base<_AP_W2,_AP_W2,_AP_S2> f_op;
+	f_op.V=op;
+	*this = f_op;
+    }
+
+    INLINE ap_fixed_base(bool b) {
+	*this=(ap_private<1,false>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(char b) {
+	*this=(ap_private<8,false>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(signed char b) {
+	*this=(ap_private<8,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned char b) {
+	*this=(ap_private<8,false>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(signed short b) {
+	*this=(ap_private<16,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned short b) {
+	*this=(ap_private<16,false>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(signed int b) {
+	*this=(ap_private<32,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned int b) {
+	*this=(ap_private<32,false>)b;
+	report();
+    }
+# if defined __x86_64__
+    INLINE ap_fixed_base(signed long b) {
+	*this=(ap_private<64,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned long  b) {
+	*this=(ap_private<64,false>)b;
+	report();
+    }
+# else
+    INLINE ap_fixed_base(signed long  b) {
+	*this=(ap_private<32,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned long  b) {
+	*this=(ap_private<32,false>)b;
+	report();
+    }
+# endif
+
+    INLINE ap_fixed_base(ap_slong b) {
+	*this=(ap_private<64,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(ap_ulong b) {
+	*this=(ap_private<64,false>)b;
+	report();
+    }
+
+#if 1
+    INLINE ap_fixed_base(const char* val):V(0) {
+         ap_private<_AP_W, _AP_S> Tmp(val);
+         V = Tmp;
+    }
+
+    INLINE  ap_fixed_base(const char* val, signed char rd): V(0) {
+         ap_private<_AP_W, _AP_S> Tmp(val, rd);
+         V = Tmp;
+    }
+
+#endif
+
+    INLINE ap_fixed_base(const std::string& val) {
+        ap_private<_AP_W, _AP_S> Tmp(val, 2);
+        V = Tmp;
+        report();
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed_base(const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+        *this = ((bool)op);
+        report();
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed_base(const ap_range_ref<_AP_W2, _AP_S2>& op) {
+	*this = ap_private<_AP_W2, _AP_S2>(op);
+	report();
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_fixed_base(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op) {
+	*this = ((const ap_private<_AP_W2 + _AP_W3, false>&)(op));
+	report();
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed_base(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+         *this = (bool(op));
+        report();
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed_base(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+        *this = (ap_private<_AP_W2, false>(op));
+        report();
+    }
+
+    //helper function
+    INLINE unsigned long long doubleToRawBits(double pf)const {
+        union {
+            unsigned long long __L;
+            double __D;
+        }LD;
+        LD.__D=pf;
+        return LD.__L;
+    }
+
+
+    INLINE double rawBitsToDouble(unsigned long long pi) const {
+        union {
+            unsigned long long __L;
+            double __D;
+        }LD;
+        LD.__L=pi;
+        return LD.__D;
+    }
+
+    INLINE float rawBitsToFloat(uint32_t pi) const {
+        union {
+            uint32_t __L;
+            float __D;
+        }LD;
+        LD.__L = pi;
+        return LD.__D;
+    }
+
+    INLINE ap_fixed_base(double d):V(0) {
+	if (!d) return;
+	const bool isneg=d<0;
+
+	const uint64_t ireg=doubleToRawBits(isneg?-d:d);
+	if ((ireg&0x7fffffffffffffffULL)!=0) {
+	    const int32_t exp=(((ireg)>>DOUBLE_MAN)&0x07ff)-DOUBLE_BIAS;
+	    ap_private<DOUBLE_MAN+2, true> man = ireg & DOUBLE_MAN_MASK;
+	    man.clear(DOUBLE_MAN+1);
+	    man.set(DOUBLE_MAN);
+	    if (isneg) {
+		man.flip();
+                man++;
+            }
+
+	    enum {_AP_S2=true,  _AP_W2=DOUBLE_MAN+2,_AP_F=_AP_W -_AP_I };
+	    const int _AP_I2=exp+2;
+            const int F2=_AP_W2-_AP_I2;
+	    const bool QUAN_INC=F2>_AP_F && !(_AP_Q==AP_TRN || (_AP_Q==AP_TRN_ZERO &&
+		    !_AP_S2));
+	    bool carry=false;
+	    //handle quantization
+	    const unsigned sh_amt=abs(F2-_AP_F); // sh_amt = F2>_AP_F ? F2 -_AP_F : _AP_F-F2;
+	    if (F2==_AP_F )
+		V=man;
+	    else if (F2>_AP_F) {
+		if (sh_amt >= DOUBLE_MAN+2)
+		    V=isneg?-1:0;
+		else
+		    V=(man>>sh_amt) | ((man & 1ULL<<(DOUBLE_MAN+1)) ? (DOUBLE_MAN_MASK>>(DOUBLE_MAN+2-sh_amt) <<(DOUBLE_MAN+2-sh_amt)):0);
+
+		if (_AP_Q!=AP_TRN && !(_AP_Q==AP_TRN_ZERO && !_AP_S2)) {
+		    const bool qb=((F2-_AP_F > DOUBLE_MAN+2) ? isneg : (man & (1ULL<<(F2-_AP_F-1))) != 0);
+		    const int pos3=F2-_AP_F-2;
+		    const bool r = (pos3>= 0) ? (man << AP_MAX(0, _AP_W2-pos3-1)& DOUBLE_MAN_MASK)!=0  : false;
+		    carry = quantization_adjust(qb,r,isneg);
+		}
+	    }
+	    else { //no quantization
+		//                V=man;
+		if (sh_amt < _AP_W) {
+		    V = man;
+		    V <<= sh_amt;
+		}
+	    }
+	    //handle overflow/underflow
+	    if ((_AP_O != AP_WRAP || _AP_N != 0) &&
+		    ((!_AP_S && _AP_S2) || _AP_I-_AP_S <
+		     _AP_I2-_AP_S2+(QUAN_INC|| (_AP_S2 &&
+			 _AP_O==AP_SAT_SYM)) )) {// saturation
+		bool deleted_zeros = _AP_S2?true:!carry,
+		     deleted_ones = true;
+		bool neg_src;
+		const bool lD=(_AP_I2>_AP_I) && (_AP_W2-_AP_I2+_AP_I>=0) && (man & (1ULL <<(DOUBLE_MAN+2-_AP_I2+_AP_I)));
+		int pos1=F2+_AP_W-_AP_F;
+		if (pos1 < _AP_W2) {
+		    int pos2=pos1+1;
+		    bool Range1_all_ones=true;
+		    bool Range1_all_zeros=true;
+		    if (pos1>=0) {
+			ap_private<_AP_W,_AP_S> Range1=
+			    ap_private<_AP_W,_AP_S>((man >> pos1) | ((1ULL<<(DOUBLE_MAN+1)&man) ? (DOUBLE_MAN_MASK >> (DOUBLE_MAN+2-pos1) <<(DOUBLE_MAN+2-pos1)):0));
+			Range1_all_ones = Range1.isAllOnesValue(); // Range1.isAllOnesValue();
+			Range1_all_zeros = Range1.isMinValue(); // Range1.isMinValue();
+		    } else {
+			Range1_all_ones=false;
+			Range1_all_zeros = man==0; // man.isMinValue();
+		    }
+		    bool Range2_all_ones=true;
+		    if (pos2<_AP_W2 && pos2>=0) {
+			ap_private<_AP_W, _AP_S> Range2=
+			    ap_private<_AP_W, _AP_S>((man >> pos2) | ((1ULL<<(DOUBLE_MAN+1)&man) ? (DOUBLE_MAN_MASK >> (DOUBLE_MAN+2-pos2) <<(DOUBLE_MAN+2-pos2)):0));
+			Range2_all_ones=Range2.isAllOnesValue(); // Range2.isAllOnesValue();
+		    } else if (pos2<0)
+			Range2_all_ones=false;
+		    deleted_zeros=deleted_zeros && (carry?Range1_all_ones:Range1_all_zeros);
+		    deleted_ones=carry?Range2_all_ones&&(F2-_AP_F+_AP_W<0||!lD) : Range1_all_ones;
+		    neg_src=isneg&&!(carry&Range1_all_ones);
+		} else
+		    neg_src = isneg &&  V[_AP_W -1];
+
+		const bool neg_trg=V.isNegative();
+		const bool overflow=(neg_trg||!deleted_zeros) && !isneg;
+		bool underflow=(!neg_trg||!deleted_ones)&&neg_src;
+		//printf("neg_src = %d, neg_trg = %d, deleted_zeros = %d,
+		//          deleted_ones = %d, overflow = %d, underflow = %d\n",
+		//          neg_src, neg_trg, deleted_zeros, deleted_ones,
+		//          overflow, underflow);
+		if (_AP_O==AP_SAT_SYM && _AP_S2 && _AP_S)
+		    underflow |= neg_src && (_AP_W>1?V.isMinSignedValue():true);
+		overflow_adjust(underflow,overflow,lD, neg_src);
+	    }
+	}
+	report();
+    }
+
+
+        ///assign operators
+    //-------------------------------------------------------------------------
+
+    INLINE volatile ap_fixed_base& operator=(const ap_fixed_base<_AP_W, _AP_I, _AP_S,
+                                    _AP_Q, _AP_O, _AP_N>& op) volatile {
+        V = op.V;
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator=(const ap_fixed_base<_AP_W, _AP_I, _AP_S,
+                                    _AP_Q, _AP_O, _AP_N>& op) {
+        V = op.V;
+        return *this;
+    }
+
+    INLINE volatile ap_fixed_base& operator=(const volatile ap_fixed_base<_AP_W, _AP_I, _AP_S,
+                                    _AP_Q, _AP_O, _AP_N>& op) volatile {
+        V = op.V;
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator=(const volatile ap_fixed_base<_AP_W, _AP_I, _AP_S,
+                                    _AP_Q, _AP_O, _AP_N>& op) {
+        V = op.V;
+        return *this;
+    }
+
+    // Set this ap_fixed_base with a bits string. That means the ssdm_int::V
+    // inside this ap_fixed_base is assigned by bv.
+    // Note the input parameter should be a fixed-point formatted bit string.
+    INLINE ap_fixed_base& setBits(unsigned long long bv) {
+        V=bv;
+        return *this;
+    }
+
+    // Return a ap_fixed_base object whose ssdm_int::V is assigned by bv.
+    // Note the input parameter should be a fixed-point formatted bit string.
+    static INLINE ap_fixed_base bitsToFixed(unsigned long long bv) {
+	ap_fixed_base Tmp=bv;
+	return Tmp;
+    }
+
+    // Explicit conversion functions to ap_private that captures
+    // all integer bits (bits are truncated)
+    INLINE ap_private<AP_MAX(_AP_I,1),_AP_S>
+    to_ap_private(bool Cnative = true) const {
+	ap_private<AP_MAX(_AP_I,1),_AP_S> ret = ap_private<AP_MAX(_AP_I,1),_AP_S> ((_AP_I >= 1) ? (_AP_S==true ? V.ashr(AP_MAX(0,_AP_W - _AP_I)) : V.lshr(AP_MAX(0,_AP_W - _AP_I))) : ap_private<_AP_W, _AP_S>(0));
+
+	if (Cnative) {
+	    bool r = false;
+	    if (_AP_I < _AP_W) {
+		if (_AP_I > 0) r = !(V.getLoBits(_AP_W - _AP_I).isMinValue());
+		else r = !(V.isMinValue());
+	    }
+	    if (r && V.isNegative()) { // if this is negative integer
+		++ret;//ap_private<AP_MAX(_AP_I,1),_AP_S>(1,_AP_S);
+	    }
+	} else {
+	    //Follow OSCI library, conversion from sc_fixed to sc_int
+	}
+	return ret;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE operator ap_private<_AP_W2,_AP_S2> () const {
+        return (ap_private<_AP_W2,_AP_S2>)to_ap_private();
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_N2>
+    INLINE operator ap_private<_AP_W2,_AP_S2,_AP_N2> () const {
+        return (ap_private<_AP_W2,_AP_S2,_AP_N2>)to_ap_private();
+    }
+
+    //Explict conversion function to C built-in integral type
+    INLINE int to_int() const {
+        return to_ap_private().to_int();
+    }
+
+    INLINE int to_uint() const {
+        return to_ap_private().to_uint();
+    }
+
+    INLINE ap_slong to_int64() const {
+        return to_ap_private().to_int64();
+    }
+
+    INLINE ap_ulong to_uint64() const {
+        return to_ap_private().to_uint64();
+    }
+
+    INLINE double to_double() const {
+        if (!V)
+	    return 0;
+	if (_AP_W>64 || (_AP_W - _AP_I) > 0) {
+	    bool isneg = _AP_S && V[_AP_W-1];
+	    uint64_t res = isneg ? 0x8000000000000000ULL : 0;
+	    ap_private<_AP_W, false>  tmp = V;
+	    if (isneg) tmp = -tmp;
+	    int i = _AP_W -1 - tmp.countLeadingZeros();
+	    int exp = _AP_I-(_AP_W-i);
+	    res|=((uint64_t)(exp+DOUBLE_BIAS))<<DOUBLE_MAN;
+	    if (i!=0) {
+		tmp.clear(i);
+		uint64_t man = ((i>DOUBLE_MAN)?tmp.lshr(i-DOUBLE_MAN):tmp).to_uint64() & DOUBLE_MAN_MASK;
+		res |= i<DOUBLE_MAN ? (man)<<(DOUBLE_MAN-i)& DOUBLE_MAN_MASK  : man;
+	    }
+	    double dp=rawBitsToDouble(res);
+	    return dp;
+	} else if (_AP_W - _AP_I > 0) {
+	    /* This specialization is disabled. It is giving wrong results in some cases.
+	       bool isneg=V.isNegative();
+	       double dp = V.get();
+	       dp /= (1<< (_AP_W - _AP_I));
+	       return dp;*/
+	} else
+	    return double(to_int64());
+    }
+
+    INLINE float to_float() const {
+	uint32_t res=0;
+	if (V==0)
+	    return 0;
+	bool isneg=V.isNegative();
+	ap_private<_AP_W, _AP_S> tmp=V;
+	if (isneg) tmp = -tmp;
+	if (_AP_W-_AP_I>0||_AP_W>64) {
+	    if (isneg)
+		res=0x80000000;
+	    int i=_AP_W-1;
+	    i-=tmp.countLeadingZeros();
+	    int exp=_AP_I-(_AP_W-i);
+	    res|=(exp+FLOAT_BIAS)<<FLOAT_MAN;
+
+	    ap_private<_AP_W, _AP_S> man = 0;
+	    if (i!=0) {
+		tmp.clear(i);
+		if (i>FLOAT_MAN)
+		    man=tmp.lshr(i-FLOAT_MAN);
+		else
+		    man=tmp;
+		res |= i < FLOAT_MAN?man.getZExtValue()<<(FLOAT_MAN-i):man.getZExtValue();
+	    }
+	} else {
+	    return float(to_int64());
+	}
+	float dp=rawBitsToFloat(res);
+	return dp;
+    }
+
+    INLINE operator double () const {
+	return to_double();
+    }
+#ifndef __SC_COMPATIBLE__
+    INLINE operator float () const {
+           return to_float();
+    }
+
+    INLINE operator char () const {
+        return (char) to_int();
+    }
+
+    INLINE operator unsigned char () const {
+        return (unsigned char) to_uint();
+    }
+
+    INLINE operator short () const {
+        return (short) to_int();
+    }
+
+    INLINE operator unsigned short () const {
+        return (unsigned short) to_uint();
+    }
+
+    INLINE operator int () const {
+        return to_int();
+    }
+
+    INLINE operator unsigned int () const {
+        return to_uint();
+    }
+#if 1
+#ifdef __x86_64__
+    INLINE operator long () const {
+        return (long)to_int64();
+    }
+
+    INLINE operator unsigned long () const {
+        return (unsigned long) to_uint64();
+    }
+#else
+    INLINE operator long () const {
+        return to_int64();
+    }
+
+    INLINE operator unsigned long () const {
+        return to_uint64();
+    }
+
+#endif
+#endif
+    INLINE operator unsigned long long () const {
+        return to_uint64();
+    }
+
+    INLINE operator long long () const {
+        return to_int64();
+    }
+#endif
+
+    INLINE std::string to_string(uint8_t radix=2, bool sign=false) const;
+
+    INLINE ap_slong bits_to_int64() const  {
+      ap_private<AP_MIN(_AP_W, 64), _AP_S> res(V);
+        return (ap_slong) res;
+    }
+
+    INLINE ap_ulong bits_to_uint64() const {
+      ap_private<AP_MIN(64,_AP_W), _AP_S> res(V);
+      return (ap_ulong) res;
+    }
+
+    INLINE int length() const {return _AP_W;}
+
+    // Count the number of zeros from the most significant bit
+    // to the first one bit. Note this is only for ap_fixed_base whose
+    // _AP_W <= 64, otherwise will incur assertion.
+    INLINE int countLeadingZeros() {
+        return V.countLeadingZeros();
+    }
+
+    ///Arithmetic:Binary
+    //-------------------------------------------------------------------------
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE typename RType<_AP_W2,_AP_I2,_AP_S2>::mult
+    operator * (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+	typename RType<_AP_W2,_AP_I2,_AP_S2>::mult r;
+	r.V = V * op2.V;
+	return r;
+    }
+
+    template<int _AP_W1, int _AP_I1, bool _AP_S1, int _AP_W2, int _AP_I2, bool _AP_S2>
+    static INLINE ap_fixed_base multiply(const ap_fixed_base<_AP_W1,_AP_I1,_AP_S1>& op1, const
+         ap_fixed_base<_AP_W2,_AP_I2,_AP_S2>& op2) {
+	ap_private<_AP_W+_AP_W2, _AP_S> OP1=op1.V;
+	ap_private<_AP_W2,_AP_S2> OP2=op2.V;
+	return OP1*OP2;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE typename RType<_AP_W2,_AP_I2,_AP_S2>::div
+    operator / (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+        enum {F2 = _AP_W2-_AP_I2, _W1=AP_MAX(_AP_W + AP_MAX(F2, 0), _AP_W2),
+              _W2=AP_MAX(_AP_W2,AP_MAX(_AP_W + AP_MAX(F2, 0), _AP_W2))};
+        ap_private<_W1, _AP_S> dividend = (ap_private<_W1, _AP_S>(V)) << ((_W1>_AP_W)?F2:0);
+        ap_private<_W1, _AP_S2> divisior = ap_private<_W2, _AP_S2>(op2.V);
+        ap_private<_W1, _AP_S> ret = ap_private<_W1,_AP_S> ((_AP_S||_AP_S2) ? dividend.sdiv(divisior): dividend.udiv(divisior));
+        typename RType<_AP_W2, _AP_I2, _AP_S2>::div r;
+        r.V = ret;
+        return r;
+    }
+#define OP_BIN_AF(Sym, Rty, Width, Sign, Fun)                                \
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+    INLINE typename RType<_AP_W2,_AP_I2,_AP_S2>::Rty  \
+    operator Sym (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const \
+    {                                                                        \
+	enum {_AP_F=_AP_W-_AP_I, F2=_AP_W2-_AP_I2};                                \
+	typename RType<_AP_W2,_AP_I2,_AP_S2>::Rty  r, lhs(*this), rhs(op2);        \
+	r.V = lhs.V.Fun(rhs.V);                                                \
+	return r;                                                                \
+    }                                                                        \
+    INLINE typename RType<_AP_W,_AP_I,_AP_S>::Rty                        \
+    operator Sym (const ap_fixed_base& op2) const                        \
+    {                                                                        \
+	typename RType<_AP_W,_AP_I,_AP_S>::Rty  r;                                \
+	r.V = V Sym op2.V;                                                        \
+	return r;                                                                \
+    }                                                                        \
+
+    OP_BIN_AF(+, plus, plus_w, plus_s, Add)
+    OP_BIN_AF(-, minus, minus_w, minus_s, Sub)
+
+#define OP_LOGIC_BIN_AF(Sym, Rty, Width, Sign)                                \
+        template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+        INLINE typename RType<_AP_W2,_AP_I2,_AP_S2>::Rty                \
+        operator Sym (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const \
+    {                                                                        \
+	typename RType<_AP_W2,_AP_I2,_AP_S2>::Rty r, lhs(*this), rhs(op2);  \
+	r.V=lhs.V Sym rhs.V;                                                \
+	return r;                                                                \
+    }                                                                        \
+    INLINE typename RType<_AP_W,_AP_I,_AP_S>::Rty                        \
+    operator Sym (const ap_fixed_base& op2) const                        \
+    {                                                                        \
+	typename RType<_AP_W,_AP_I,_AP_S>::Rty  r; \
+	r.V = V Sym op2.V;                                                        \
+	return r;                                                                \
+    }                                                                        \
+    INLINE typename RType<_AP_W,_AP_I,_AP_S>::Rty  operator Sym(int op2) const \
+    {                                                                        \
+	return V Sym (op2<<(_AP_W - _AP_I));                                \
+    }
+    OP_LOGIC_BIN_AF(&, logic, logic_w, logic_s)
+    OP_LOGIC_BIN_AF(|, logic, logic_w, logic_s)
+    OP_LOGIC_BIN_AF(^, logic, logic_w, logic_s)
+
+    ///Arithmic : assign
+    //-------------------------------------------------------------------------
+#define OP_ASSIGN_AF(Sym) \
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+    INLINE ap_fixed_base& operator Sym##= (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) \
+    { \
+        *this=operator Sym (op2) ; \
+        return *this; \
+    }
+
+    OP_ASSIGN_AF(+)
+    OP_ASSIGN_AF(-)
+    OP_ASSIGN_AF(&)
+    OP_ASSIGN_AF(|)
+    OP_ASSIGN_AF(^)
+    OP_ASSIGN_AF(*)
+    OP_ASSIGN_AF(/)
+
+    ///Prefix increment, decrement
+    //-------------------------------------------------------------------------
+    INLINE ap_fixed_base& operator ++() {
+        operator+=(ap_fixed_base<1,1,false>(1)); //SystemC's semantics
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator --() {
+        operator-=(ap_fixed_base<1,1,false>(1)); //SystemC's semantics
+        return *this;
+    }
+
+    //Postfix increment, decrement
+    //-------------------------------------------------------------------------
+    INLINE const ap_fixed_base operator ++(int) {
+        ap_fixed_base t(*this);
+        operator++();
+        return t;
+    }
+
+    INLINE const ap_fixed_base operator --(int) {
+        ap_fixed_base t = *this;
+        operator--();
+        return t;
+    }
+
+    ///Unary arithmetic
+    //-------------------------------------------------------------------------
+    INLINE ap_fixed_base operator +() {return *this;}
+
+    INLINE ap_fixed_base<_AP_W + 1, _AP_I + 1, true> operator -() const {
+        ap_fixed_base<_AP_W + 1, _AP_I + 1, true> Tmp(*this);
+        Tmp.V = - Tmp.V;
+        return Tmp;
+    }
+
+    INLINE ap_fixed_base<_AP_W,_AP_I,true,_AP_Q,_AP_O, _AP_N> getNeg() {
+        ap_fixed_base<_AP_W,_AP_I,true,_AP_Q,_AP_O, _AP_N> Tmp(*this);
+        Tmp.V=-Tmp.V;
+        return Tmp;
+    }
+
+    ///Not (!)
+    //-------------------------------------------------------------------------
+    INLINE bool operator !() const {
+	return !V;
+    }
+
+    ///Bitwise complement
+    //-------------------------------------------------------------------------
+    INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S>
+         operator ~() const {
+        ap_fixed_base<_AP_W, _AP_I, _AP_S> res(*this);
+        res.V.flip();
+        return res;
+    }
+
+    ///Shift
+    ///template argument as shift value
+    template<int _AP_SHIFT>
+    INLINE ap_fixed_base<_AP_W, _AP_I + _AP_SHIFT, _AP_S> lshift () const {
+        ap_fixed_base<_AP_W, _AP_I + _AP_SHIFT, _AP_S> r;
+        r.V = V;
+        return r;
+    }
+
+    template<int _AP_SHIFT>
+    INLINE ap_fixed_base<_AP_W, _AP_I - _AP_SHIFT, _AP_S> rshift () const {
+        ap_fixed_base<_AP_W, _AP_I - _AP_SHIFT, _AP_S> r;
+        r.V = V;
+        return r;
+    }
+
+    //Because the return type is the type of the the first operand, shift assign
+    //operators do not carry out any quantization or overflow
+    //While systemc, shift assigns for sc_fixed/sc_ufixed will result in
+    //quantization or overflow (depending on the mode of the first operand)
+    //-------------------------------------------------------------------------
+    INLINE ap_fixed_base operator << (int sh) const {
+        ap_fixed_base r;
+        bool isNeg=(sh&0x80000000) != 0;
+        sh=isNeg?-sh:sh;
+        bool shiftoverflow = sh >= _AP_W;
+        bool NegSrc = V.isNegative();
+        if (isNeg) {
+            if (shiftoverflow)
+                NegSrc?r.V.set():r.V.clear();
+            else
+                r.V=_AP_S?V.ashr(sh):V.lshr(sh);
+        } else {
+            if (shiftoverflow)
+                r.V.clear();
+            else
+                r.V=V<<sh;
+        }
+#ifdef __SC_COMPATIBLE__
+        if (sh == 0) return r;
+        if (isNeg == true && _AP_Q != AP_TRN) {
+           bool qb = false;
+           if (sh <= _AP_W) qb = V[sh - 1];
+           bool rb  =  false;
+           if (sh > 1 && sh <= _AP_W)
+                rb = (V << (_AP_W - sh + 1 )) != 0;
+           else if (sh > _AP_W)
+                rb = V != 0;
+           r.quantization_adjust(qb, rb, NegSrc);
+        } else if (isNeg == false && _AP_O != AP_WRAP) {
+             bool allones, allzeros;
+             if (sh < _AP_W ) {
+                 ap_private<_AP_W, _AP_S > range1 = V.lshr(_AP_W - sh - 1);
+                 allones = range1.isAllOnesValue();
+                 allzeros = range1.isMinValue();
+             } else {
+                 allones = false;
+                 allzeros = V.isMinValue();
+             }
+             bool overflow = !allzeros && !NegSrc;
+             bool underflow = !allones && NegSrc;
+             if (_AP_O == AP_SAT_SYM && _AP_S)
+                  underflow |= NegSrc && (_AP_W > 1 ? r.V.isMinSignedValue():true);
+             bool lD = false;
+             if ( sh < _AP_W ) lD = V[_AP_W - sh - 1];
+             r.overflow_adjust(underflow, overflow, lD, NegSrc);
+        }
+#endif
+        return r;
+    }
+
+    template<int _AP_W2>
+    INLINE ap_fixed_base operator<<(const ap_private<_AP_W2,true>& op2) const {
+        int sh = op2.to_int();
+        return operator << (sh);
+    }
+
+    INLINE ap_fixed_base operator << (unsigned int sh ) const {
+        ap_fixed_base r;
+        bool shiftoverflow = sh >= _AP_W;
+        r.V = shiftoverflow ? ap_private<_AP_W, _AP_S >(0) : V << sh;
+        if (sh == 0) return r;
+#ifdef __SC_COMPATIBLE__
+        bool NegSrc = V.isNegative();
+        if (_AP_O != AP_WRAP) {
+             bool allones, allzeros;
+             if (sh < _AP_W ) {
+                 ap_private<_AP_W, _AP_S > range1 = V.lshr(_AP_W - sh -1);
+                 allones = range1.isAllOnesValue();
+                 allzeros = range1.isMinValue();
+             } else {
+                 allones = false;
+                 allzeros = V.isMinValue();
+             }
+             bool overflow = !allzeros && !NegSrc;
+             bool underflow = !allones && NegSrc;
+             if (_AP_O == AP_SAT_SYM && _AP_S)
+                  underflow |= NegSrc && (_AP_W > 1 ? r.V.isMinSignedValue():true);
+             bool lD = false;
+             if ( sh < _AP_W ) lD = V[_AP_W - sh - 1];
+             r.overflow_adjust(underflow, overflow, lD, NegSrc);
+        }
+#endif
+        return r;
+    }
+
+    template<int _AP_W2>
+    INLINE ap_fixed_base operator << (const ap_private<_AP_W2,false>& op2) const {
+        unsigned int sh = op2.to_uint();
+        return operator << (sh);
+    }
+
+    INLINE ap_fixed_base operator >> (int sh) const {
+        ap_fixed_base r;
+        bool isNeg=(sh&0x80000000) != 0;
+        bool NegSrc = V.isNegative();
+        sh=isNeg?-sh:sh;
+        bool shiftoverflow = sh >= _AP_W;
+        if (isNeg && !shiftoverflow) r.V=V<<sh;
+        else {
+            if (shiftoverflow)
+                NegSrc?r.V.set():r.V.clear();
+            else
+                r.V=_AP_S?V.ashr(sh):V.lshr(sh);
+        }
+#ifdef __SC_COMPATIBLE__
+        if (sh == 0) return r;
+        if (isNeg == false && _AP_Q != AP_TRN) {
+           bool qb = false;
+           if (sh <= _AP_W) qb = V[sh - 1];
+           bool rb  =  false;
+           if (sh > 1 && sh <= _AP_W)
+                rb = (V << (_AP_W - sh + 1 )) != 0;
+           else if (sh > _AP_W)
+                rb = V != 0;
+           r.quantization_adjust(qb, rb, NegSrc);
+        } else if (isNeg == true && _AP_O != AP_WRAP) {
+             bool allones, allzeros;
+             if (sh < _AP_W ) {
+                 ap_private<_AP_W, _AP_S > range1 = V.lshr(_AP_W - sh - 1);
+                 allones = range1.isAllOnesValue();
+                 allzeros = range1.isMinValue();
+             } else {
+                 allones = false;
+                 allzeros = V.isMinValue();
+             }
+             bool overflow = !allzeros && !NegSrc;
+             bool underflow = !allones && NegSrc;
+             if (_AP_O == AP_SAT_SYM && _AP_S)
+                  underflow |= NegSrc && (_AP_W > 1 ? r.V.isMinSignedValue():true);
+             bool lD = false;
+             if ( sh < _AP_W ) lD = V[_AP_W - sh - 1];
+             r.overflow_adjust(underflow, overflow, lD, NegSrc);
+        }
+#endif
+        return r;
+    }
+
+    template<int _AP_W2>
+    INLINE ap_fixed_base operator >> (const ap_private<_AP_W2,true>& op2) const {
+        int sh = op2.to_int();
+        return operator >> (sh);
+    }
+
+    INLINE ap_fixed_base operator >> (unsigned int sh) const {
+        ap_fixed_base r;
+        bool NegSrc = V.isNegative();
+        bool shiftoverflow = sh >= _AP_W;
+        if (shiftoverflow)
+            NegSrc?r.V.set():r.V.clear();
+        else
+            r.V=_AP_S?V.ashr(sh):V.lshr(sh);
+#ifdef __SC_COMPATIBLE__
+        if (sh == 0) return r;
+        if (_AP_Q != AP_TRN) {
+           bool qb = false;
+           if (sh <= _AP_W) qb = V[sh - 1];
+           bool rb  =  false;
+           if (sh > 1 && sh <= _AP_W)
+                rb = (V << (_AP_W - sh + 1 )) != 0;
+           else if (sh > _AP_W)
+                rb = V != 0;
+           r.quantization_adjust(qb, rb, NegSrc);
+        }
+#endif
+        return r;
+    }
+
+    template<int _AP_W2>
+    INLINE ap_fixed_base operator >> (const ap_private<_AP_W2,false>& op2) const {
+        unsigned int sh = op2.to_uint();
+        return operator >> (sh);
+    }
+
+    ///shift assign
+    //-------------------------------------------------------------------------
+#define OP_AP_SHIFT_AP_ASSIGN_AF(Sym) \
+    template<int _AP_W2, bool _AP_S2> \
+    INLINE ap_fixed_base& operator Sym##=(const ap_private<_AP_W2,_AP_S2>& op2) \
+    { \
+        *this=operator Sym (op2); \
+        return *this; \
+    }
+
+    OP_AP_SHIFT_AP_ASSIGN_AF(<<)
+    OP_AP_SHIFT_AP_ASSIGN_AF(>>)
+
+    ///Support shift(ap_fixed_base)
+#define OP_AP_SHIFT_AF(Sym) \
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+    INLINE ap_fixed_base operator Sym (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const \
+    { \
+        return operator Sym (op2.to_ap_private()); \
+    } \
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+    INLINE ap_fixed_base& operator Sym##= (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) \
+    { \
+        *this=operator Sym (op2); \
+        return *this; \
+    }
+
+    OP_AP_SHIFT_AF(<<)
+    OP_AP_SHIFT_AF(>>)
+
+    INLINE ap_fixed_base& operator >>= (unsigned int sh) {
+        *this = operator >> (sh);
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator <<= (unsigned int sh) {
+        *this = operator << (sh);
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator >>= (int sh) {
+        *this = operator >> (sh);
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator <<= (int sh) {
+        *this = operator << (sh);
+        return *this;
+    }
+
+    ///Comparisons
+    //-------------------------------------------------------------------------
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator == (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+	enum {_AP_F=_AP_W-_AP_I,F2=_AP_W2-_AP_I2, shAmt1 = AP_MAX(F2-_AP_F, 0), shAmt2 = AP_MAX(_AP_F-F2,0), _AP_W3 = (_AP_F==F2) ? AP_MAX(_AP_W,_AP_W2) : AP_MAX(_AP_W+shAmt1, _AP_W2+shAmt2)};
+	ap_private<_AP_W3, _AP_S > OP1= ap_private<_AP_W3, _AP_S >(V)<<shAmt1;
+	ap_private<_AP_W3,_AP_S2 > OP2=ap_private<_AP_W3,_AP_S2 >(op2.V)<<shAmt2;
+	return OP1 == OP2;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator != (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+        return !(*this==op2);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator > (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+	enum {_AP_F=_AP_W-_AP_I,F2=_AP_W2-_AP_I2, shAmt1 = AP_MAX(F2-_AP_F, 0), shAmt2 = AP_MAX(_AP_F-F2,0), _AP_W3 = (_AP_F==F2) ? AP_MAX(_AP_W,_AP_W2) : AP_MAX(_AP_W+shAmt1, _AP_W2+shAmt2)};
+	ap_private<_AP_W3, _AP_S > OP1= ap_private<_AP_W3, _AP_S >(V)<<shAmt1;
+	ap_private<_AP_W3,_AP_S2 > OP2=ap_private<_AP_W3,_AP_S2 >(op2.V)<<shAmt2;
+	if (_AP_S||_AP_S2)
+	    return OP1.sgt(OP2);
+	else
+	    return OP1.ugt(OP2);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator <= (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+        return !(*this>op2);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator < (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+	enum {_AP_F=_AP_W-_AP_I,F2=_AP_W2-_AP_I2, shAmt1 = AP_MAX(F2-_AP_F, 0), shAmt2 = AP_MAX(_AP_F-F2,0), _AP_W3 = (_AP_F==F2) ? AP_MAX(_AP_W,_AP_W2) : AP_MAX(_AP_W+shAmt1, _AP_W2+shAmt2)};
+	ap_private<_AP_W3, _AP_S > OP1= ap_private<_AP_W3, _AP_S >(V)<<shAmt1;
+	ap_private<_AP_W3,_AP_S2 > OP2=ap_private<_AP_W3,_AP_S2 >(op2.V)<<shAmt2;
+	if (_AP_S||_AP_S2)
+	    return OP1.slt(OP2);
+	else
+	    return OP1.ult(OP2);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator >= (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+        return !(*this<op2);
+    }
+
+#define DOUBLE_CMP_AF(Sym) \
+    INLINE bool operator Sym (double d) const { \
+        return to_double() Sym d; \
+    }
+
+    DOUBLE_CMP_AF(==)
+    DOUBLE_CMP_AF(!=)
+    DOUBLE_CMP_AF(>)
+    DOUBLE_CMP_AF(>=)
+    DOUBLE_CMP_AF(<)
+    DOUBLE_CMP_AF(<=)
+
+    // Bit and Slice Select
+    INLINE af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> operator [] (unsigned int index) {
+        assert(index<_AP_W&&"Attemping to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index);
+    }
+
+    INLINE af_bit_ref<_AP_W, _AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> bit(unsigned int index) {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> bit (const ap_private<_AP_W2,_AP_S2>& index) {
+        assert(index >= 0 && "Attempting to read bit with negative index");
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index.to_int());
+    }
+
+    INLINE bool bit (unsigned int index) const {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return V[index];
+    }
+
+    INLINE bool operator [] (unsigned int index) const {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return V[index];
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool bit (const ap_private<_AP_W2, _AP_S2>& index) const {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return V[index.to_uint()];
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator [] (const ap_private<_AP_W2, _AP_S2>& index) const {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return V[index.to_uint()];
+    }
+
+    INLINE af_bit_ref<_AP_W, _AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> get_bit(int index) {
+        assert(index < _AP_I && "Attempting to read bit beyond MSB");
+        assert(index >= _AP_I - _AP_W&& "Attempting to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index + _AP_W - _AP_I);
+    }
+
+    template<int _AP_W2>
+    INLINE af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> get_bit (const ap_private<_AP_W2, true>& index) {
+        assert(index >= _AP_I - _AP_W && "Attempting to read bit with negative index");
+        assert(index < _AP_I && "Attempting to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index.to_int() + _AP_W - _AP_I);
+    }
+
+    INLINE bool get_bit (int index) const {
+        assert(index >= _AP_I - _AP_W && "Attempting to read bit with negative index");
+        assert(index < _AP_I && "Attempting to read bit beyond MSB");
+        return V[index + _AP_W - _AP_I];
+    }
+
+    template<int _AP_W2>
+    INLINE bool get_bit (const ap_private<_AP_W2, true>& index) const {
+        assert(index >= _AP_I - _AP_W && "Attempting to read bit with negative index");
+        assert(index < _AP_I && "Attempting to read bit beyond MSB");
+        return V[index.to_int() + _AP_W - _AP_I];
+    }
+
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    range(int Hi, int Lo) {
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    operator () (int Hi, int Lo) {
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    range(int Hi, int Lo) const {
+        assert((Hi < _AP_W) && (Lo < _AP_W) &&"Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(const_cast<ap_fixed_base*>(this), Hi, Lo);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    operator () (int Hi, int Lo) const {
+        return this->range(Hi, Lo);
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    range(const ap_private<_AP_W2, _AP_S2> &HiIdx,
+          const ap_private<_AP_W3, _AP_S3> &LoIdx) {
+        int Hi = HiIdx.to_int();
+        int Lo = LoIdx.to_int();
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    operator () (const ap_private<_AP_W2, _AP_S2> &HiIdx,
+                 const ap_private<_AP_W3, _AP_S3> &LoIdx) {
+        int Hi = HiIdx.to_int();
+        int Lo = LoIdx.to_int();
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    range(const ap_private<_AP_W2, _AP_S2> &HiIdx,
+          const ap_private<_AP_W3, _AP_S3> &LoIdx) const {
+        int Hi = HiIdx.to_int();
+        int Lo = LoIdx.to_int();
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(const_cast<
+               ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>*>(this),
+               Hi, Lo);
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    operator () (const ap_private<_AP_W2, _AP_S2> &HiIdx,
+                 const ap_private<_AP_W3, _AP_S3> &LoIdx) const {
+        int Hi = HiIdx.to_int();
+        int Lo = LoIdx.to_int();
+        return this->range(Hi, Lo);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    range() {
+        return this->range(_AP_W - 1, 0);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    range() const {
+        return this->range(_AP_W - 1, 0);
+    }
+
+    INLINE bool is_zero () const {
+        return V.isMinValue();
+    }
+
+    INLINE bool is_neg () const {
+        if (V.isNegative())
+            return true;
+        return false;
+    }
+
+    INLINE int wl () const {
+        return _AP_W;
+    }
+
+    INLINE int iwl () const {
+        return _AP_I;
+    }
+
+    INLINE ap_q_mode q_mode () const {
+        return _AP_Q;
+    }
+
+    INLINE ap_o_mode o_mode () const {
+        return _AP_O;
+    }
+
+    INLINE int n_bits () const {
+        return 0;
+    }
+
+  //private:
+public:
+    ap_private<_AP_W, _AP_S> V;
+};
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+std::string ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>::to_string(
+                                            uint8_t radix, bool sign) const {
+    std::string str;
+    str.clear();
+    char step;
+    std::string prefix;
+    switch (radix) {
+        case 2  : prefix = "0b"; step = 1; break;
+        case 8  : prefix = "0o"; step = 3; break;
+        case 16 : prefix = "0x"; step = 4; break;
+        default : break;
+    }
+    if (_AP_W <= _AP_I)
+        str = this->to_ap_private().to_string(radix,
+               radix == 10 ? _AP_S : sign);
+    else {
+        if (radix == 10) {
+            bool isNeg = _AP_S && V.isNegative();
+            if (_AP_I > 0) {
+                ap_private<AP_MAX(_AP_I, 1),  _AP_S> int_part(0);
+                int_part = this->to_ap_private();
+                str += int_part.to_string(radix, false);
+            } else {
+                if (isNeg) str += '-';
+            }
+            ap_fixed_base<_AP_W, _AP_I, _AP_S> tmp(*this);
+            if (isNeg && _AP_I <= 0) tmp = -tmp;
+            ap_fixed_base<_AP_W - AP_MIN(_AP_I, 0), 0, false> frac_part = tmp;
+            if (frac_part == 0) return str;
+            str += ".";
+            while (frac_part != 0) {
+               char digit = (frac_part * radix).to_ap_private();
+               str += static_cast<char>(digit + '0');
+               frac_part *= radix;
+            }
+        } else {
+            if (_AP_I > 0) {
+                for (signed i = _AP_W - _AP_I; i < _AP_W; i += step) {
+
+                     char digit = (char)(this->range(AP_MIN(i + step - 1, _AP_W - 1), i));
+                     str = (digit < 10 ? static_cast<char>(digit + '0') :
+                                        static_cast<char>(digit - 10 + 'a')) + str;
+                }
+            }
+            str += '.';
+            ap_fixed_base<AP_MAX(_AP_W - _AP_I, 1), 0, _AP_S> tmp(*this);
+            for (signed i = _AP_W - _AP_I - 1; i >= 0; i -= step) {
+                char digit = (char)(tmp.range(i, AP_MAX(0, i - step + 1)));
+                str += digit < 10 ? static_cast<char>(digit + '0') :
+                       static_cast<char>(digit - 10 + 'a');
+            }
+        }
+    }
+    str = prefix + str;
+    return str;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void b_not(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {
+    ret.V = op.V;
+    ret.V.flip();
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void b_and(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+    ret.V =  op1.V & op2.V;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void b_or(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+    ret.V =  op1.V | op2.V;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void b_xor(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+    ret.V =  op1.V ^ op2.V;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+          ap_o_mode _AP_O2, int _AP_N2>
+INLINE void neg(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    ap_fixed_base<_AP_W2+!_AP_S2, _AP_I2+!_AP_S2, true, _AP_Q2, _AP_O2, _AP_N2> Tmp;
+    Tmp.V = - op.V;
+    ret = Tmp;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N>
+INLINE void neg(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {
+    ret.V = -op.V;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+         ap_o_mode _AP_O2, int _AP_N2>
+INLINE void lshift(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op,
+            int i) {
+    ap_fixed_base<_AP_W2 - _AP_I2 + AP_MAX(_AP_I, _AP_I2), AP_MAX(_AP_I, _AP_I2), _AP_S2, _AP_Q2, _AP_O2, _AP_N2> Tmp;
+    Tmp = op;
+    Tmp.V <<= i;
+    ret = Tmp;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N>
+INLINE void lshift(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,
+            int i) {
+    ret.V = op.V << i;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+         ap_o_mode _AP_O2, int _AP_N2>
+INLINE void rshift(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op,
+            int i) {
+    ap_fixed_base<_AP_I2 + AP_MAX(_AP_W - _AP_I, _AP_W2 - _AP_I2), _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> Tmp;
+    Tmp = op;
+    Tmp.V = _AP_S2 ? Tmp.V.ashr(i): Tmp.V.lshr(i);
+    ret = Tmp;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N>
+INLINE void rshift(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,
+            int i) {
+    ret.V = _AP_S ? op.V.ashr(i): op.V.lshr(i);
+}
+
+#define AF_CTOR_SPEC_BASE(_AP_W,_AP_S,C_TYPE) \
+  template<> INLINE ap_fixed_base<_AP_W,_AP_W,_AP_S,AP_TRN,AP_WRAP>::ap_fixed_base(C_TYPE i_op):V(i_op) \
+    { \
+  }
+
+#define AF_CTOR_SPEC(__W,C_TYPE) \
+    AF_CTOR_SPEC_BASE(__W,true,C_TYPE) \
+    AF_CTOR_SPEC_BASE(__W,false,C_TYPE)
+
+AF_CTOR_SPEC(1,bool)
+AF_CTOR_SPEC(8, signed char)
+AF_CTOR_SPEC(8, unsigned char)
+AF_CTOR_SPEC(16, signed short)
+AF_CTOR_SPEC(16, unsigned short)
+AF_CTOR_SPEC(32, signed int)
+AF_CTOR_SPEC(32, unsigned int)
+AF_CTOR_SPEC(64, ap_slong)
+AF_CTOR_SPEC(64, ap_ulong)
+
+///Output streaming
+//-----------------------------------------------------------------------------
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE std::ostream&
+operator <<(std::ostream& os, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& x) {
+     os << x.to_double();
+     return os;
+}
+
+///Input streaming
+//-----------------------------------------------------------------------------
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE std::istream&
+operator >> (std::istream& os, ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& x) {
+     double d;
+     os >> d;
+     x = ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(x);
+     return os;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void print(const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& x) {
+    ap_private<_AP_W,_AP_S> data=x.V;
+    if (_AP_I>0) {
+        const ap_private<_AP_I,_AP_S> p1=data>>(_AP_W-_AP_I);
+        print(p1);
+
+    } else
+        printf("0");
+    printf(".");
+    if (_AP_I<_AP_W) {
+        const ap_private<_AP_W-_AP_I,false> p2=data;
+        print(p2,false);
+    }
+}
+
+///Operators mixing Integers with ap_fixed_base
+//-----------------------------------------------------------------------------
+#if 1
+#define AF_BIN_OP_WITH_INT_SF(BIN_OP,C_TYPE,_AP_W2,_AP_S2,RTYPE)        \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+  {                                                                        \
+    return op.operator BIN_OP(ap_private<_AP_W2,_AP_S2>(i_op));        \
+  }
+#define AF_BIN_OP_WITH_INT(BIN_OP, C_TYPE, _AP_W2,_AP_S2,RTYPE)                \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+  {                                                                        \
+    return op.operator BIN_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  }                                                                        \
+                                                                        \
+  template<int _AP_W, int _AP_I, bool _AP_S,ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (C_TYPE i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) \
+  {                                                                        \
+    return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator BIN_OP (op); \
+  }
+
+#else
+#define AF_BIN_OP_WITH_INT_SF(BIN_OP,C_TYPE,_AP_W2,_AP_S2,RTYPE)        \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+  {                                                                        \
+    return op BIN_OP (i_op);                                        \
+  }
+#define AF_BIN_OP_WITH_INT(BIN_OP, C_TYPE, _AP_W2,_AP_S2,RTYPE)                \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+  {                                                                        \
+    return op.V BIN_OP (i_op<<(_AP_W-_AP_I));                        \
+  }                                                                        \
+                                                                          \
+                                                                          \
+  template<int _AP_W, int _AP_I, bool _AP_S,ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (C_TYPE i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) \
+  {                                                                        \
+    return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator BIN_OP (op);                        \
+  }
+
+#endif
+#if 1
+#define AF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2,_AP_S2)                \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+    INLINE bool operator REL_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+    { \
+        return op.operator REL_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+    } \
+    \
+    \
+    template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+    INLINE bool operator REL_OP (C_TYPE i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) \
+    { \
+        return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator REL_OP (op); \
+    }
+#else
+#define AF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2,_AP_S2) \
+    template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+    INLINE bool operator REL_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+    { \
+      return op.V.operator REL_OP (i_op<<(_AP_W-_AP_I));        \
+    } \
+    \
+    \
+    template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+    INLINE bool operator REL_OP (C_TYPE i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) \
+    { \
+      return (i_op<<(_AP_W-_AP_I)) REL_OP (op.V.VAL);        \
+    }
+#endif
+#if 1
+#define AF_ASSIGN_OP_WITH_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) { \
+    return op.operator ASSIGN_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  }
+#define AF_ASSIGN_OP_WITH_INT_SF(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) { \
+    return op.operator ASSIGN_OP (ap_private<_AP_W2,_AP_S2>(i_op)); \
+  }
+#else
+#define AF_ASSIGN_OP_WITH_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) { \
+    return op.V.operator ASSIGN_OP (i_op);                                \
+  }
+#define AF_ASSIGN_OP_WITH_INT_SF(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) { \
+    return op.V.operator ASSIGN_OP (i_op); \
+  }
+#endif
+
+#define AF_OPS_WITH_INT(C_TYPE, WI, SI) \
+  AF_BIN_OP_WITH_INT(+, C_TYPE, WI, SI, plus) \
+  AF_BIN_OP_WITH_INT(-, C_TYPE, WI, SI, minus) \
+  AF_BIN_OP_WITH_INT(*, C_TYPE, WI, SI, mult) \
+  AF_BIN_OP_WITH_INT(/, C_TYPE, WI, SI, div) \
+  AF_BIN_OP_WITH_INT_SF(>>, C_TYPE, WI, SI, arg1) \
+  AF_BIN_OP_WITH_INT_SF(<<, C_TYPE, WI, SI, arg1) \
+  AF_BIN_OP_WITH_INT(&, C_TYPE, WI, SI, logic) \
+  AF_BIN_OP_WITH_INT(|, C_TYPE, WI, SI, logic) \
+  AF_BIN_OP_WITH_INT(^, C_TYPE, WI, SI, logic) \
+  \
+  AF_REL_OP_WITH_INT(==, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(!=, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(>, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(>=, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(<, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(<=, C_TYPE, WI, SI) \
+  \
+  AF_ASSIGN_OP_WITH_INT(+=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(-=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(*=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(/=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT_SF(>>=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT_SF(<<=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(&=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(|=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(^=, C_TYPE, WI, SI)
+
+AF_OPS_WITH_INT(bool, 1, false)
+AF_OPS_WITH_INT(char, 8, true)
+AF_OPS_WITH_INT(signed char, 8, true)
+AF_OPS_WITH_INT(unsigned char, 8, false)
+AF_OPS_WITH_INT(short, 16, true)
+AF_OPS_WITH_INT(unsigned short, 16, false)
+AF_OPS_WITH_INT(int, 32, true)
+AF_OPS_WITH_INT(unsigned int, 32, false)
+# if defined __x86_64__
+AF_OPS_WITH_INT(long, 64, true)
+AF_OPS_WITH_INT(unsigned long, 64, false)
+# else
+AF_OPS_WITH_INT(long, 32, true)
+AF_OPS_WITH_INT(unsigned long, 32, false)
+# endif
+AF_OPS_WITH_INT(ap_slong, 64, true)
+AF_OPS_WITH_INT(ap_ulong, 64, false)
+
+#define AF_BIN_OP_WITH_AP_INT(BIN_OP, RTYPE) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>::template RType<_AP_W,_AP_I,_AP_S>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W2,_AP_S2>& i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) { \
+    return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator BIN_OP (op); \
+  } \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, const ap_private<_AP_W2,_AP_S2>& i_op) { \
+    return op.operator BIN_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  }
+
+#define AF_REL_OP_WITH_AP_INT(REL_OP) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, const ap_private<_AP_W2,_AP_S2>& i_op) { \
+    return op.operator REL_OP ( ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  } \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_private<_AP_W2,_AP_S2>& i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) { \
+    return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator REL_OP (op); \
+  }
+
+#define AF_ASSIGN_OP_WITH_AP_INT(ASSIGN_OP) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, const ap_private<_AP_W2,_AP_S2>& i_op) { \
+    return op.operator ASSIGN_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  } \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE ap_private<_AP_W2,_AP_S2>& operator ASSIGN_OP ( ap_private<_AP_W2,_AP_S2>& i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) { \
+    return i_op.operator ASSIGN_OP (op.to_ap_private()); \
+  }
+
+AF_BIN_OP_WITH_AP_INT(+, plus)
+AF_BIN_OP_WITH_AP_INT(-, minus)
+AF_BIN_OP_WITH_AP_INT(*, mult)
+AF_BIN_OP_WITH_AP_INT(/, div)
+AF_BIN_OP_WITH_AP_INT(&, logic)
+AF_BIN_OP_WITH_AP_INT(|, logic)
+AF_BIN_OP_WITH_AP_INT(^, logic)
+
+AF_REL_OP_WITH_AP_INT(==)
+AF_REL_OP_WITH_AP_INT(!=)
+AF_REL_OP_WITH_AP_INT(>)
+AF_REL_OP_WITH_AP_INT(>=)
+AF_REL_OP_WITH_AP_INT(<)
+AF_REL_OP_WITH_AP_INT(<=)
+
+AF_ASSIGN_OP_WITH_AP_INT(+=)
+AF_ASSIGN_OP_WITH_AP_INT(-=)
+AF_ASSIGN_OP_WITH_AP_INT(*=)
+AF_ASSIGN_OP_WITH_AP_INT(/=)
+AF_ASSIGN_OP_WITH_AP_INT(&=)
+AF_ASSIGN_OP_WITH_AP_INT(|=)
+AF_ASSIGN_OP_WITH_AP_INT(^=)
+
+#define AF_REF_REL_OP_MIX_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE bool operator REL_OP ( const af_range_ref<_AP_W,_AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op, C_TYPE op2) {  \
+    return (ap_private<_AP_W, false>(op)).operator REL_OP (ap_private<_AP_W2,_AP_S2>(op2));  \
+  }  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE bool operator REL_OP ( C_TYPE op2, const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op) {  \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator REL_OP (ap_private<_AP_W, false>(op));  \
+  } \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE bool operator REL_OP ( const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op, C_TYPE op2) {  \
+    return (bool(op)) REL_OP op2;  \
+  }  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE bool operator REL_OP ( C_TYPE op2, const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op) {  \
+    return op2 REL_OP (bool(op));  \
+  }
+
+#define AF_REF_REL_MIX_INT(C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(>, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(<, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(>=, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(<=, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(==, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(!=, C_TYPE, _AP_WI, _AP_SI)
+
+AF_REF_REL_MIX_INT(bool, 1, false)
+AF_REF_REL_MIX_INT(char, 8, true)
+AF_REF_REL_MIX_INT(signed char, 8, true)
+AF_REF_REL_MIX_INT(unsigned char, 8, false)
+AF_REF_REL_MIX_INT(short, 16, true)
+AF_REF_REL_MIX_INT(unsigned short, 16, false)
+AF_REF_REL_MIX_INT(int, 32, true)
+AF_REF_REL_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+AF_REF_REL_MIX_INT(long, 64, true)
+AF_REF_REL_MIX_INT(unsigned long, 64, false)
+# else
+AF_REF_REL_MIX_INT(long, 32, true)
+AF_REF_REL_MIX_INT(unsigned long, 32, false)
+# endif
+AF_REF_REL_MIX_INT(ap_slong, 64, true)
+AF_REF_REL_MIX_INT(ap_ulong, 64, false)
+
+#define AF_REF_REL_OP_AP_INT(REL_OP)  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const af_range_ref<_AP_W,_AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op, const ap_private<_AP_W2, _AP_S> &op2) {  \
+    return (ap_private<_AP_W, false>(op)).operator REL_OP (op2);  \
+  }  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP (const ap_private<_AP_W2, _AP_S2> &op2, const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op) {  \
+    return op2.operator REL_OP (ap_private<_AP_W, false>(op));  \
+  } \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op, const ap_private<_AP_W2, _AP_S2> &op2) {  \
+    return (ap_private<1, false>(op)).operator REL_OP (op2);  \
+  }  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_private<_AP_W2, _AP_S2> &op2, const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op) {  \
+    return op2.operator REL_OP (ap_private<1,false>(op));  \
+  }
+
+AF_REF_REL_OP_AP_INT(>)
+AF_REF_REL_OP_AP_INT(<)
+AF_REF_REL_OP_AP_INT(>=)
+AF_REF_REL_OP_AP_INT(<=)
+AF_REF_REL_OP_AP_INT(==)
+AF_REF_REL_OP_AP_INT(!=)
+
+// Relational Operators with double
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator == ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator == (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator != ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator != (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator > ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator < (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator >= ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator <= (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator < ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator > (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator <= ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator >= (op1);
+}
+
+#endif /* #ifndef __AESL_GCC_AP_FIXED_H__ */
\ No newline at end of file

hls_2018/router_02_boardstr/etc/ap_int_sim.h

+/*
+ * Copyright 2012 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AESL_GCC_AP_INT_H__
+#define __AESL_GCC_AP_INT_H__
+
+#ifndef __cplusplus
+#error C++ is required to include this header file
+#endif /* #ifndef __cplusplus */
+
+#undef _AP_DEBUG_
+#include <stdio.h>
+#include <iostream>
+
+// for safety
+#if (defined(_AP_N)|| defined(_AP_C))
+#error One or more of the following is defined: _AP_N, _AP_C. Definition conflicts with their usage as template parameters.
+#endif /* #if (defined(_AP_N)|| defined(_AP_C)) */
+
+// for safety
+#if (defined(_AP_W) || defined(_AP_I) || defined(_AP_S) || defined(_AP_Q) || defined(_AP_O) || defined(_AP_W2) || defined(_AP_I2) || defined(_AP_S2) || defined(_AP_Q2) || defined(_AP_O2))
+#error One or more of the following is defined: _AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2. Definition conflicts with their usage as template parameters.
+#endif /* #if (defined(_AP_W) || defined(_AP_I) || defined(_AP_S) || defined(_AP_Q) || defined(_AP_O) || defined(_AP_W2) || defined(_AP_I2) || defined(_AP_S2) || defined(_AP_Q2) || defined(_AP_O2)) */
+
+//for safety
+#if (defined(_AP_W3) || defined(_AP_S3) || defined(_AP_W4) || defined(_AP_S4))
+#error One or more of the following is defined: _AP_W3, _AP_S3, _AP_W4,_AP_S4. Definition conflicts with their usage as template parameters.
+#endif /* #if (defined(_AP_W3) || defined(_AP_S3) || defined(_AP_W4) || defined(_AP_S4)) */
+
+//for safety
+#if (defined(_AP_W1) || defined(_AP_S1) || defined(_AP_I1) || defined(_AP_T) || defined(_AP_T1) || defined(_AP_T2) || defined(_AP_T3) || defined(_AP_T4))
+#error One or more of the following is defined: _AP_W1, _AP_S1, _AP_I1, _AP_T,  _AP_T1, _AP_T2, _AP_T3, _AP_T4. Definition conflicts with their usage as template parameters.
+#endif /* #if (defined(_AP_W1) || defined(_AP_S1) || defined(_AP_I1) || defined(_AP_T) || defined(_AP_T1) || defined(_AP_T2) || defined(_AP_T3) || defined(_AP_T4)) */
+
+#define __AESL_APDT_IN_SCFLOW__
+#ifndef __AESL_APDT_IN_SCFLOW__
+    #include "etc/ap_private.h"
+#else
+    #include "../etc/ap_private.h"
+#endif /* #ifndef __AESL_APDT_IN_SCFLOW__ */
+
+#ifdef _AP_DEBUG_
+    #define AP_DEBUG(s) s
+#else
+    #define AP_DEBUG(s)
+#endif /* #ifdef _AP_DEBUG_ */
+
+#ifndef __SIMULATION__
+    #define __SIMULATION__
+#endif /* #ifndef __SIMULATION__ */
+
+#if !(defined SYSTEMC_H) && !(defined SYSTEMC_INCLUDED)
+    #ifndef SC_TRN
+        #define SC_TRN AP_TRN
+    #endif /* #ifndef SC_TRN */
+    #ifndef SC_RND
+        #define SC_RND AP_RND
+    #endif /* #ifndef SC_RND */
+    #ifndef SC_TRN_ZERO
+        #define SC_TRN_ZERO AP_TRN_ZERO
+    #endif /* #ifndef SC_TRN_ZERO */
+    #ifndef SC_RND_ZERO
+        #define SC_RND_ZERO AP_RND_ZERO
+    #endif /* #ifndef SC_RND_ZERO */
+    #ifndef SC_RND_INF
+        #define SC_RND_INF AP_RND_INF
+    #endif /* #ifndef SC_RND_INF */
+    #ifndef SC_RND_MIN_INF
+        #define SC_RND_MIN_INF AP_RND_MIN_INF
+    #endif /* #ifndef SC_RND_MIN_INF */
+    #ifndef SC_RND_CONV
+        #define SC_RND_CONV AP_RND_CONV
+    #endif /* #ifndef SC_RND_CONV */
+    #ifndef SC_WRAP
+        #define SC_WRAP AP_WRAP
+    #endif /* #ifndef SC_WRAP */
+    #ifndef SC_SAT
+        #define SC_SAT AP_SAT
+    #endif /* #ifndef SC_SAT */
+    #ifndef SC_SAT_ZERO
+        #define SC_SAT_ZERO AP_SAT_ZERO
+    #endif /* #ifndef SC_SAT_ZERO */
+    #ifndef SC_SAT_SYM
+        #define SC_SAT_SYM AP_SAT_SYM
+    #endif /* #ifndef SC_SAT_SYM */
+    #ifndef SC_WRAP_SM
+        #define SC_WRAP_SM AP_WRAP_SM
+    #endif /* #ifndef SC_WRAP_SM */
+    #ifndef SC_BIN
+        #define SC_BIN 	AP_BIN
+    #endif /* #ifndef SC_BIN */
+    #ifndef SC_OCT
+        #define SC_OCT  AP_OCT
+    #endif /* #ifndef SC_OCT */
+    #ifndef SC_DEC
+        #define SC_DEC AP_DEC
+    #endif /* #ifndef SC_DEC */
+    #ifndef SC_HEX
+        #define SC_HEX AP_HEX
+    #endif /* #ifndef SC_HEX */
+#endif /* #if !(defined SYSTEMC_H) && !(defined SYSTEMC_INCLUDED) */
+#ifndef AP_INT_MAX_W
+#define AP_INT_MAX_W 1024
+#endif
+#define BIT_WIDTH_UPPER_LIMIT (1 << 15)
+#if AP_INT_MAX_W > BIT_WIDTH_UPPER_LIMIT
+#error "Bitwidth exceeds 32768 (1 << 15), the maximum allowed value"
+#endif
+#define MAX_MODE(BITS) ((BITS + 1023) / 1024)
+
+///Forward declaration
+template<int _AP_W, bool _AP_S> struct ap_range_ref;
+template<int _AP_W, bool _AP_S> struct ap_bit_ref;
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N> struct ap_fixed_base;
+template<int _AP_W, int _AP_I, bool _AP_S,
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> struct af_range_ref;
+template<int _AP_W, int _AP_I, bool _AP_S,
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> struct af_bit_ref;
+template<int _AP_W> class ap_uint;
+
+enum {
+    AP_BIN = 2,
+    AP_OCT = 8,
+    AP_DEC = 10,
+    AP_HEX = 16
+};
+
+///Why to use reference?
+///Because we will operate the original object indirectly by operating the
+///result object directly after concating or part selecting
+
+///Proxy class which allows concatination to be used as rvalue(for reading) and
+//lvalue(for writing)
+
+/// Concatination reference.
+// ----------------------------------------------------------------
+template<int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2>
+struct ap_concat_ref {
+#ifdef _MSC_VER
+    #pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+    enum {_AP_WR=_AP_W1+_AP_W2,};
+    _AP_T1& mbv1;
+    _AP_T2& mbv2;
+
+    INLINE ap_concat_ref(const ap_concat_ref<_AP_W1, _AP_T1,
+          _AP_W2, _AP_T2>& ref):
+           mbv1(ref.mbv1), mbv2(ref.mbv2) {}
+
+    INLINE ap_concat_ref(_AP_T1& bv1, _AP_T2& bv2):mbv1(bv1),mbv2(bv2) {}
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref& operator = (const ap_private<_AP_W3,_AP_S3>& val) {
+        ap_private<_AP_W1+_AP_W2, false>  vval(val);
+        int W_ref1=mbv1.length();
+        int W_ref2=mbv2.length();
+        ap_private<_AP_W1,false> mask1(-1);
+        mask1>>=_AP_W1-W_ref1;
+        ap_private<_AP_W2,false> mask2(-1);
+        mask2>>=_AP_W2-W_ref2;
+        mbv1.set(ap_private<_AP_W1,false>((vval>>W_ref2)&mask1));
+        mbv2.set(ap_private<_AP_W2,false>(vval&mask2));
+        return *this;
+    }
+
+    INLINE ap_concat_ref& operator = (unsigned long long val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template<int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+    INLINE ap_concat_ref& operator =
+        (const ap_concat_ref <_AP_W3, _AP_T3, _AP_W4, _AP_T4>&  val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    INLINE ap_concat_ref& operator =
+        (const ap_concat_ref <_AP_W1, _AP_T1, _AP_W2, _AP_T2>&  val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref& operator =(const ap_bit_ref<_AP_W3, _AP_S3>& val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref& operator =(const ap_range_ref<_AP_W3,_AP_S3>& val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator =(tmpVal);
+    }
+
+    template<int _AP_W3, int _AP_I3, bool _AP_S3,
+             ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE ap_concat_ref& operator= (const af_range_ref<_AP_W3, _AP_I3, _AP_S3,
+                                    _AP_Q3, _AP_O3, _AP_N3>& val) {
+        return operator = ((const ap_private<_AP_W3, false>)(val));
+    }
+
+    template<int _AP_W3, int _AP_I3, bool _AP_S3,
+             ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE ap_concat_ref& operator= (const ap_fixed_base<_AP_W3, _AP_I3, _AP_S3,
+                                    _AP_Q3, _AP_O3, _AP_N3>& val) {
+        return operator = (val.to_ap_private());
+    }
+
+    template<int _AP_W3, int _AP_I3, bool _AP_S3,
+             ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE ap_concat_ref& operator= (const af_bit_ref<_AP_W3, _AP_I3, _AP_S3,
+                                    _AP_Q3, _AP_O3, _AP_N3>& val) {
+        return operator=((unsigned long long)(bool)(val));
+     }
+
+
+    INLINE operator ap_private<_AP_WR, false> () const {
+        return get();
+    }
+
+    INLINE operator unsigned long long () const {
+         return get().to_uint64();
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_range_ref<_AP_W3, _AP_S3> >
+        operator, (const ap_range_ref<_AP_W3, _AP_S3> &a2) {
+        return ap_concat_ref<_AP_WR, ap_concat_ref,
+                           _AP_W3, ap_range_ref<_AP_W3, _AP_S3> >(*this,
+                           const_cast<ap_range_ref<_AP_W3, _AP_S3> &>(a2));
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_private<_AP_W3, _AP_S3> >
+        operator, (ap_private<_AP_W3, _AP_S3> &a2) {
+          return ap_concat_ref<_AP_WR, ap_concat_ref,
+                               _AP_W3, ap_private<_AP_W3, _AP_S3> >(*this, a2);
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_private<_AP_W3, _AP_S3> >
+        operator, (const ap_private<_AP_W3, _AP_S3> &a2) {
+          return ap_concat_ref<_AP_WR, ap_concat_ref,
+                               _AP_W3, ap_private<_AP_W3, _AP_S3> >(*this,
+                               const_cast<ap_private<_AP_W3, _AP_S3>&>(a2));
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, 1, ap_bit_ref<_AP_W3, _AP_S3> >
+        operator, (const ap_bit_ref<_AP_W3, _AP_S3> &a2) {
+        return ap_concat_ref<_AP_WR, ap_concat_ref,
+                               1, ap_bit_ref<_AP_W3, _AP_S3> >(*this,
+                          const_cast<ap_bit_ref<_AP_W3, _AP_S3> &>(a2));
+    }
+
+    template<int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3+_AP_W4, ap_concat_ref<_AP_W3,_AP_T3,_AP_W4,_AP_T4> >
+        operator, (const ap_concat_ref<_AP_W3,_AP_T3,_AP_W4,_AP_T4> &a2)
+    {
+        return ap_concat_ref<_AP_WR, ap_concat_ref,
+                               _AP_W3+_AP_W4, ap_concat_ref<_AP_W3,_AP_T3,_AP_W4,
+                               _AP_T4> >(*this, const_cast<ap_concat_ref<_AP_W3,
+                               _AP_T3,_AP_W4, _AP_T4>& >(a2));
+    }
+
+    template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE
+    ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >
+    operator, (const af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3,
+               _AP_O3, _AP_N3> &a2) {
+        return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, af_range_ref<_AP_W3,
+                _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >(*this,
+                const_cast<af_range_ref<_AP_W3,_AP_I3, _AP_S3, _AP_Q3,
+                _AP_O3, _AP_N3>& >(a2));
+    }
+
+    template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE
+    ap_concat_ref<_AP_WR, ap_concat_ref, 1, af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >
+    operator, (const af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3,
+               _AP_O3, _AP_N3> &a2) {
+        return ap_concat_ref<_AP_WR, ap_concat_ref, 1, af_bit_ref<_AP_W3,
+                _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >(*this,
+                const_cast<af_bit_ref<_AP_W3,_AP_I3, _AP_S3,
+                _AP_Q3, _AP_O3, _AP_N3>& >(a2));
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_private<AP_MAX(_AP_WR,_AP_W3), _AP_S3>
+        operator & (const ap_private<_AP_W3,_AP_S3>& a2) {
+        return get() & a2;
+    }
+
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_private<AP_MAX(_AP_WR,_AP_W3), _AP_S3>
+        operator | (const ap_private<_AP_W3,_AP_S3>& a2) {
+        return get() | a2;
+    }
+
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_private<AP_MAX(_AP_WR,_AP_W3), _AP_S3>
+        operator ^ (const ap_private<_AP_W3,_AP_S3>& a2) {
+      return ap_private<AP_MAX(_AP_WR,_AP_W3), _AP_S3>(get() ^ a2);
+    }
+
+    INLINE const ap_private<_AP_WR, false> get() const
+    {
+      ap_private<_AP_W1+_AP_W2, false> tmpVal = ap_private<_AP_W1+_AP_W2, false> (mbv1.get());
+      ap_private<_AP_W1+_AP_W2, false> tmpVal2 = ap_private<_AP_W1+_AP_W2, false> (mbv2.get());
+        int W_ref2 = mbv2.length();
+        tmpVal <<= W_ref2;
+        tmpVal |= tmpVal2;
+        return tmpVal;
+    }
+
+    INLINE const ap_private<_AP_WR, false> get() {
+      ap_private<_AP_W1+_AP_W2, false> tmpVal = ap_private<_AP_W1+_AP_W2, false> ( mbv1.get());
+      ap_private<_AP_W1+_AP_W2, false> tmpVal2 = ap_private<_AP_W1+_AP_W2, false> (mbv2.get());
+        int W_ref2 = mbv2.length();
+        tmpVal <<= W_ref2;
+        tmpVal |= tmpVal2;
+        return tmpVal;
+    }
+
+    template <int _AP_W3>
+    INLINE void set(const ap_private<_AP_W3,false> & val) {
+        ap_private<_AP_W1+_AP_W2, false> vval(val);
+        int W_ref1=mbv1.length();
+        int W_ref2=mbv2.length();
+        ap_private<_AP_W1,false> mask1(-1);
+        mask1>>=_AP_W1-W_ref1;
+        ap_private<_AP_W2,false> mask2(-1);
+        mask2>>=_AP_W2-W_ref2;
+        mbv1.set(ap_private<_AP_W1,false>((vval>>W_ref2)&mask1));
+        mbv2.set(ap_private<_AP_W2,false>(vval&mask2));
+    }
+
+    INLINE int length() const {
+        return mbv1.length()+mbv2.length();
+    }
+
+    INLINE std::string to_string(uint8_t radix=2) const {
+        return get().to_string(radix);
+    }
+};
+
+///Proxy class, which allows part selection to be used as rvalue(for reading) and
+//lvalue(for writing)
+
+///Range(slice)  reference
+//------------------------------------------------------------
+template<int _AP_W, bool _AP_S>
+struct ap_range_ref {
+#ifdef _MSC_VER
+    #pragma warning( disable : 4521 4522 )
+#endif /* #ifdef _MSC_VER */
+    ap_private<_AP_W,_AP_S> &d_bv;
+    int l_index;
+    int h_index;
+
+public:
+    INLINE ap_range_ref(const ap_range_ref<_AP_W, _AP_S>& ref):
+         d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {}
+
+    INLINE ap_range_ref(ap_private<_AP_W,_AP_S>* bv, int h, int l):
+        d_bv(*bv),l_index(l),h_index(h) {
+        //if (h < l)
+	  //fprintf(stderr, "Warning! The bits selected will be returned in reverse order\n");
+    }
+
+    INLINE operator ap_private<_AP_W, false> () const {
+        ap_private<_AP_W, false> val(0);
+        if(h_index>=l_index) {
+	  if (_AP_W > 64) {
+            val=d_bv;
+            ap_private<_AP_W,false> mask(-1);
+            mask>>=_AP_W-(h_index-l_index+1);
+            val>>=l_index;
+            val&=mask;
+	  } else {
+	    const static uint64_t mask = (~0ULL>> (64>_AP_W ? (64-_AP_W):0));
+	    val = (d_bv >> l_index) & (mask >>(_AP_W-(h_index-l_index+1)));
+	  }
+        } else {
+            for(int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+                    if((d_bv)[j]) val.set(i);
+        }
+        return val;
+    }
+
+    INLINE operator unsigned long long () const {
+        return to_uint64();
+    }
+
+    template<int _AP_W2,bool _AP_S2>
+    INLINE ap_range_ref& operator =(const ap_private<_AP_W2,_AP_S2>& val) {
+        ap_private<_AP_W,false> vval=ap_private<_AP_W,false>(val);
+        if (l_index>h_index) {
+	        for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+	            (vval)[i]? d_bv.set(j):d_bv.clear(j);
+        } else {
+	        if (_AP_W > 64) {
+	          ap_private<_AP_W,false> mask(-1);
+	          if (l_index>0) {
+        	      mask<<=l_index;
+        	      vval<<=l_index;
+        	  }
+	  if(h_index<_AP_W-1)
+	    {
+	      ap_private<_AP_W,false> mask2(-1);
+	      mask2>>=_AP_W-h_index-1;
+	      mask&=mask2;
+	      vval&=mask2;
+	    }
+	  mask.flip();
+	  d_bv&=mask;
+	  d_bv|=vval;
+	} else {
+	  unsigned shift = 64-_AP_W;
+	  uint64_t mask = ~0ULL>>(shift);
+	  if(l_index>0)
+	    {
+	      vval = mask & vval << l_index;
+	      mask = mask & mask << l_index;
+	    }
+	  if(h_index<_AP_W-1)
+	    {
+	      uint64_t mask2 = mask;
+	      mask2 >>= (_AP_W-h_index-1);
+	      mask&=mask2;
+	      vval&=mask2;
+	    }
+	  mask = ~mask;
+	  d_bv&=mask;
+	  d_bv|=vval;
+	}
+      }
+      return *this;
+    }
+
+  INLINE ap_range_ref& operator = (unsigned long long val)
+    {
+        const ap_private<_AP_W,_AP_S> vval=val;
+        return operator = (vval);
+    }
+
+
+    INLINE ap_range_ref& operator =(const ap_range_ref<_AP_W, _AP_S>& val)
+    {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator =(tmpVal);
+    }
+
+
+
+    template<int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+    INLINE ap_range_ref& operator =
+        (const ap_concat_ref <_AP_W3, _AP_T3, _AP_W4, _AP_T4>& val)
+    {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE ap_range_ref& operator =(const ap_range_ref<_AP_W3,_AP_S3>& val)
+    {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator =(tmpVal);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_range_ref& operator= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((const ap_private<_AP_W2, _AP_S2>)(val));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_range_ref& operator= (const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=(val.to_ap_private());
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_range_ref& operator= (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((unsigned long long)(bool)(val));
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_range_ref& operator= (const ap_bit_ref<_AP_W2, _AP_S2>& val) {
+        return operator=((unsigned long long)(bool)(val));
+    }
+
+    template <int _AP_W2, bool _AP_S2>
+    INLINE
+    ap_concat_ref<_AP_W,ap_range_ref,_AP_W2,ap_range_ref<_AP_W2,_AP_S2> >
+    operator, (const ap_range_ref<_AP_W2,_AP_S2> &a2)
+    {
+        return
+            ap_concat_ref<_AP_W, ap_range_ref, _AP_W2,
+                   ap_range_ref<_AP_W2,_AP_S2> >(*this,
+                   const_cast<ap_range_ref<_AP_W2,_AP_S2>& >(a2));
+    }
+
+
+    template <int _AP_W2, bool _AP_S2>
+    INLINE ap_concat_ref<_AP_W,ap_range_ref,_AP_W2,ap_private<_AP_W2,_AP_S2> >
+    operator , (ap_private<_AP_W2,_AP_S2>& a2)
+    {
+        return
+            ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_private<_AP_W2,_AP_S2> >(*this, a2);
+    }
+
+    INLINE ap_concat_ref<_AP_W,ap_range_ref,_AP_W,ap_private<_AP_W,_AP_S> >
+    operator , (ap_private<_AP_W, _AP_S>& a2)
+    {
+        return
+            ap_concat_ref<_AP_W, ap_range_ref, _AP_W,
+                          ap_private<_AP_W,_AP_S> >(*this, a2);
+    }
+
+
+
+    template <int _AP_W2, bool _AP_S2>
+    INLINE
+    ap_concat_ref<_AP_W,ap_range_ref,1,ap_bit_ref<_AP_W2,_AP_S2> >
+    operator, (const ap_bit_ref<_AP_W2,_AP_S2> &a2)
+    {
+        return
+            ap_concat_ref<_AP_W, ap_range_ref, 1,
+                      ap_bit_ref<_AP_W2,_AP_S2> >(*this, const_cast<ap_bit_ref<
+                      _AP_W2,_AP_S2>& >(a2));
+    }
+
+
+    template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE
+    ap_concat_ref<_AP_W, ap_range_ref, _AP_W2+_AP_W3, ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+    operator, (const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2)
+    {
+        return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2+_AP_W3,
+                       ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this,
+                       const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3,
+                       _AP_T3>& >(a2));
+    }
+
+    template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE
+    ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &a2) {
+        return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, af_range_ref<_AP_W2,
+                _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                const_cast<af_range_ref<_AP_W2,_AP_I2, _AP_S2,
+                _AP_Q2, _AP_O2, _AP_N2>& >(a2));
+    }
+
+    template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE
+    ap_concat_ref<_AP_W, ap_range_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &a2) {
+        return ap_concat_ref<_AP_W, ap_range_ref, 1, af_bit_ref<_AP_W2,
+                _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                const_cast<af_bit_ref<_AP_W2,_AP_I2, _AP_S2,
+                _AP_Q2, _AP_O2, _AP_N2>& >(a2));
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator == (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs==rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator != (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs!=rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator > (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator >= (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>=rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator < (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator <= (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<=rhs;
+    }
+
+
+    template<int _AP_W2>
+    INLINE void set(const ap_private<_AP_W2,false>& val)
+    {
+        ap_private<_AP_W,_AP_S> vval=val;
+        if(l_index>h_index)
+        {
+            for(int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+                    (vval)[i]? d_bv.set(j):d_bv.clear(j);
+        } else {
+	  if (_AP_W>64 ) {
+            ap_private<_AP_W,_AP_S> mask(-1);
+            if(l_index>0)
+	      {
+                ap_private<_AP_W,false> mask1(-1);
+                mask1>>=_AP_W-l_index;
+                mask1.flip();
+                mask=mask1;
+                //vval&=mask1;
+                vval<<=l_index;
+	      }
+            if(h_index<_AP_W-1)
+	      {
+                ap_private<_AP_W,false> mask2(-1);
+                mask2<<=h_index+1;
+                mask2.flip();
+                mask&=mask2;
+                vval&=mask2;
+	      }
+            mask.flip();
+            d_bv&=mask;
+            d_bv|=vval;
+	  } else {
+	    uint64_t mask = ~0ULL >> (64-_AP_W);
+            if(l_index>0)
+	      {
+		uint64_t mask1 = mask;
+		mask1=mask & (mask1>>(_AP_W-l_index));
+		vval =mask&( vval <<l_index);
+		mask=~mask1&mask;
+		//vval&=mask1;
+	      }
+            if(h_index<_AP_W-1) {
+		uint64_t mask2 = ~0ULL >> (64-_AP_W);
+		mask2 = mask &(mask2<<(h_index+1));
+		mask&=~mask2;
+		vval&=~mask2;
+	      }
+            d_bv&=(~mask&(~0ULL >> (64-_AP_W)));
+            d_bv|=vval;
+	  }
+	}
+    }
+
+
+    INLINE ap_private<_AP_W,false> get() const
+    {
+      ap_private<_AP_W,false> val(0);
+      if(h_index<l_index) {
+	for(int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+	  if((d_bv)[j]) val.set(i);
+      } else {
+	val=d_bv;
+	val>>=l_index;
+	if(h_index<_AP_W-1)
+	  {
+	    if (_AP_W <= 64) {
+	      const static uint64_t mask = (~0ULL>> (64>_AP_W ? (64-_AP_W):0));
+	      val &=  (mask>> (_AP_W-(h_index-l_index+1)));
+	    } else {
+	      ap_private<_AP_W,false> mask(-1);
+	      mask>>=_AP_W-(h_index-l_index+1);
+	      val&=mask;
+	    }
+	  }
+      }
+      return val;
+    }
+
+
+  INLINE ap_private<_AP_W,false> get()
+  {
+    ap_private<_AP_W,false> val(0);
+    if(h_index<l_index) {
+      for(int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+	if((d_bv)[j]) val.set(i);
+    } else {
+      val=d_bv;
+      val>>=l_index;
+      if(h_index<_AP_W-1)
+	{
+	  if (_AP_W <= 64 ) {
+	    static const uint64_t mask = ~0ULL>> (64>_AP_W ? (64-_AP_W):0);
+	    return val &= ( (mask) >> (_AP_W - (h_index-l_index+1)));
+	  } else {
+	    ap_private<_AP_W,false> mask(-1);
+	    mask>>=_AP_W-(h_index-l_index+1);
+	    val&=mask;
+	  }
+	}
+    }
+    return val;
+  }
+
+
+    INLINE int length() const
+    {
+        return h_index>=l_index?h_index-l_index+1:l_index-h_index+1;
+    }
+
+
+    INLINE int to_int() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_int();
+    }
+
+
+    INLINE unsigned int to_uint() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_uint();
+    }
+
+
+    INLINE long to_long() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_long();
+    }
+
+
+    INLINE unsigned long to_ulong() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_ulong();
+    }
+
+
+    INLINE ap_slong to_int64() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_int64();
+    }
+
+
+    INLINE ap_ulong to_uint64() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_uint64();
+    }
+
+    INLINE std::string to_string(uint8_t radix=2) const {
+        return get().to_string(radix);
+    }
+
+};
+
+///Proxy class, which allows bit selection to be used as rvalue(for reading) and
+//lvalue(for writing)
+
+///Bit reference
+//--------------------------------------------------------------
+template <int _AP_W, bool _AP_S>
+struct ap_bit_ref {
+#ifdef _MSC_VER
+#pragma warning( disable : 4521 4522 )
+#endif
+    ap_private<_AP_W,_AP_S>& d_bv;
+    int d_index;
+
+public:
+    INLINE ap_bit_ref(const ap_bit_ref<_AP_W, _AP_S>& ref):
+            d_bv(ref.d_bv), d_index(ref.d_index) {}
+
+    INLINE ap_bit_ref(ap_private<_AP_W,_AP_S>& bv, int index=0):
+        d_bv(bv),d_index(index)
+    {
+#ifdef _AP_DEBUG_
+        assert(d_index<_AP_W&&"index out of bound");
+#endif
+    }
+
+
+    INLINE operator bool () const
+    {
+      return d_bv.get_bit(d_index);
+    }
+
+
+    INLINE bool to_bool() const
+    {
+        return operator bool ();
+    }
+
+
+    INLINE ap_bit_ref& operator = (unsigned long long val)
+    {
+        if(val)
+            d_bv.set(d_index);
+        else
+            d_bv.clear(d_index);
+        return *this;
+    }
+
+
+#if 0
+    INLINE ap_bit_ref& operator = (bool val)
+    {
+        if(val)
+            d_bv.set(d_index);
+        else
+            d_bv.clear(d_index);
+        return *this;
+    }
+#endif
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_bit_ref& operator =(const ap_private<_AP_W2,_AP_S2>& val)
+    {
+        return operator =((unsigned long long)(val != 0));
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_bit_ref& operator =(const ap_bit_ref<_AP_W2,_AP_S2>& val)
+    {
+        return operator =((unsigned long long)(bool)val);
+    }
+
+    INLINE ap_bit_ref& operator =(const ap_bit_ref<_AP_W,_AP_S>& val)
+    {
+        return operator =((unsigned long long)(bool)val);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_bit_ref& operator =(const ap_range_ref<_AP_W2,_AP_S2>&  val)
+    {
+        return operator =((unsigned long long)(bool) val);
+    }
+
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_bit_ref& operator= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((const ap_private<_AP_W2, false>)(val));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_bit_ref& operator= (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((unsigned long long)(bool)(val));
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_bit_ref& operator= (const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) {
+        return operator=((const ap_private<_AP_W2 + _AP_W3, false>)(val));
+    }
+
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_private<_AP_W2,_AP_S2> >
+    operator , (ap_private<_AP_W2, _AP_S2>& a2)
+     {
+        return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_private<_AP_W2,_AP_S2> >(*this, a2);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_range_ref<_AP_W2,_AP_S2> >
+    operator, (const ap_range_ref<_AP_W2, _AP_S2> &a2)
+    {
+        return
+            ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_range_ref<_AP_W2,_AP_S2> >(*this,
+                    const_cast<ap_range_ref<_AP_W2, _AP_S2> &>(a2));
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref<_AP_W2,_AP_S2> >
+    operator, (const ap_bit_ref<_AP_W2, _AP_S2> &a2)
+    {
+        return
+            ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref<_AP_W2,_AP_S2> >(*this,
+                    const_cast<ap_bit_ref<_AP_W2, _AP_S2> &>(a2));
+    }
+
+
+    INLINE ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref >
+    operator, (const ap_bit_ref &a2)
+    {
+        return
+            ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref >(*this,
+                const_cast<ap_bit_ref&>(a2));
+    }
+
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2+_AP_W3, ap_concat_ref<_AP_W2,_AP_T2,_AP_W3,_AP_T3> >
+    operator, (const ap_concat_ref<_AP_W2,_AP_T2,_AP_W3,_AP_T3> &a2)
+    {
+        return
+            ap_concat_ref<1,ap_bit_ref,_AP_W2+_AP_W3,
+                    ap_concat_ref<_AP_W2,_AP_T2,_AP_W3,_AP_T3> >(*this,
+                    const_cast<ap_concat_ref<_AP_W2,_AP_T2,_AP_W3,_AP_T3>& >(a2));
+    }
+
+    template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE
+    ap_concat_ref<1, ap_bit_ref, _AP_W2, af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &a2) {
+        return ap_concat_ref<1, ap_bit_ref, _AP_W2, af_range_ref<_AP_W2,
+                _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                const_cast<af_range_ref<_AP_W2,_AP_I2, _AP_S2, _AP_Q2,
+                _AP_O2, _AP_N2>& >(a2));
+    }
+
+    template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE
+    ap_concat_ref<1, ap_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &a2) {
+        return ap_concat_ref<1, ap_bit_ref, 1, af_bit_ref<_AP_W2,
+                _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                _AP_Q2, _AP_O2, _AP_N2>& >(a2));
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator == (const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+        return get() == op.get();
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator != (const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+        return get() != op.get();
+    }
+
+
+    INLINE bool get() const
+    {
+        return operator bool ();
+    }
+
+
+    INLINE bool get()
+    {
+        return operator bool ();
+    }
+
+
+    template <int _AP_W3>
+    INLINE void set(const ap_private<_AP_W3, false>& val)
+    {
+        operator = (val);
+    }
+
+    INLINE bool operator ~ () const {
+        bool bit = (d_bv)[d_index];
+        return bit ? false : true;
+    }
+
+    INLINE int length() const { return 1; }
+
+    INLINE std::string to_string() const {
+        bool val = get();
+        return val ? "1" : "0";
+    }
+};
+
+/// Operators mixing Integers with AP_Int
+// ----------------------------------------------------------------
+#if 1
+#define OP_BIN_MIX_INT(BIN_OP, C_TYPE, _AP_WI, _AP_SI, RTYPE)  \
+  template<int _AP_W, bool _AP_S>					\
+  INLINE typename ap_private<_AP_WI,_AP_SI>::template RType<_AP_W,_AP_S>::RTYPE \
+  operator BIN_OP ( C_TYPE i_op, const ap_private<_AP_W,_AP_S> &op) {  \
+    return ap_private<_AP_WI,_AP_SI>(i_op).operator BIN_OP (op);	\
+  }									\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE typename ap_private<_AP_W,_AP_S>::template RType<_AP_WI,_AP_SI>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W,_AP_S> &op, C_TYPE i_op) {	\
+    return op.operator BIN_OP (ap_private<_AP_WI,_AP_SI>(i_op));	\
+  }
+#else
+#define OP_BIN_MIX_INT(BIN_OP, C_TYPE, _AP_WI, _AP_SI, RTYPE)  \
+    template<int _AP_W, bool _AP_S> \
+    INLINE typename ap_private<_AP_WI,_AP_SI>::template RType<_AP_W,_AP_S>::RTYPE \
+    operator BIN_OP ( C_TYPE i_op, const ap_private<_AP_W,_AP_S> &op) {  \
+        return ap_private<_AP_WI,_AP_SI>(i_op).operator BIN_OP (op);  \
+      } \
+    template<int _AP_W, bool _AP_S>   \
+    INLINE typename ap_private<_AP_W,_AP_S>::template RType<_AP_WI,_AP_SI>::RTYPE \
+      operator BIN_OP ( const ap_private<_AP_W,_AP_S> &op, C_TYPE i_op) {  \
+        return op.operator BIN_OP (ap_private<_AP_WI,_AP_SI>(i_op));  \
+    }
+#endif
+#define OP_REL_MIX_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)  \
+  template<int _AP_W, bool _AP_S>					\
+  INLINE bool operator REL_OP ( const ap_private<_AP_W,_AP_S> &op, C_TYPE op2) { \
+    return op.operator REL_OP (ap_private<_AP_W2, _AP_S2>(op2));	\
+  }									\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE bool operator REL_OP ( C_TYPE op2, const ap_private<_AP_W,_AP_S> &op) { \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator REL_OP (op);		\
+  }
+#define OP_ASSIGN_MIX_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)		\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE ap_private<_AP_W,_AP_S> &operator ASSIGN_OP ( ap_private<_AP_W,_AP_S> &op, C_TYPE op2) { \
+    return op.operator ASSIGN_OP (ap_private<_AP_W2,_AP_S2>(op2));	\
+  }
+
+#define OP_BIN_SHIFT_INT(BIN_OP, C_TYPE, _AP_WI, _AP_SI, RTYPE)		\
+  template<int _AP_W, bool _AP_S>					\
+  C_TYPE  operator BIN_OP ( C_TYPE i_op, const ap_private<_AP_W,_AP_S> &op) { \
+    return i_op BIN_OP (op.getVal());					\
+  }									\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE typename ap_private<_AP_W,_AP_S>::template RType<_AP_WI,_AP_SI>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W,_AP_S> &op, C_TYPE i_op) {	\
+    return op.operator BIN_OP (i_op);		\
+  }
+#define OP_ASSIGN_RSHIFT_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)		\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE  ap_private<_AP_W,_AP_S> &operator ASSIGN_OP ( ap_private<_AP_W,_AP_S> &op, C_TYPE op2) { \
+    op = op.operator >> (op2);					\
+    return op;						\
+  }
+#define OP_ASSIGN_LSHIFT_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)		\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE  ap_private<_AP_W,_AP_S> &operator ASSIGN_OP ( ap_private<_AP_W,_AP_S> &op, C_TYPE op2) { \
+    op = op.operator << (op2);					\
+    return op;						\
+  }
+
+#define OPS_MIX_INT(C_TYPE, WI, SI)		\
+  OP_BIN_MIX_INT(*, C_TYPE, WI, SI, mult)	\
+    OP_BIN_MIX_INT(+, C_TYPE, WI, SI, plus)	\
+    OP_BIN_MIX_INT(-, C_TYPE, WI, SI, minus)	\
+    OP_BIN_MIX_INT(/, C_TYPE, WI, SI, div)	\
+    OP_BIN_MIX_INT(%, C_TYPE, WI, SI, mod)	\
+    OP_BIN_MIX_INT(&, C_TYPE, WI, SI, logic)	\
+    OP_BIN_MIX_INT(|, C_TYPE, WI, SI, logic)	\
+    OP_BIN_MIX_INT(^, C_TYPE, WI, SI, logic)	\
+    OP_BIN_SHIFT_INT(>>, C_TYPE, WI, SI, arg1)	\
+    OP_BIN_SHIFT_INT(<<, C_TYPE, WI, SI, arg1)	\
+						\
+    OP_REL_MIX_INT(==, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(!=, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(>, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(>=, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(<, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(<=, C_TYPE, WI, SI)		\
+						\
+    OP_ASSIGN_MIX_INT(+=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(-=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(*=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(/=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(%=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(&=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(|=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(^=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_RSHIFT_INT(>>=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_LSHIFT_INT(<<=, C_TYPE, WI, SI)
+
+
+OPS_MIX_INT(bool, 1, false)
+OPS_MIX_INT(char, 8, true)
+OPS_MIX_INT(signed char, 8, true)
+OPS_MIX_INT(unsigned char, 8, false)
+OPS_MIX_INT(short, 16, true)
+OPS_MIX_INT(unsigned short, 16, false)
+OPS_MIX_INT(int, 32, true)
+OPS_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+OPS_MIX_INT(long, 64, true)
+OPS_MIX_INT(unsigned long, 64, false)
+# else
+OPS_MIX_INT(long, 32, true)
+OPS_MIX_INT(unsigned long, 32, false)
+# endif
+OPS_MIX_INT(ap_slong, 64, true)
+OPS_MIX_INT(ap_ulong, 64, false)
+
+#define OP_BIN_MIX_RANGE(BIN_OP, RTYPE) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_private<_AP_W1,_AP_S1>::template RType<_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_range_ref<_AP_W1,_AP_S1>& op1, const ap_private<_AP_W2,_AP_S2>& op2) { \
+      return ap_private<_AP_W1, false>(op1).operator BIN_OP (op2); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_private<_AP_W1,_AP_S1>::template RType<_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W1,_AP_S1>& op1, const ap_range_ref<_AP_W2,_AP_S2>& op2) { \
+      return op1.operator BIN_OP (ap_private<_AP_W2, false>(op2)); \
+  }
+
+#define OP_REL_MIX_RANGE(REL_OP) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>   \
+  INLINE bool operator REL_OP ( const ap_range_ref<_AP_W1,_AP_S1>& op1, const ap_private<_AP_W2,_AP_S2>& op2) { \
+    return ap_private<_AP_W1,false>(op1).operator REL_OP (op2); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_private<_AP_W1,_AP_S1>& op1, const ap_range_ref<_AP_W2,_AP_S2>& op2) { \
+    return op1.operator REL_OP (op2.operator ap_private<_AP_W2, false>()); \
+  }
+
+#define OP_ASSIGN_MIX_RANGE(ASSIGN_OP) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE ap_private<_AP_W1,_AP_S1>& operator ASSIGN_OP ( ap_private<_AP_W1,_AP_S1>& op1, const ap_range_ref<_AP_W2,_AP_S2>& op2) { \
+    return op1.operator ASSIGN_OP (ap_private<_AP_W2, false>(op2)); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE ap_range_ref<_AP_W1,_AP_S1>& operator ASSIGN_OP (ap_range_ref<_AP_W1,_AP_S1>& op1, ap_private<_AP_W2,_AP_S2>& op2) { \
+    ap_private<_AP_W1, false> tmp(op1); \
+    tmp.operator ASSIGN_OP (op2); \
+    op1 = tmp; \
+    return op1; \
+  }
+
+
+OP_ASSIGN_MIX_RANGE(+=)
+OP_ASSIGN_MIX_RANGE(-=)
+OP_ASSIGN_MIX_RANGE(*=)
+OP_ASSIGN_MIX_RANGE(/=)
+OP_ASSIGN_MIX_RANGE(%=)
+OP_ASSIGN_MIX_RANGE(>>=)
+OP_ASSIGN_MIX_RANGE(<<=)
+OP_ASSIGN_MIX_RANGE(&=)
+OP_ASSIGN_MIX_RANGE(|=)
+OP_ASSIGN_MIX_RANGE(^=)
+
+OP_REL_MIX_RANGE(==)
+OP_REL_MIX_RANGE(!=)
+OP_REL_MIX_RANGE(>)
+OP_REL_MIX_RANGE(>=)
+OP_REL_MIX_RANGE(<)
+OP_REL_MIX_RANGE(<=)
+
+OP_BIN_MIX_RANGE(+, plus)
+OP_BIN_MIX_RANGE(-, minus)
+OP_BIN_MIX_RANGE(*, mult)
+OP_BIN_MIX_RANGE(/, div)
+OP_BIN_MIX_RANGE(%, mod)
+OP_BIN_MIX_RANGE(>>, arg1)
+OP_BIN_MIX_RANGE(<<, arg1)
+OP_BIN_MIX_RANGE(&, logic)
+OP_BIN_MIX_RANGE(|, logic)
+OP_BIN_MIX_RANGE(^, logic)
+
+#define OP_BIN_MIX_BIT(BIN_OP, RTYPE) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_private<1, false>::template RType<_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_bit_ref<_AP_W1,_AP_S1>& op1, const ap_private<_AP_W2,_AP_S2>& op2) { \
+      return ap_private<1, false>(op1).operator BIN_OP (op2); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_private<_AP_W1,_AP_S1>::template RType<1,false>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W1,_AP_S1>& op1, const ap_bit_ref<_AP_W2,_AP_S2>& op2) { \
+      return op1.operator BIN_OP (ap_private<1, false>(op2)); \
+  }
+
+#define OP_REL_MIX_BIT(REL_OP) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>   \
+  INLINE bool operator REL_OP ( const ap_bit_ref<_AP_W1,_AP_S1>& op1, const ap_private<_AP_W2,_AP_S2>& op2) { \
+    return ap_private<_AP_W1,false>(op1).operator REL_OP (op2); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_private<_AP_W1,_AP_S1>& op1, const ap_bit_ref<_AP_W2,_AP_S2>& op2) { \
+    return op1.operator REL_OP (ap_private<1, false>(op2)); \
+  }
+
+#define OP_ASSIGN_MIX_BIT(ASSIGN_OP) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE ap_private<_AP_W1,_AP_S1>& operator ASSIGN_OP ( ap_private<_AP_W1,_AP_S1>& op1, ap_bit_ref<_AP_W2,_AP_S2>& op2) { \
+    return op1.operator ASSIGN_OP (ap_private<1, false>(op2)); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE ap_bit_ref<_AP_W1,_AP_S1>& operator ASSIGN_OP ( ap_bit_ref<_AP_W1,_AP_S1>& op1, ap_private<_AP_W2,_AP_S2>& op2) { \
+    ap_private<1, false> tmp(op1); \
+    tmp.operator ASSIGN_OP (op2); \
+    op1 = tmp; \
+    return op1; \
+  }
+
+
+OP_ASSIGN_MIX_BIT(+=)
+OP_ASSIGN_MIX_BIT(-=)
+OP_ASSIGN_MIX_BIT(*=)
+OP_ASSIGN_MIX_BIT(/=)
+OP_ASSIGN_MIX_BIT(%=)
+OP_ASSIGN_MIX_BIT(>>=)
+OP_ASSIGN_MIX_BIT(<<=)
+OP_ASSIGN_MIX_BIT(&=)
+OP_ASSIGN_MIX_BIT(|=)
+OP_ASSIGN_MIX_BIT(^=)
+
+OP_REL_MIX_BIT(==)
+OP_REL_MIX_BIT(!=)
+OP_REL_MIX_BIT(>)
+OP_REL_MIX_BIT(>=)
+OP_REL_MIX_BIT(<)
+OP_REL_MIX_BIT(<=)
+
+OP_BIN_MIX_BIT(+, plus)
+OP_BIN_MIX_BIT(-, minus)
+OP_BIN_MIX_BIT(*, mult)
+OP_BIN_MIX_BIT(/, div)
+OP_BIN_MIX_BIT(%, mod)
+OP_BIN_MIX_BIT(>>, arg1)
+OP_BIN_MIX_BIT(<<, arg1)
+OP_BIN_MIX_BIT(&, logic)
+OP_BIN_MIX_BIT(|, logic)
+OP_BIN_MIX_BIT(^, logic)
+
+#define REF_REL_OP_MIX_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)  \
+  template<int _AP_W, bool _AP_S>   \
+  INLINE bool operator REL_OP ( const ap_range_ref<_AP_W,_AP_S> &op, C_TYPE op2) {  \
+    return (ap_private<_AP_W, false>(op)).operator REL_OP (ap_private<_AP_W2,_AP_S2>(op2));  \
+  }  \
+  template<int _AP_W, bool _AP_S> \
+  INLINE bool operator REL_OP ( C_TYPE op2, const ap_range_ref<_AP_W,_AP_S> &op) {  \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator REL_OP (ap_private<_AP_W, false>(op));  \
+  } \
+  template<int _AP_W, bool _AP_S>   \
+  INLINE bool operator REL_OP ( const ap_bit_ref<_AP_W,_AP_S> &op, C_TYPE op2) {  \
+    return (bool(op)) REL_OP op2;  \
+  }  \
+  template<int _AP_W, bool _AP_S> \
+  INLINE bool operator REL_OP ( C_TYPE op2, const ap_bit_ref<_AP_W,_AP_S> &op) {  \
+    return op2 REL_OP (bool(op));  \
+  } \
+  template<int _AP_W, typename _AP_T, int _AP_W1, typename _AP_T1>   \
+  INLINE bool operator REL_OP ( const ap_concat_ref<_AP_W,_AP_T, _AP_W1, _AP_T1> &op, C_TYPE op2) {  \
+    return (ap_private<_AP_W + _AP_W1, false>(op)).operator REL_OP (ap_private<_AP_W2,_AP_S2>(op2));  \
+  }  \
+  template<int _AP_W, typename _AP_T, int _AP_W1, typename _AP_T1>   \
+  INLINE bool operator REL_OP ( C_TYPE op2, const ap_concat_ref<_AP_W,_AP_T, _AP_W1, _AP_T1> &op) {  \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator REL_OP (ap_private<_AP_W + _AP_W1, false>(op));  \
+  }
+
+#define REF_REL_MIX_INT(C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(>, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(<, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(>=, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(<=, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(==, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(!=, C_TYPE, _AP_WI, _AP_SI)
+
+REF_REL_MIX_INT(bool, 1, false)
+REF_REL_MIX_INT(char, 8, true)
+REF_REL_MIX_INT(signed char, 8, true)
+REF_REL_MIX_INT(unsigned char, 8, false)
+REF_REL_MIX_INT(short, 16, true)
+REF_REL_MIX_INT(unsigned short, 16, false)
+REF_REL_MIX_INT(int, 32, true)
+REF_REL_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+REF_REL_MIX_INT(long, 64, true)
+REF_REL_MIX_INT(unsigned long, 64, false)
+# else
+REF_REL_MIX_INT(long, 32, true)
+REF_REL_MIX_INT(unsigned long, 32, false)
+# endif
+REF_REL_MIX_INT(ap_slong, 64, true)
+REF_REL_MIX_INT(ap_ulong, 64, false)
+
+#define REF_BIN_OP_MIX_INT(BIN_OP, RTYPE, C_TYPE, _AP_W2, _AP_S2)  \
+  template<int _AP_W, bool _AP_S>   \
+  INLINE typename ap_private<_AP_W, false>::template RType<_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_range_ref<_AP_W,_AP_S> &op, C_TYPE op2) {  \
+    return (ap_private<_AP_W, false>(op)).operator BIN_OP (ap_private<_AP_W2,_AP_S2>(op2));  \
+  }  \
+  template<int _AP_W, bool _AP_S> \
+  INLINE typename ap_private<_AP_W2, _AP_S2>::template RType<_AP_W,false>::RTYPE \
+  operator BIN_OP ( C_TYPE op2, const ap_range_ref<_AP_W,_AP_S> &op) {  \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator BIN_OP (ap_private<_AP_W, false>(op));  \
+  }
+
+#define REF_BIN_MIX_INT(C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(+, plus, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(-, minus, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(*, mult, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(/, div, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(%, mod, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(>>, arg1, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(<<, arg1, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(&, logic, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(|, logic, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(^, logic, C_TYPE, _AP_WI, _AP_SI)
+
+REF_BIN_MIX_INT(bool, 1, false)
+REF_BIN_MIX_INT(char, 8, true)
+REF_BIN_MIX_INT(signed char, 8, true)
+REF_BIN_MIX_INT(unsigned char, 8, false)
+REF_BIN_MIX_INT(short, 16, true)
+REF_BIN_MIX_INT(unsigned short, 16, false)
+REF_BIN_MIX_INT(int, 32, true)
+REF_BIN_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+REF_BIN_MIX_INT(long, 64, true)
+REF_BIN_MIX_INT(unsigned long, 64, false)
+#else
+REF_BIN_MIX_INT(long, 32, true)
+REF_BIN_MIX_INT(unsigned long, 32, false)
+#endif
+REF_BIN_MIX_INT(ap_slong, 64, true)
+REF_BIN_MIX_INT(ap_ulong, 64, false)
+
+#define REF_BIN_OP(BIN_OP, RTYPE) \
+template<int _AP_W, bool _AP_S, int _AP_W2, bool _AP_S2> \
+INLINE typename ap_private<_AP_W, false>::template RType<_AP_W2, false>::RTYPE \
+operator BIN_OP (const ap_range_ref<_AP_W,_AP_S> &lhs, const ap_range_ref<_AP_W2,_AP_S2> &rhs) {  \
+  return ap_private<_AP_W,false>(lhs).operator BIN_OP (ap_private<_AP_W2, false>(rhs));  \
+}
+
+REF_BIN_OP(+, plus)
+REF_BIN_OP(-, minus)
+REF_BIN_OP(*, mult)
+REF_BIN_OP(/, div)
+REF_BIN_OP(%, mod)
+REF_BIN_OP(>>, arg1)
+REF_BIN_OP(<<, arg1)
+REF_BIN_OP(&, logic)
+REF_BIN_OP(|, logic)
+REF_BIN_OP(^, logic)
+
+#if 1
+#define CONCAT_OP_MIX_INT(C_TYPE, _AP_WI, _AP_SI) \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private< _AP_W +  _AP_WI, false > \
+  operator, (const ap_private<_AP_W, _AP_S> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + _AP_W, false> val(op2); \
+  ap_private<_AP_WI + _AP_W, false> ret(op1); \
+  ret <<= _AP_WI; \
+  if (_AP_SI) { \
+      val <<= _AP_W; val >>= _AP_W; \
+  }\
+  ret |= val; \
+  return ret;\
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private< _AP_W +  _AP_WI, false > \
+  operator, (C_TYPE op1, const ap_private<_AP_W, _AP_S>& op2)  { \
+  ap_private<_AP_WI + _AP_W, false> val(op1); \
+  ap_private<_AP_WI + _AP_W, false> ret(op2); \
+  if (_AP_S) { \
+     ret <<= _AP_WI; ret >>= _AP_WI; \
+  } \
+  ret |= val << _AP_W; \
+  return ret; \
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private< _AP_W +  _AP_WI, false > \
+  operator, (const ap_range_ref<_AP_W, _AP_S> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + _AP_W, false> val(op2); \
+  ap_private<_AP_WI + _AP_W, false> ret(op1); \
+  ret <<= _AP_WI; \
+  if (_AP_SI) { \
+      val <<= _AP_W; val >>= _AP_W; \
+  } \
+  ret |= val; \
+  return ret; \
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private< _AP_W +  _AP_WI, false > \
+  operator, (C_TYPE op1, const ap_range_ref<_AP_W, _AP_S> &op2)  { \
+  ap_private<_AP_WI + _AP_W, false> val(op1); \
+  ap_private<_AP_WI + _AP_W, false> ret(op2); \
+  int len = op2.length(); \
+  val <<= len; \
+  ret |= val; \
+  return ret; \
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private<_AP_WI + 1, false > \
+  operator, (const ap_bit_ref<_AP_W, _AP_S> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + 1, false> val(op2); \
+  val[_AP_WI] = op1; \
+  return val; \
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private<_AP_WI + 1, false > \
+  operator, (C_TYPE op1, const ap_bit_ref<_AP_W, _AP_S> &op2)  { \
+  ap_private<_AP_WI + 1, false> val(op1); \
+  val <<= 1; \
+  val[0] = op2; \
+  return val; \
+} \
+template<int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2> \
+INLINE \
+ap_private<_AP_W + _AP_W2 + _AP_WI, false > \
+   operator, (const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op1, C_TYPE op2) {\
+   ap_private<_AP_WI + _AP_W + _AP_W2, _AP_SI> val(op2);\
+   ap_private<_AP_WI + _AP_W + _AP_W2, _AP_SI> ret(op1);\
+   if (_AP_SI) { \
+       val <<= _AP_W + _AP_W2; val >>= _AP_W + _AP_W2; \
+   } \
+   ret <<= _AP_WI; \
+   ret |= val; \
+   return ret; \
+}\
+template<int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2> \
+INLINE \
+ap_private<_AP_W + _AP_W2 + _AP_WI, false > \
+   operator, (C_TYPE op1, const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op2) {\
+   ap_private<_AP_WI + _AP_W + _AP_W2, _AP_SI> val(op1);\
+   ap_private<_AP_WI + _AP_W + _AP_W2, _AP_SI> ret(op2);\
+   int len = op2.length(); \
+   val <<= len; \
+   ret |= val;\
+   return ret; \
+}\
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, \
+         int _AP_N > \
+INLINE \
+ap_private< _AP_W + _AP_WI, false > \
+  operator, (const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + _AP_W, false> val(op2); \
+  ap_private<_AP_WI + _AP_W, false> ret(op1); \
+  if (_AP_SI) { \
+      val <<= _AP_W; val >>= _AP_W; \
+  }\
+  ret <<= _AP_WI; \
+  ret |= val; \
+  return ret; \
+} \
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, \
+         int _AP_N > \
+INLINE \
+ap_private< _AP_W + _AP_WI, false > \
+  operator, (C_TYPE op1, const af_range_ref<_AP_W, _AP_I, _AP_S, \
+             _AP_Q, _AP_O, _AP_N> &op2) { \
+  ap_private<_AP_WI + _AP_W, false> val(op1); \
+  ap_private<_AP_WI + _AP_W, false> ret(op2); \
+  int len = op2.length(); \
+  val <<= len; \
+  ret |= val; \
+  return ret; \
+} \
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, \
+         int _AP_N > \
+INLINE \
+ap_private< 1 + _AP_WI, false> \
+  operator, (const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, \
+             _AP_N> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + 1, _AP_SI> val(op2); \
+  val[_AP_WI] = op1; \
+  return val; \
+} \
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, \
+         int _AP_N > \
+INLINE \
+ap_private< 1 + _AP_WI, false> \
+  operator, (C_TYPE op1, const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q,\
+        _AP_O, _AP_N> &op2) { \
+  ap_private<_AP_WI + 1, _AP_SI> val(op1); \
+  val <<= 1; \
+  val[0] = op2; \
+  return val; \
+}
+
+CONCAT_OP_MIX_INT(bool, 1, false)
+CONCAT_OP_MIX_INT(char, 8, true)
+CONCAT_OP_MIX_INT(signed char, 8, true)
+CONCAT_OP_MIX_INT(unsigned char, 8, false)
+CONCAT_OP_MIX_INT(short, 16, true)
+CONCAT_OP_MIX_INT(unsigned short, 16, false)
+CONCAT_OP_MIX_INT(int, 32, true)
+CONCAT_OP_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+CONCAT_OP_MIX_INT(long, 64, true)
+CONCAT_OP_MIX_INT(unsigned long, 64, false)
+# else
+CONCAT_OP_MIX_INT(long, 32, true)
+CONCAT_OP_MIX_INT(unsigned long, 32, false)
+# endif
+CONCAT_OP_MIX_INT(ap_slong, 64, true)
+CONCAT_OP_MIX_INT(ap_ulong, 64, false)
+#endif
+
+#if 1
+#define CONCAT_SHIFT_MIX_INT(C_TYPE, op) \
+template<int _AP_W, typename _AP_T, int _AP_W1, typename _AP_T1>   \
+INLINE ap_uint<_AP_W+_AP_W1> operator op (const ap_concat_ref<_AP_W, _AP_T, _AP_W1, _AP_T1> lhs, C_TYPE rhs) { \
+  return ((ap_uint<_AP_W+_AP_W1>)lhs.get()) op ((int)rhs); \
+}
+
+CONCAT_SHIFT_MIX_INT(long, <<)
+CONCAT_SHIFT_MIX_INT(unsigned long, <<)
+CONCAT_SHIFT_MIX_INT(unsigned int, <<)
+CONCAT_SHIFT_MIX_INT(ap_ulong, <<)
+CONCAT_SHIFT_MIX_INT(ap_slong, <<)
+CONCAT_SHIFT_MIX_INT(long, >>)
+CONCAT_SHIFT_MIX_INT(unsigned long, >>)
+CONCAT_SHIFT_MIX_INT(unsigned int, >>)
+CONCAT_SHIFT_MIX_INT(ap_ulong, >>)
+CONCAT_SHIFT_MIX_INT(ap_slong, >>)
+#endif
+
+#if defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED)
+template<int _AP_W, bool _AP_S>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_private<_AP_W, _AP_S> &op,
+                     const std::string &name) {
+    if (tf)
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+#endif
+
+template<int _AP_W, bool _AP_S>
+INLINE std::ostream& operator<<(std::ostream& out, const ap_private<_AP_W,_AP_S> &op)
+{
+  ap_private<_AP_W, _AP_S> v=op;
+    const std::ios_base::fmtflags basefield = out.flags() & std::ios_base::basefield;
+    unsigned radix = (basefield == std::ios_base::hex) ? 16 :
+                     ((basefield == std::ios_base::oct) ? 8 : 10);
+    std::string str=v.toString(radix,_AP_S);
+    out<<str;
+    return out;
+
+}
+
+template<int _AP_W, bool _AP_S>
+INLINE std::istream& operator >> (std::istream& in, ap_private<_AP_W,_AP_S> &op)
+{
+    std::string str;
+    in >> str;
+    op = ap_private<_AP_W, _AP_S>(str.c_str());
+    return in;
+
+}
+
+template<int _AP_W, bool _AP_S>
+INLINE std::ostream& operator<<(std::ostream& out, const ap_range_ref<_AP_W,_AP_S> &op)
+{
+    return operator<<(out, ap_private<_AP_W, _AP_S>(op));
+}
+
+template<int _AP_W, bool _AP_S>
+INLINE std::istream& operator >> (std::istream& in, ap_range_ref<_AP_W,_AP_S> &op)
+{
+    return operator>>(in, ap_private<_AP_W, _AP_S>(op));;
+}
+
+template<int _AP_W, bool _AP_S>
+INLINE void print(const ap_private<_AP_W,_AP_S> &op, bool fill=true )
+{
+    ap_private<_AP_W, _AP_S> v=op;
+    uint32_t ws=v.getNumWords();
+    const uint64_t *ptr=v.getRawData();
+    int i=ws-1;
+#if 0
+    if(fill)
+        printf("%016llx",*(ptr+i));
+    else
+        printf("%llx",*(ptr+i));
+#else
+//match SystemC output
+    if(_AP_W%64 != 0) {
+        uint32_t offset=_AP_W%64;
+        uint32_t count=(offset+3)/4;
+        int64_t data=*(ptr+i);
+        if(_AP_S)
+            data=(data<<(64-offset))>>(64-offset);
+        else
+            count=(offset+4)/4;
+        while(count-->0)
+            printf("%llx",(data>>(count*4))&0xf);
+    } else {
+        if(_AP_S==false)
+            printf("0");
+        printf("%016llx",*(ptr+i));
+    }
+#endif
+    for(--i;i>=0;i--)
+        printf("%016llx",*(ptr+i));
+    printf("\n");
+
+}
+#endif /* #ifndef __AESL_GCC_AP_INT_H__ */
\ No newline at end of file

hls_2018/router_02_boardstr/main.cpp

+/**
+ * main.cpp
+ *
+ * for Vivado HLS
+ */
+
+#ifdef SOFTWARE
+#include "ap_int.h"
+#else
+#include <ap_int.h>
+#endif
+
+#ifdef CALCTIME
+#include <stdio.h>
+#include <time.h>
+#endif
+
+#include "router.hpp"
+
+#define PRINT_SOLUTION
+
+
+int main(int argc, char *argv[]) {
+    using namespace std;
+
+    // Test data // 
+    // NL_Q00.txt
+    //char boardstr[BOARDSTR_SIZE] = "X10Y05Z3L0000107041L0004107002L0102102021L0900100003";
+    // NL_Q06.txt
+    char boardstr[BOARDSTR_SIZE] = "X10Y18Z2L0900109002L0901105012L0902103052L0903103062L0904100102L0905106012L0906109022L0717109102L0808109112L0017209172L0401200072L0912208152L0009201092L0709209092L0901206052L0309204092L0701209072L0101201022L0011202152L0016202162";
+    // NL_Q08.txt
+    //char boardstr[BOARDSTR_SIZE] = "X17Y20Z2L0000103022L1603115052L0916107032L0302108012L1104111042L1002100002L0919116162L1616113182L1001115012L0500201182L1603213152L0600210022";
+    char boardstr_high[BOARDSTR_SIZE] = {};
+
+    // Read boardstr from command line
+    if (1 < argc) {
+        // From stdin
+        if(argv[1][0]!='X')
+        {
+            char* c_p=fgets(boardstr, BOARDSTR_SIZE, stdin);
+            int length=strlen(c_p);
+            boardstr[length-1]=0;
+        }
+        else
+        {
+            strcpy(boardstr, argv[1]);
+        }
+    }
+
+    // Seed value
+    int seed = 12345;
+    if (2 < argc) {
+        seed = atoi(argv[2]);
+    }
+
+#ifdef PRINT_SOLUTION
+    int size_x = (boardstr[1] - '0') * 10 + (boardstr[2] - '0');
+    int size_y = (boardstr[4] - '0') * 10 + (boardstr[5] - '0');
+    int size_z = (boardstr[7] - '0');
+#endif
+
+    // Solver
+    ap_int<32> status;
+    clock_t clock_start, clock_done;
+    clock_start = clock();
+    bool result = pynqrouter(boardstr, boardstr_high, seed, &status);
+    clock_done = clock();
+    if (result) {
+        cout << endl << "Test Passed!" << endl;
+    } else {
+        cout << endl << "Test Failed!" << endl;
+    }
+    cout << "status = " << (int)status << endl;
+    cout << "elapsed = " << ((double)(clock_done - clock_start) / CLOCKS_PER_SEC) << endl << endl;
+
+#ifdef PRINT_SOLUTION
+    cout << "SOLUTION" << endl;
+    cout << "========" << endl;
+    cout << "SIZE " << size_x << "X" << size_y << "X" << size_z << endl;
+    for (int z = 0; z < size_z; z++) {
+        cout << "LAYER " << (z + 1) << endl;
+        for (int y = 0; y < size_y; y++) {
+            for (int x = 0; x < size_x; x++) {
+                if (x != 0) {
+                    cout << ",";
+                }
+                int i = ((x * MAX_WIDTH + y) << BITWIDTH_Z) | z;
+                unsigned int num = (unsigned char)(boardstr[i]) + ((unsigned char)(boardstr_high[i]) << 8);
+                cout << setfill('0') << setw(3) << right << num;
+                //cout << num;
+            }
+            cout << endl;
+        }
+    }
+#endif
+
+    return 0;
+}
+

hls_2018/router_02_boardstr/router.cpp

+/**
+ * router.cpp
+ *
+ * for Vivado HLS
+ */
+
+#ifdef SOFTWARE
+#include "ap_int.h"
+#else
+#include <ap_int.h>
+#endif
+
+#include "./router.hpp"
+
+// Set weight
+ap_uint<8> new_weight(ap_uint<16> x) {
+#pragma HLS INLINE
+    // K. Terada: y = 1~32 (8bit)
+    ap_uint<8> y;
+    y = ((x & 255) >> 3) + 1;
+    return y;
+}
+
+
+// Global values
+static ap_uint<7> size_x;    // X
+static ap_uint<7> size_y;    // Y
+static ap_uint<4> size_z;    // Z
+
+static ap_uint<LINE_BIT> line_num = 0; // #Lines
+
+#ifdef DEBUG_PRINT
+int max_queue_length;    // Max length of priority queue
+int max_search_count;    // Max count of queue pop
+int max_buffer_length;   // Max length of line buffer
+#endif
+
+
+bool pynqrouter(char boardstr[BOARDSTR_SIZE], char boardstr_high[BOARDSTR_SIZE], ap_uint<32> seed, ap_int<32> *status) {
+#pragma HLS INTERFACE s_axilite port=boardstr bundle=AXI4LS
+#pragma HLS INTERFACE s_axilite port=boardstr_high bundle=AXI4LS
+#pragma HLS INTERFACE s_axilite port=seed bundle=AXI4LS
+#pragma HLS INTERFACE s_axilite port=status bundle=AXI4LS
+#pragma HLS INTERFACE s_axilite port=return bundle=AXI4LS
+
+    // status(0:Solved, 1:Not solved)
+    *status = -1;
+
+    // For all lines
+    ap_uint<CELL_BIT> paths[MAX_BUFFER];    // Line buffer
+
+    // For each line
+    // Note: Should not partition completely
+    bool adjacents[MAX_LINES];              // Line has adjacent terminals?
+    ap_uint<CELL_BIT> starts[MAX_LINES];    // Start list
+    ap_uint<CELL_BIT> goals[MAX_LINES];     // Goal list
+    ap_uint<BUFF_BIT> s_idx[MAX_LINES];     // Start point on line buffer
+
+    ap_uint<8> weights[MAX_CELLS];          // Weight of each cell
+    // Note: Should not partition weight array
+    // since each element will be accessed in "random" order
+
+
+    // ================================
+    // (Step.0) Initialization (BEGIN)
+    // ================================
+
+    // Note: Loop counter -> need an extra bit (for condition determination)
+
+    INIT_WEIGHTS:
+    for (ap_uint<CELL_BIT> i = 0; i < (ap_uint<CELL_BIT>)(MAX_CELLS); i++) {
+#pragma HLS UNROLL factor=2
+        weights[i] = 1;
+    }
+
+    /// Parse ///
+    size_x = (boardstr[1] - '0') * 10 + (boardstr[2] - '0');
+    size_y = (boardstr[4] - '0') * 10 + (boardstr[5] - '0');
+    size_z = (boardstr[7] - '0');
+
+    INIT_BOARDS:
+    for (ap_uint<CELL_BIT> idx = 8; idx < (ap_uint<CELL_BIT>)(BOARDSTR_SIZE); idx+=11) {
+
+    	// NULL-terminated
+        if (boardstr[idx] == 0) break;
+
+        // Start & Goal of each line
+        ap_uint<7> s_x = (boardstr[idx+1] - '0') * 10 + (boardstr[idx+2] - '0');
+        ap_uint<7> s_y = (boardstr[idx+3] - '0') * 10 + (boardstr[idx+4] - '0');
+        ap_uint<3> s_z = (boardstr[idx+5] - '0') - 1;
+        ap_uint<7> g_x = (boardstr[idx+6] - '0') * 10 + (boardstr[idx+7] - '0');
+        ap_uint<7> g_y = (boardstr[idx+8] - '0') * 10 + (boardstr[idx+9] - '0');
+        ap_uint<3> g_z = (boardstr[idx+10] - '0') - 1;
+
+        ap_uint<CELL_BIT> start_id = (((ap_uint<CELL_BIT>)s_x * MAX_WIDTH + (ap_uint<CELL_BIT>)s_y) << BITWIDTH_Z) | (ap_uint<CELL_BIT>)s_z;
+        ap_uint<CELL_BIT> goal_id  = (((ap_uint<CELL_BIT>)g_x * MAX_WIDTH + (ap_uint<CELL_BIT>)g_y) << BITWIDTH_Z) | (ap_uint<CELL_BIT>)g_z;
+        starts[line_num] = start_id;
+        goals[line_num] = goal_id;
+        weights[start_id] = MAX_WEIGHT;
+        weights[goal_id] = MAX_WEIGHT;
+
+        // Line has adjacent terminals?
+        adjacents[line_num] = false;
+        ap_int<8> dx = (ap_int<8>)g_x - (ap_int<8>)s_x; // Min: -71, Max: 71 (Signed 8bit)
+        ap_int<8> dy = (ap_int<8>)g_y - (ap_int<8>)s_y; // Min: -71, Max: 71 (Signed 8bit)
+        ap_int<4> dz = (ap_int<4>)g_z - (ap_int<4>)s_z; // Min:  -7, Max:  7 (Signed 4bit)
+        if ((dx == 0 && dy == 0 && (dz == 1 || dz == -1)) || (dx == 0 && (dy == 1 || dy == -1) && dz == 0) || ((dx == 1 || dx == -1) && dy == 0 && dz == 0)) {
+            adjacents[line_num] = true;
+        }
+
+        line_num++;
+    }
+
+    // ================================
+    // (Step.0) Initialization (END)
+    // ================================
+
+#ifdef DEBUG_PRINT
+    max_queue_length = 0;
+    max_search_count = 0;
+    max_buffer_length = 0;
+#endif
+
+    ap_uint<BUFF_BIT> pointer = 0; // Pointer for line buffer
+
+    // ================================
+    // (Step.1) Initial Routing (BEGIN)
+    // ================================
+
+#ifdef DEBUG_PRINT
+    cout << "Initial Routing ..." << endl;
+#endif
+
+    FIRST_ROUTING:
+    for (ap_uint<LINE_BIT> i = 0; i < (ap_uint<LINE_BIT>)(line_num); i++) {
+#pragma HLS LOOP_TRIPCOUNT min=2 max=999
+
+        s_idx[i] = pointer;
+
+        if (adjacents[i] == true) continue; // Skip routing
+
+#ifdef DEBUG_PRINT
+        //cout << "LINE #" << (int)(i + 1) << endl;
+#endif
+        // Routing
+        ap_uint<BUFF_BIT> dummy = MAX_BUFFER-1;
+        pointer = search(s_idx[i], &dummy, paths, starts[i], goals[i], weights);
+    }
+
+    // ================================
+    // (Step.1) Initial Routing (END)
+    // ================================
+
+
+    // Memories for Overlap Check
+    ap_uint<1> overlap_checks[MAX_CELLS];
+#pragma HLS ARRAY_PARTITION variable=overlap_checks cyclic factor=16 dim=1
+    bool has_overlap = false;
+
+    // ================================
+    // (Step.2) Rip-up Routing (BEGIN)
+    // ================================
+
+#ifdef DEBUG_PRINT
+    cout << "Rip-up Routing ..." << endl;
+#endif
+
+    ap_uint<LINE_BIT> target = line_num - 1, next_target;
+
+    ROUTING:
+    for (ap_uint<16> round = 0; round < 32768 /* = (2048 * 16) */; round++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=32768
+
+        // Target line
+        target = round % line_num;
+        next_target = target + 1;
+        if (next_target == line_num) next_target = 0;
+
+#ifdef DEBUG_PRINT
+        //cout << "(round " << round << ") LINE #" << (int)(target + 1);
+        //cout << " -> " << pointer << endl;
+#endif
+#ifdef DEBUG_PRINT
+        int buffer_length = pointer - s_idx[target];
+        if (max_buffer_length < buffer_length) { max_buffer_length = buffer_length; }
+#endif
+
+        // Skip routing
+        if (adjacents[target] == true) {
+            s_idx[target] = pointer;  continue;
+        }
+
+
+        // (Step.2-1) Reset weights of target line
+        WEIGHT_RESET:
+        for (ap_uint<BUFF_BIT> j = s_idx[target]; j != s_idx[next_target]; j++) {
+#pragma HLS UNROLL factor=2
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+            weights[paths[j]] = 1;
+        }
+
+        // (Step.2-2) Set weights of non-target lines and terminals
+        ap_uint<8> current_round_weight = new_weight(round);
+        WEIGHT_PATH:
+        for (ap_uint<BUFF_BIT> j = s_idx[next_target]; j != pointer; j++) {
+#pragma HLS UNROLL factor=2
+#pragma HLS LOOP_TRIPCOUNT min=1 max=8192
+            weights[paths[j]] = current_round_weight;
+        }
+        WEIGHT_TERMINAL:
+        for (ap_uint<LINE_BIT> i = 0; i < (ap_uint<LINE_BIT>)(line_num); i++) {
+#pragma HLS UNROLL factor=2
+#pragma HLS LOOP_TRIPCOUNT min=2 max=999
+            weights[starts[i]] = MAX_WEIGHT;
+            weights[goals[i]] = MAX_WEIGHT;
+        }
+        // Reset weight of start terminal of target line (bug avoiding)
+        // Restore original settings in (*)
+        weights[starts[target]] = 1;
+
+        // (Step.2-3) Routing
+        s_idx[target] = pointer;
+        ap_uint<BUFF_BIT> n_idx = s_idx[next_target]; // For overflow check
+        pointer = search(s_idx[target], &n_idx, paths, starts[target], goals[target], weights);
+		//pointer = search(s_idx[target], paths, starts[target], goals[target], weights);
+        //cout << n_idx << ", " << s_idx[next_target] << endl;
+
+        // (*)
+        weights[starts[target]] = MAX_WEIGHT;
+
+#ifdef DEBUG_PRINT
+    bool ng = false;
+    for (ap_uint<LINE_BIT> i = 0; i < (ap_uint<LINE_BIT>)(line_num); i++) {
+    	if (weights[starts[i]] != 255 || weights[goals[i]] != 255) {
+            cout << i << " "; ng = true;
+        }
+    }
+    if(ng) { cout << endl; }
+#endif
+
+        // (Step.2-4) Overlap check
+        has_overlap = false;
+        if (n_idx != s_idx[next_target]) break; // Overflow check
+        OVERLAP_RESET:
+        for (ap_uint<CELL_BIT> i = 0; i < (ap_uint<CELL_BIT>)(MAX_CELLS); i++) {
+#pragma HLS UNROLL factor=32
+            overlap_checks[i] = 0;
+        }
+        OVERLAP_CHECK_LINE:
+        for (ap_uint<LINE_BIT> i = 0; i < (ap_uint<LINE_BIT>)(line_num); i++) {
+#pragma HLS UNROLL factor=2
+#pragma HLS LOOP_TRIPCOUNT min=2 max=999
+            overlap_checks[starts[i]] = 1;
+            overlap_checks[goals[i]] = 1;
+        }
+        OVERLAP_CHECK_PATH:
+        for (ap_uint<BUFF_BIT> j = s_idx[next_target]; j != pointer; j++) {
+#pragma HLS UNROLL factor=2
+#pragma HLS LOOP_TRIPCOUNT min=1 max=8192
+            ap_uint<CELL_BIT> cell_id = paths[j];
+            if (overlap_checks[cell_id]) {
+                has_overlap = true;  break;
+            }
+            overlap_checks[cell_id] = 1;
+        }
+#ifdef DEBUG_PRINT
+    if(!has_overlap){ cout << "ROUND: " << round << endl; }
+#endif
+        if (!has_overlap) break; // Finish routing?
+    }
+
+#ifdef DEBUG_PRINT
+    cout << "MAX PQ LENGTH: " << max_queue_length << endl;
+    cout << "MAX SEARCH COUNT: " << max_search_count << endl;
+    cout << "MAX BUFFER: " << max_buffer_length << endl;
+#endif
+
+    // Not solved
+    if (has_overlap) {
+        *status = 1;  return false;
+    }
+
+    // ================================
+    // (Step.2) Rip-up Routing (END)
+    // ================================
+
+
+    // ================================
+    // (Step.3) Output (BEGIN)
+    // ================================
+
+#ifdef DEBUG_PRINT
+    cout << "Output ..." << endl;
+#endif
+
+    // Init: Blank = 0
+    OUTPUT_INIT:
+    for (ap_uint<CELL_BIT> i = 0; i < (ap_uint<CELL_BIT>)(MAX_CELLS); i++) {
+        boardstr[i] = 0;
+        boardstr_high[i] = 0;
+    }
+    // Line
+    OUTPUT_LINE:
+    for (ap_uint<LINE_BIT> i = 0; i < (ap_uint<LINE_BIT>)(line_num); i++) {
+#pragma HLS LOOP_TRIPCOUNT min=2 max=999
+        boardstr[starts[i]] = (i + 1);
+        boardstr[goals[i]] = (i + 1);
+        boardstr_high[starts[i]] = (i + 1) >> 8;
+        boardstr_high[goals[i]] = (i + 1) >> 8;
+
+/**
+    cout << "#" << i;
+    ap_uint<13> start_xy = (ap_uint<13>)(starts[i] >> BITWIDTH_Z);
+    ap_uint<7> start_x = (ap_uint<7>)(start_xy / MAX_WIDTH);
+    ap_uint<7> start_y = (ap_uint<7>)(start_xy - start_x * MAX_WIDTH);
+    ap_uint<3> start_z = (ap_uint<3>)(starts[i] & BITMASK_Z);
+    ap_uint<13> goal_xy = (ap_uint<13>)(goals[i] >> BITWIDTH_Z);
+    ap_uint<7> goal_x = (ap_uint<7>)(goal_xy / MAX_WIDTH);
+    ap_uint<7> goal_y = (ap_uint<7>)(goal_xy - goal_x * MAX_WIDTH);
+    ap_uint<3> goal_z = (ap_uint<3>)(goals[i] & BITMASK_Z);
+    cout << "(" << start_x << "," << start_y << "," << start_z << ")->";
+    cout << "(" << goal_x << "," << goal_y << "," << goal_z << ")" << endl;
+**/
+
+        ap_uint<BUFF_BIT> p1; // p1: s_idx of target
+        ap_uint<BUFF_BIT> p2; // p2: s_idx of next target
+        p1 = s_idx[i];
+        if (i == (ap_uint<LINE_BIT>)(line_num-1)) {
+            p2 = s_idx[0];
+        }
+        else {
+            p2 = s_idx[i+1];
+        }
+        if (i == target) {
+            p2 = pointer;
+        }
+        OUTPUT_LINE_PATH:
+        for (ap_uint<BUFF_BIT> j = p1; j != p2; j++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+            boardstr[paths[j]] = (i + 1);
+            boardstr_high[paths[j]] = (i + 1) >> 8;
+
+/**
+    ap_uint<13> trgt_xy = (ap_uint<13>)(paths[j] >> BITWIDTH_Z);
+    ap_uint<7> trgt_x = (ap_uint<7>)(trgt_xy / MAX_WIDTH);
+    ap_uint<7> trgt_y = (ap_uint<7>)(trgt_xy - trgt_x * MAX_WIDTH);
+    ap_uint<3> trgt_z = (ap_uint<3>)(paths[j] & BITMASK_Z);
+    cout << "(" << trgt_x << "," << trgt_y << "," << trgt_z << ")";
+**/
+
+        }
+/**
+    cout << endl;
+**/
+    }
+
+    // ================================
+    // (Step.3) Output (END)
+    // ================================
+
+    *status = 0;  return true;
+}
+
+
+// ================================ //
+// For Routing
+// ================================ //
+
+// Max: 71, Min: 0 (7bit)
+ap_uint<7> abs_uint7(ap_uint<7> a, ap_uint<7> b) {
+#pragma HLS INLINE
+    if (a < b) { return b - a; }
+    else  { return a - b; }
+}
+// Max: 7, Min: 0 (3bit)
+ap_uint<3> abs_uint3(ap_uint<3> a, ap_uint<3> b) {
+#pragma HLS INLINE
+    if (a < b) { return b - a; }
+    else  { return a - b; }
+}
+
+// Reference codes:
+// http://lethe2211.hatenablog.com/entry/2014/12/30/011030
+// http://www.redblobgames.com/pathfinding/a-star/implementation.html
+// Need to modify "array partition factor"
+ap_uint<BUFF_BIT> search(ap_uint<BUFF_BIT> idx, ap_uint<BUFF_BIT> *n_idx, ap_uint<CELL_BIT> paths[MAX_BUFFER], ap_uint<CELL_BIT> start, ap_uint<CELL_BIT> goal, ap_uint<8> w[MAX_CELLS]) {
+
+    ap_uint<CELL_BIT> dist[MAX_CELLS];
+#pragma HLS ARRAY_PARTITION variable=dist cyclic factor=64 dim=1
+    ap_uint<CELL_BIT> prev[MAX_CELLS];
+
+    SEARCH_INIT_DIST:
+    for (ap_uint<CELL_BIT> i = 0; i < (ap_uint<CELL_BIT>)(MAX_CELLS); i++) {
+#pragma HLS UNROLL factor=128
+        dist[i] = 65535; // = (2^16 - 1)
+    }
+
+    // Priority queue (Circular list)
+    ap_uint<PQ_BIT> top = 1, bottom = 0;
+    bool is_empty = true;
+    ap_uint<32> pq_nodes[MAX_PQ];
+#pragma HLS ARRAY_PARTITION variable=pq_nodes cyclic factor=32 dim=1
+/** Set!: factor=PP **/
+
+#ifdef DEBUG_PRINT
+    int queue_length = 0;
+    int search_count = 0;
+#endif
+
+    // Point of goal terminal
+    ap_uint<13> goal_xy = (ap_uint<13>)(goal >> BITWIDTH_Z);
+    ap_uint<7> goal_x = (ap_uint<7>)(goal_xy / MAX_WIDTH);
+    ap_uint<7> goal_y = (ap_uint<7>)(goal_xy - goal_x * MAX_WIDTH);
+    ap_uint<3> goal_z = (ap_uint<3>)(goal & BITMASK_Z);
+
+    dist[start] = 0;
+    pq_push(pq_nodes, 0, start, &top, &bottom, &is_empty); // push start terminal
+
+    SEARCH_PQ:
+    while (!is_empty) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=1000
+#pragma HLS LOOP_FLATTEN off
+
+        ap_uint<16> prev_cost;
+        ap_uint<16> src; // target cell
+        pq_pop(pq_nodes, &prev_cost, &src, &top, &bottom, &is_empty);
+#ifdef DEBUG_PRINT
+        search_count++;
+#endif
+
+
+        // End routing
+        if (src == goal) break;
+
+
+        // Target cell
+        ap_uint<16> dist_src = dist[src];
+        ap_uint<8> cost = w[src];
+        // Point of target cell
+        ap_uint<13> src_xy = (ap_uint<13>)(src >> BITWIDTH_Z);
+        ap_uint<7> src_x = (ap_uint<7>)(src_xy / MAX_WIDTH);
+        ap_uint<7> src_y = (ap_uint<7>)(src_xy - src_x * MAX_WIDTH);
+        ap_uint<3> src_z = (ap_uint<3>)(src & BITMASK_Z);
+
+        // Search adjacent cells
+        SEARCH_ADJACENTS:
+        for (ap_uint<3> a = 0; a < 6; a++) {
+            ap_int<8> dest_x = (ap_int<8>)src_x; // Min: -1, Max: 72 (Signed 8bit)
+            ap_int<8> dest_y = (ap_int<8>)src_y; // Min: -1, Max: 72 (Signed 8bit)
+            ap_int<5> dest_z = (ap_int<5>)src_z; // Min: -1, Max:  8 (Signed 5bit)
+            if (a == 0) { dest_x -= 1; }
+            if (a == 1) { dest_x += 1; }
+            if (a == 2) { dest_y -= 1; }
+            if (a == 3) { dest_y += 1; }
+            if (a == 4) { dest_z -= 1; }
+            if (a == 5) { dest_z += 1; }
+
+            // Inside the board ? //
+            if (0 <= dest_x && dest_x < (ap_int<8>)size_x && 0 <= dest_y && dest_y < (ap_int<8>)size_y && 0 <= dest_z && dest_z < (ap_int<5>)size_z) {
+            	// Adjacent cell
+                ap_uint<16> dest = (((ap_uint<16>)dest_x * MAX_WIDTH + (ap_uint<16>)dest_y) << BITWIDTH_Z) | (ap_uint<16>)dest_z;
+                ap_uint<16> dist_new = dist_src + cost;
+
+                if (dist[dest] > dist_new) {
+                    dist[dest] = dist_new;	// Update dist
+                    prev[dest] = src;		// Recode previous cell
+                    dist_new += abs_uint7(dest_x, goal_x) + abs_uint7(dest_y, goal_y) + abs_uint3(dest_z, goal_z); // A* heuristic
+                    pq_push(pq_nodes, dist_new, dest, &top, &bottom, &is_empty); // push adjacent cell
+                }
+            }
+        }
+#ifdef DEBUG_PRINT
+        if (queue_length < (bottom-top+1)) { queue_length = (bottom-top+1); }
+#endif
+    }
+
+    // Output target path
+    // Note: Do not include start & goal terminals
+    ap_uint<16> t = prev[goal];
+
+    // Backtracking
+    ap_uint<BUFF_BIT> p = idx; // buffer-idx
+    SEARCH_BACKTRACK:
+    while (t != start) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=256
+        // overflow check
+        if (p == (*n_idx)) {
+            (*n_idx)++; break;
+        }
+        paths[p] = t;
+        p++;
+        t = prev[t];
+    }
+
+#ifdef DEBUG_PRINT
+    if (max_queue_length < queue_length) { max_queue_length = queue_length; }
+    if (max_search_count < search_count) { max_search_count = search_count; }
+#endif
+
+    return p;
+}
+
+// Queue push (Enqueue)
+// Need to modify "trip count" (5)
+void pq_push(ap_uint<32> pq_nodes[MAX_PQ], ap_uint<16> priority, ap_uint<16> data, ap_uint<PQ_BIT> *top, ap_uint<PQ_BIT> *bottom, bool *is_empty) {
+#pragma HLS INLINE
+
+    (*bottom)++;
+    if ((*bottom) == (*top) && !(*is_empty)) { (*bottom)--; } // Queue is full -> Last element is automatically removed
+
+    // Binary search for circular list
+    ap_uint<PQ_BIT> t = (*top);
+    ap_uint<PQ_BIT> b = (*bottom);
+    ap_uint<PQ_BIT> h = ((ap_uint<PQ_BIT>)(b - t) / 2) + t;
+    // Note: "h = (t + b) / 2" causes a bug!
+    PQ_PUSH_BINARY:
+    while (t != b) {
+#pragma HLS LOOP_TRIPCOUNT min=0 max=13
+/** Set!: min=0 max=PQ_BIT **/
+    	if ((ap_uint<16>)(pq_nodes[h] & PQ_PRIORITY_MASK) >= priority) {
+    		b = h;
+    	}
+    	else {
+    		t = h + 1;
+    	}
+    	h = ((ap_uint<PQ_BIT>)(b - t) / 2) + t;
+    }
+
+    // Parallel shifting (PP parallel)
+    ap_uint<PQ_BIT> shift_count = (*bottom) - t; // # of shifting
+
+    ap_uint<PQ_BIT-LOG_PP> bottom_H = (*bottom) / PP; // High-order bits of (*bottom)
+    ap_uint<LOG_PP> bottom_L = (*bottom) % PP; // Low-order bits of (*bottom)
+    ap_uint<PQ_BIT> p0 = (*bottom), p1;
+    if (shift_count > (ap_uint<PQ_BIT>)(bottom_L)) {
+    	// bottom_L bit shift
+    	PQ_PUSH_SHIFT_H_1:
+    	for (ap_uint<LOG_PP> k = 0; k < (ap_uint<LOG_PP>)(bottom_L); k++) {
+#pragma HLS LOOP_TRIPCOUNT min=0 max=31
+/** Set!: min=0 max=PP-1 **/
+    		p0 = p0 - 1; // source
+    		p1 = p0 + 1; // destination
+    		pq_nodes[p1] = pq_nodes[p0];
+    	}
+    	shift_count = shift_count - bottom_L;
+    }
+    else {
+    	// shift_count bit shift
+    	PQ_PUSH_SHIFT_H_2:
+    	for (ap_uint<LOG_PP> k = 0; k < (ap_uint<LOG_PP>)(shift_count); k++) {
+#pragma HLS LOOP_TRIPCOUNT min=0 max=31
+/** Set!: min=0 max=PP-1 **/
+    		p0 = p0 - 1; // source
+    		p1 = p0 + 1; // destination
+    		pq_nodes[p1] = pq_nodes[p0];
+    	}
+    	pq_nodes[p0] = ((ap_uint<32>)data << PQ_PRIORITY_WIDTH) | (ap_uint<32>)priority;
+    	*is_empty = false;  return;
+    }
+
+    ap_uint<PQ_BIT-LOG_PP> shift_count_i = shift_count >> LOG_PP;
+    ap_uint<LOG_PP>  shift_count_j = shift_count - (shift_count_i << LOG_PP);
+    // Note: Bit adjustment is necessary
+    // when the values of PP & LOG_PP have been changed.
+
+    ap_uint<PQ_BIT> p[PP+1];
+#pragma HLS ARRAY_PARTITION variable=p complete dim=1
+    p[0] = bottom_H * PP;
+    ap_uint<32> tmp[PP];
+#pragma HLS ARRAY_PARTITION variable=tmp complete dim=1
+    PQ_PUSH_SHIFT_I:
+    for (ap_uint<PQ_BIT-LOG_PP> i = 0; i < (ap_uint<PQ_BIT-LOG_PP>)(shift_count_i); i++) {
+#pragma HLS LOOP_TRIPCOUNT min=0 max=255
+/** Set!: min=0 max=(MAX_PQ)/(PP)-1 **/
+    	p[0] = p[0] - PP;
+    	for (ap_uint<LOG_PP+1> k = 1; k <= (ap_uint<LOG_PP+1>)(PP); k++) {
+#pragma HLS UNROLL
+    		p[k] = p[0] + k;
+    	}
+    	for (ap_uint<LOG_PP+1> k = 1; k <= (ap_uint<LOG_PP+1>)(PP); k++) {
+#pragma HLS UNROLL
+    		tmp[k-1] = pq_nodes[p[k-1]];
+    	}
+    	for (ap_uint<LOG_PP+1> k = 1; k <= (ap_uint<LOG_PP+1>)(PP); k++) {
+#pragma HLS UNROLL
+    		pq_nodes[p[k]] = tmp[k-1];
+    	}
+    }
+    PQ_PUSH_SHIFT_J:
+    for (ap_uint<LOG_PP> j = 0; j < (ap_uint<LOG_PP>)(shift_count_j); j++) {
+#pragma HLS LOOP_TRIPCOUNT min=0 max=31
+/** Set!: min=0 max=PP-1 **/
+    	p[0] = p[0] - 1;
+    	p[1] = p[0] + 1;
+    	pq_nodes[p[1]] = pq_nodes[p[0]];
+    }
+    pq_nodes[p[0]] = ((ap_uint<32>)data << PQ_PRIORITY_WIDTH) | (ap_uint<32>)priority;
+    *is_empty = false;
+}
+
+// Queue pop (Dequeue)
+void pq_pop(ap_uint<32> pq_nodes[MAX_PQ], ap_uint<16> *ret_priority, ap_uint<16> *ret_data, ap_uint<PQ_BIT> *top, ap_uint<PQ_BIT> *bottom, bool *is_empty) {
+#pragma HLS INLINE
+
+    *ret_priority = (ap_uint<16>)(pq_nodes[(*top)] & PQ_PRIORITY_MASK);
+    *ret_data     = (ap_uint<16>)(pq_nodes[(*top)] >> PQ_PRIORITY_WIDTH);
+    (*top)++;
+    if (((*bottom)-(*top)+1) == 0) { *is_empty = true; }
+}

hls_2018/router_02_boardstr/router.hpp

+/**
+ * router.hpp
+ *
+ * for Vivado HLS
+ */
+
+#ifndef __ROUTER_HPP__
+#define __ROUTER_HPP__
+
+#ifdef SOFTWARE
+#include "ap_int.h"
+#else
+#include <ap_int.h>
+#endif
+
+//#define DEBUG_PRINT // for debug
+
+#ifdef DEBUG_PRINT
+using namespace std;
+#endif
+
+// Parameters
+#define MAX_WIDTH   72      // Max of X, Y
+#define BITWIDTH_XY 13
+#define BITMASK_XY  65528   // 1111 1111 1111 1000
+#define MAX_LAYER   8       // Max of Z
+#define BITWIDTH_Z  3
+#define BITMASK_Z   7       // 0000 0000 0000 0111
+
+#define MAX_CELLS	41472    // Max #cells (16bit)
+#define MAX_LINES	1024     // Max #lines (10bit)
+#define MAX_PQ		8192     // Queue size (13bit)
+#define MAX_BUFFER	16384    // Line buffer size (14bit)
+#define CELL_BIT	16
+#define LINE_BIT	10
+#define PQ_BIT		13
+#define BUFF_BIT	14
+
+#define PQ_PRIORITY_WIDTH 16
+#define PQ_PRIORITY_MASK  65535       // 0000 0000 0000 0000 1111 1111 1111 1111
+#define PQ_DATA_WIDTH     16
+#define PQ_DATA_MASK      4294901760  // 1111 1111 1111 1111 0000 0000 0000 0000
+
+#define MAX_WEIGHT	255      // Max weight
+#define BOARDSTR_SIZE 41472      // Size of I/O
+
+#define PP 32		// Parameter for Parallel shifting in queue push
+#define LOG_PP 5	// LOG_PP is log2(PP)
+
+ap_uint<8> new_weight(ap_uint<16> x);
+bool pynqrouter(char boardstr[BOARDSTR_SIZE], char boardstr_high[BOARDSTR_SIZE], ap_uint<32> seed, ap_int<32> *status);
+
+ap_uint<7> abs_uint7(ap_uint<7> a, ap_uint<7> b);
+ap_uint<3> abs_uint3(ap_uint<3> a, ap_uint<3> b);
+ap_uint<BUFF_BIT> search(ap_uint<BUFF_BIT> idx, ap_uint<BUFF_BIT> *n_idx, ap_uint<CELL_BIT> paths[MAX_BUFFER], ap_uint<CELL_BIT> start, ap_uint<CELL_BIT> goal, ap_uint<8> w[MAX_WEIGHT]);
+void pq_push(ap_uint<32> pq_nodes[MAX_PQ], ap_uint<16> priority, ap_uint<16> data, ap_uint<PQ_BIT> *top, ap_uint<PQ_BIT> *bottom, bool *is_empty);
+void pq_pop(ap_uint<32> pq_nodes[MAX_PQ], ap_uint<16> *ret_priority, ap_uint<16> *ret_data, ap_uint<PQ_BIT> *top, ap_uint<PQ_BIT> *bottom, bool *is_empty);
+
+#endif /* __ROUTER_HPP__ */

hls_2018/router_04_boardstr/bitstream/router_design.tcl

+
+################################################################
+# This is a generated script based on design: router_design
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2018.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source router_design_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96:part0:1.0 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name router_design
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:hls:pynqrouter:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.2\
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {1} \
+   CONFIG.NUM_SI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: pynqrouter_0, and set properties
+  set pynqrouter_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:pynqrouter:1.0 pynqrouter_0 ]
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_SLEW {slow} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_SLEW {slow} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_SLEW {slow} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_SLEW {slow} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_SLEW {slow} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_SLEW {slow} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_SLEW {slow} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_SLEW {slow} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_SLEW {slow} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_SLEW {slow} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_SLEW {slow} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_SLEW {slow} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_SLEW {slow} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {525.000000} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000024} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000005} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000005} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {262.500005} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000012} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666667} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000006} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000012} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000010} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000002} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000011} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000010} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000001} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000010} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000005} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999985} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000002} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000005} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000002} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000010} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500004} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000002} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200.000004} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500004} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {200.000004} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {200.000004} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000002} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000002} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000002} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000005} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000005} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {15} \
+   CONFIG.PSU__DDRC__T_RP {15} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|FPD;RCPU_GIC;F9000000;F900FFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9000000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USE__IRQ0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {1} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] [get_bd_intf_pins pynqrouter_0/s_axi_AXI4LS]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM1_FPD [get_bd_intf_pins ps8_0_axi_periph/S01_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM1_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_interconnect_aresetn [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins rst_ps8_0_100M/interconnect_aresetn]
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins ps8_0_axi_periph/S01_ARESETN] [get_bd_pins pynqrouter_0/ap_rst_n] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins ps8_0_axi_periph/S01_ACLK] [get_bd_pins pynqrouter_0/ap_clk] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x00040000 -offset 0xA0000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs pynqrouter_0/s_axi_AXI4LS/Reg] SEG_pynqrouter_0_Reg
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls_2018/router_04_boardstr/router.cpp

@@ -164,13 +164,15 @@ bool pynqrouter(char boardstr[BOARDSTR_SIZE], char boardstr_high[BOARDSTR_SIZE],
     cout << "Rip-up Routing ..." << endl;
 #endif
 
+    ap_uint<LINE_BIT> target = line_num - 1, next_target;
+
     ROUTING:
     for (ap_uint<16> round = 0; round < 32768 /* = (2048 * 16) */; round++) {
 #pragma HLS LOOP_TRIPCOUNT min=1 max=32768
 
         // Target line
-        ap_uint<LINE_BIT> target = round % line_num;
-        ap_uint<LINE_BIT> next_target = target + 1;
+        target = round % line_num;
+        next_target = target + 1;
         if (next_target == line_num) next_target = 0;
 
 #ifdef DEBUG_PRINT
@@ -310,7 +312,7 @@ bool pynqrouter(char boardstr[BOARDSTR_SIZE], char boardstr_high[BOARDSTR_SIZE],
         else {
             p2 = s_idx[i+1];
         }
-        if ((ap_uint<BUFF_BIT>)(p2 - p1) > 8192){
+        if (i == target) {
             p2 = pointer;
         }
         OUTPUT_LINE_PATH:
@@ -474,7 +476,7 @@ void pq_push(ap_uint<32> pq_nodes[MAX_PQ], ap_uint<16> priority, ap_uint<16> dat
     ap_uint<PQ_BIT> p = (*pq_len) >> 1; // parent node
     PQ_PUSH_LOOP:
     while (i > 1 && (ap_uint<16>)(pq_nodes[p] & PQ_PRIORITY_MASK) >= priority) {
-#pragma HLS LOOP_TRIPCOUNT min=0 max=15
+#pragma HLS LOOP_TRIPCOUNT min=0 max=16
 /** Set!: min=0 max=PQ_BIT **/
         pq_nodes[i] = pq_nodes[p];
         i = p;
@@ -497,7 +499,7 @@ void pq_pop(ap_uint<32> pq_nodes[MAX_PQ], ap_uint<16> *ret_priority, ap_uint<16>
 
     PQ_POP_LOOP:
     while (!(i >> (PQ_BIT-1))) { // (2018.08.24) Loop condition fixed
-#pragma HLS LOOP_TRIPCOUNT min=1 max=15
+#pragma HLS LOOP_TRIPCOUNT min=1 max=16
 /** Set!: min=0 max=PQ_BIT **/
         ap_uint<PQ_BIT> c1 = i << 1; // child node(left)
         ap_uint<PQ_BIT> c2 = c1 + 1; // child node(right)

hls_2018/router_04_boardstr/router.hpp

@@ -28,13 +28,13 @@ using namespace std;
 #define BITMASK_Z   7       // 0000 0000 0000 0111
 
 #define MAX_CELLS	41472    // Max #cells (16bit)
-#define MAX_LINES	1024     // Max #lines (10bit)
+#define MAX_LINES	2048     // Max #lines (11bit)
 #define MAX_PQ		65536    // Queue size (16bit)
-#define MAX_BUFFER	16384    // Line buffer size (14bit)
+#define MAX_BUFFER	32768    // Line buffer size (15bit)
 #define CELL_BIT	16
-#define LINE_BIT	10
+#define LINE_BIT	11
 #define PQ_BIT		16
-#define BUFF_BIT	14
+#define BUFF_BIT	15
 
 #define PQ_PRIORITY_WIDTH 16
 #define PQ_PRIORITY_MASK  65535       // 0000 0000 0000 0000 1111 1111 1111 1111

hls_2018/router_05/Makefile

+TARGET = sim
+OBJS = $(CPPS:.cpp=.o)
+CPPS = $(wildcard *.cpp)
+CXX = g++
+CXXFLAGS = -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -DSOFTWARE -DCALCTIME
+
+all: $(TARGET)
+
+$(TARGET): $(OBJS)
+	$(CXX) -O3 -o $@ $(OBJS)
+
+run:
+	python3 ../NLGenerator.py -x 20 -y 20 -z 6 -l 100;\
+	python3 ./gen_boardstr.py Q-20x20x5_100_10.txt |\
+	./$(TARGET) -
+
+
+clean:
+	rm *.o
+	rm $(TARGET)

hls_2018/router_05/Makefile.cygwin

+TARGET = sim
+OBJS = $(CPPS:.cpp=.o)
+CPPS = $(wildcard *.cpp)
+CXX = g++
+CXXFLAGS = -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -DSOFTWARE -DCALCTIME
+
+all: $(TARGET)
+
+$(TARGET): $(OBJS)
+	$(CXX) -O3 -Wl,--stack,33554432 -o $@ $(OBJS)
+
+clean:
+	rm *.o
+	rm $(TARGET)

hls_2018/router_05/ap_int.h

+/*
+ * Copyright 2012 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AESL_AP_SIM_H__
+#define __AESL_AP_SIM_H__
+
+#ifndef __cplusplus
+#error C++ is required to include this header file
+#else
+
+#include "etc/ap_int_sim.h"
+#include "etc/ap_fixed_sim.h"
+
+//Forward declaration
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N> class ap_fixed;
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N> class ap_ufixed;
+template<int _AP_W> class ap_int;
+template<int _AP_W> class ap_uint;
+
+//AP_INT
+//--------------------------------------------------------
+template<int _AP_W>
+class ap_int : public ap_private<_AP_W, true> {
+#ifdef _MSC_VER
+#pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+public:
+    typedef ap_private<_AP_W, true> Base;
+
+    //Constructor
+    INLINE ap_int(): Base() {}
+    template<int _AP_W2>
+    INLINE ap_int(const volatile ap_int<_AP_W2> &op):Base((const ap_private<_AP_W2,true> &)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_int(const ap_int<_AP_W2> &op):Base((const ap_private<_AP_W2,true> &)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_int(const ap_uint<_AP_W2> &op):Base((const ap_private<_AP_W2,false> &)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_int(const volatile ap_uint<_AP_W2> &op):Base((const ap_private<_AP_W2,false> &)(op)) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_int(const ap_range_ref<_AP_W2, _AP_S2>& ref):Base(ref) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_int(const ap_bit_ref<_AP_W2, _AP_S2>& ref):Base(ref) {}
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_int(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref):Base(ref) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                 :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                  :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                 :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                  :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_int(const ap_private<_AP_W2, _AP_S2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+                  _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+                  _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_int(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op):Base(op.to_ap_private()) {}
+
+#define CTOR(TYPE) \
+    INLINE ap_int(TYPE v):Base(v) {}
+    CTOR(bool)
+    CTOR(signed char)
+    CTOR(unsigned char)
+    CTOR(short)
+    CTOR(unsigned short)
+    CTOR(int)
+    CTOR(unsigned int)
+    CTOR(long)
+    CTOR(unsigned long)
+    CTOR(unsigned long long)
+    CTOR(long long)
+    CTOR(float)
+    CTOR(double)
+    CTOR(const char*)
+    CTOR(const std::string&)
+#undef CTOR
+    INLINE ap_int(const char* str, signed char rd):Base(str, rd) {}
+     //Assignment
+     //Another form of "write"
+    INLINE void operator = (const ap_int<_AP_W>& op2) volatile {
+      const_cast<ap_int*>(this)->operator = (op2);
+    }
+
+    INLINE void operator = (const volatile ap_int<_AP_W>& op2) volatile {
+      const_cast<Base*>(this)->operator = (op2);
+    }
+
+    INLINE ap_int<_AP_W>& operator = (const volatile ap_int<_AP_W>& op2) {
+      Base::operator = (const_cast<ap_int<_AP_W>& >(op2));
+        return *this;
+    }
+
+    INLINE ap_int<_AP_W>& operator = (const ap_int<_AP_W>& op2) {
+      Base::operator = ((const ap_private<_AP_W, true>&)op2);
+        return *this;
+    }
+};
+
+//AP_UINT
+//---------------------------------------------------------------
+template<int _AP_W>
+class ap_uint: public ap_private<_AP_W, false> {
+#ifdef _MSC_VER
+#pragma warning( disable : 4521 4522 )
+#endif
+public:
+    typedef ap_private<_AP_W, false> Base;
+    //Constructor
+    INLINE ap_uint(): Base() {}
+  INLINE ap_uint(const ap_uint<_AP_W>& op) :Base(dynamic_cast<const ap_private<_AP_W, false>&>(op)) {}
+  INLINE ap_uint(const volatile ap_uint<_AP_W>& op):Base(dynamic_cast<const volatile ap_private<_AP_W, false>&>(op)){}
+    template<int _AP_W2>
+    INLINE ap_uint(const volatile ap_uint<_AP_W2> &op):Base((const ap_private<_AP_W2, false>&)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_uint(const ap_uint<_AP_W2> &op) : Base((const ap_private<_AP_W2, false>&)(op)){}
+
+    template<int _AP_W2>
+    INLINE ap_uint(const ap_int<_AP_W2> &op) : Base((const ap_private<_AP_W2, true>&)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_uint(const volatile ap_int<_AP_W2> &op) : Base((const ap_private<_AP_W2, false>&)(op)) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_uint(const ap_range_ref<_AP_W2, _AP_S2>& ref):Base(ref) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_uint(const ap_bit_ref<_AP_W2, _AP_S2>& ref):Base(ref) {}
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_uint(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref):Base(ref) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                   :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                   :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                   :Base(op.to_ap_private()) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+                   :Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_uint(const ap_private<_AP_W2, _AP_S2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+                  _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+                  _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_uint(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op):Base(op.to_ap_private()) {}
+
+#define CTOR(TYPE) \
+    INLINE ap_uint(TYPE v):Base(v) {}
+    CTOR(bool)
+    CTOR(signed char)
+    CTOR(unsigned char)
+    CTOR(short)
+    CTOR(unsigned short)
+    CTOR(int)
+    CTOR(unsigned int)
+    CTOR(long)
+    CTOR(unsigned long)
+    CTOR(unsigned long long)
+    CTOR(long long)
+    CTOR(float)
+    CTOR(double)
+    CTOR(const char*)
+    CTOR(const std::string&)
+#undef CTOR
+    INLINE ap_uint(const char* str, signed char rd):Base(str, rd) {}
+     //Assignment
+     //Another form of "write"
+    INLINE void operator = (const ap_uint<_AP_W>& op2) volatile {
+      Base::operator = (op2);
+    }
+
+    INLINE void operator = (const volatile ap_uint<_AP_W>& op2) volatile {
+      Base::operator = (op2);
+    }
+
+    INLINE ap_uint<_AP_W>& operator = (const volatile ap_uint<_AP_W>& op2) {
+      Base::operator = (op2);
+        return *this;
+    }
+
+    INLINE ap_uint<_AP_W>& operator = (const ap_uint<_AP_W>& op2) {
+      Base::operator = ((const ap_private<_AP_W, false>&)(op2));
+        return *this;
+    }
+};
+
+#define ap_bigint ap_int
+#define ap_biguint ap_uint
+
+//AP_FIXED
+//---------------------------------------------------------------------
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q = AP_TRN,
+         ap_o_mode _AP_O = AP_WRAP, int _AP_N = 0>
+class ap_fixed: public ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> {
+#ifdef _MSC_VER
+#pragma warning( disable : 4521 4522 )
+#endif
+public:
+    typedef ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> Base;
+     //Constructor
+    INLINE ap_fixed():Base() {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const ap_fixed<_AP_W2, _AP_I2,  _AP_Q2, _AP_O2,
+                    _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2,
+                    _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                   false, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_fixed(const ap_int<_AP_W2>& op):
+                   Base(ap_private<_AP_W2, true>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_fixed(const ap_uint<_AP_W2>& op):Base(ap_private<_AP_W2, false>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const volatile ap_fixed<_AP_W2, _AP_I2,  _AP_Q2, _AP_O2,
+                    _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                    true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2,
+                    _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                   false, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_fixed(const volatile ap_int<_AP_W2>& op):
+                   Base(ap_private<_AP_W2, true>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_fixed(const volatile ap_uint<_AP_W2>& op):Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed(const ap_bit_ref<_AP_W2, _AP_S2>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed(const ap_range_ref<_AP_W2, _AP_S2>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_fixed(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed(const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed(const ap_private<_AP_W2, _AP_S2>& op):Base(op) {}
+
+ #define CTOR(TYPE) \
+    INLINE ap_fixed(TYPE v):Base(v) {}
+    CTOR(bool)
+    CTOR(signed char)
+    CTOR(unsigned char)
+    CTOR(short)
+    CTOR(unsigned short)
+    CTOR(int)
+    CTOR(unsigned int)
+    CTOR(long)
+    CTOR(unsigned long)
+    CTOR(unsigned long long)
+    CTOR(long long)
+    CTOR(float)
+    CTOR(double)
+    CTOR(const char*)
+    CTOR(const std::string&)
+#undef CTOR
+    INLINE ap_fixed(const char* str, signed char rd):Base(str, rd) {}
+
+    //Assignment
+    INLINE ap_fixed& operator = (const ap_fixed<_AP_W, _AP_I,
+                    _AP_Q, _AP_O, _AP_N>& op) {
+      Base::operator = (op);
+        return *this;
+    }
+
+  INLINE ap_fixed& operator = (const volatile ap_fixed<_AP_W, _AP_I,
+                    _AP_Q, _AP_O, _AP_N>& op) {
+        Base::operator = (op);
+        return *this;
+    }
+};
+
+//AP_ UFIXED
+//--- ----------------------------------------------------------------
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q = AP_TRN,
+         ap_o_mode _AP_O = AP_WRAP, int _AP_N = 0>
+class ap_ufixed : public ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> {
+#ifdef _MSC_VER
+#pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+public:
+    typedef ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> Base;
+
+     //Constructor
+    INLINE ap_ufixed():Base() {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2,
+                     _AP_O2, _AP_N2>& op) : Base(ap_fixed_base<_AP_W2,
+                     _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const ap_ufixed<_AP_W2, _AP_I2,  _AP_Q2,
+                     _AP_O2, _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                      false, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_ufixed(const ap_int<_AP_W2>& op):
+      Base((const ap_private<_AP_W2, true>&)(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_ufixed(const ap_uint<_AP_W2>& op):
+      Base((const ap_private<_AP_W2, false>&)(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2,
+                     _AP_O2, _AP_N2>& op) : Base(ap_fixed_base<_AP_W2,
+                     _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const volatile ap_ufixed<_AP_W2, _AP_I2,  _AP_Q2,
+                     _AP_O2, _AP_N2>& op): Base(ap_fixed_base<_AP_W2, _AP_I2,
+                      false, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_ufixed(const volatile ap_int<_AP_W2>& op):
+                     Base(ap_private<_AP_W2, true>(op)) {}
+
+    template<int _AP_W2>
+    INLINE ap_ufixed(const volatile ap_uint<_AP_W2>& op):
+                     Base(ap_private<_AP_W2, false>(op)) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+                     _AP_O2, _AP_N2>& op):Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_ufixed(const ap_bit_ref<_AP_W2, _AP_S2>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_ufixed(const ap_range_ref<_AP_W2, _AP_S2>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_ufixed(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op):
+                   Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_ufixed(const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                    _AP_Q2, _AP_O2, _AP_N2>& op): Base(op) {}
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_ufixed(const ap_private<_AP_W2, _AP_S2>& op):Base(op) {}
+
+ #define CTOR(TYPE) \
+    INLINE ap_ufixed(TYPE v):Base(v) {}
+    CTOR(bool)
+    CTOR(signed char)
+    CTOR(unsigned char)
+    CTOR(short)
+    CTOR(unsigned short)
+    CTOR(int)
+    CTOR(unsigned int)
+    CTOR(long)
+    CTOR(unsigned long)
+    CTOR(unsigned long long)
+    CTOR(long long)
+    CTOR(float)
+    CTOR(double)
+    CTOR(const char*)
+    CTOR(const std::string&)
+#undef CTOR
+    INLINE ap_ufixed(const char* str, signed char rd):Base(str, rd) {}
+
+    //Assignment
+    INLINE ap_ufixed& operator = (const ap_ufixed<_AP_W, _AP_I,
+                    _AP_Q, _AP_O, _AP_N>& op) {
+      Base::operator = (op);
+        return *this;
+    }
+
+    INLINE ap_ufixed& operator = (const volatile ap_ufixed<_AP_W, _AP_I,
+                    _AP_Q, _AP_O, _AP_N>& op) {
+        Base::V = const_cast<ap_ufixed&>(op);
+        return *this;
+    }
+};
+
+#if defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED)
+template<int _AP_W>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_int<_AP_W> &op,
+                     const std::string &name) {
+    if (tf)
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+
+template<int _AP_W>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_uint<_AP_W> &op,
+                     const std::string &name) {
+    if (tf)
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N >&op, const std::string &name) {
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+
+template<int _AP_W, int _AP_I, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N >&op, const std::string &name) {
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+#endif /* #if defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED) */
+#endif /* #ifndef __cplusplus */
+#endif /* #ifndef __AESL_AP_SIM_H__ */
\ No newline at end of file

hls_2018/router_05/etc/ap_fixed_sim.h

+/*
+ * Copyright 2012 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AESL_GCC_AP_FIXED_H__
+#define __AESL_GCC_AP_FIXED_H__
+
+#ifndef __cplusplus
+    #error C++ is required to include this header file
+#endif /* #ifndef __cplusplus */
+
+
+#include <math.h>
+#ifndef __AESL_APDT_IN_SCFLOW__
+    #include "etc/ap_int_sim.h"
+#else
+    #include "../etc/ap_private.h"
+#endif /* #ifndef __AESL_APDT_IN_SCFLOW__ */
+
+#define FLOAT_MAN 23
+#define FLOAT_EXP 8
+#define DOUBLE_MAN 52
+#define DOUBLE_EXP 11
+// #define DOUBLE_MAN_MASK (~0ULL >> (64-DOUBLE_MAN-2))
+#define DOUBLE_MAN_MASK 0x3fffffffffffffULL
+#define BIAS(e) ((1ULL<<(e-1))-1)
+#define FLOAT_BIAS BIAS(FLOAT_EXP)
+#define DOUBLE_BIAS BIAS(DOUBLE_EXP)
+
+/// Forward declaration.
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> struct ap_fixed_base;
+
+///Proxy class, which allows bit selection  to be used as both rvalue(for reading) and
+//lvalue(for writing)
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+struct af_bit_ref {
+#ifdef _MSC_VER
+    #pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+    ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& d_bv;
+    int d_index;
+public:
+    INLINE af_bit_ref(const af_bit_ref<_AP_W, _AP_I, _AP_S,
+                                        _AP_Q, _AP_O, _AP_N>& ref):
+           d_bv(ref.d_bv), d_index(ref.d_index) {}
+
+    INLINE af_bit_ref(ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>* bv, int index=0):
+    d_bv(*bv),d_index(index) {}
+
+    INLINE operator bool() const {
+        return d_bv.V[d_index];
+    }
+
+    INLINE af_bit_ref& operator=(unsigned long long val) {
+        if (val)
+            d_bv.V.set(d_index);
+        else
+            d_bv.V.clear(d_index);
+        return *this;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE af_bit_ref& operator =(const ap_private<_AP_W2,_AP_S2>& val) {
+        return operator=(val!=0);
+    }
+
+    INLINE af_bit_ref& operator =(const af_bit_ref<_AP_W, _AP_I, _AP_S,
+                                        _AP_Q, _AP_O, _AP_N>& val) {
+        return operator=((unsigned long long)(bool)val);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE af_bit_ref operator=(const af_bit_ref<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& val) {
+        return operator=((unsigned long long)(bool)val);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE af_bit_ref& operator = ( const ap_bit_ref<_AP_W2, _AP_S2> &val) {
+        return operator =((unsigned long long) (bool) val);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE af_bit_ref& operator = ( const ap_range_ref<_AP_W2,_AP_S2>& val) {
+        return operator =((const ap_private<_AP_W2, false>) val);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE af_bit_ref& operator= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((const ap_private<_AP_W2, false>)(val));
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE af_bit_ref& operator= (const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) {
+        return operator=((const ap_private<_AP_W2 + _AP_W3, false>)(val));
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<1, af_bit_ref, _AP_W2, ap_private<_AP_W2, _AP_S2> >
+    operator, (ap_private<_AP_W2, _AP_S2>& op) {
+        return ap_concat_ref<1, af_bit_ref, _AP_W2,
+               ap_private<_AP_W2, _AP_S2> >(*this, op);
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<1, af_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >
+    operator, (const ap_bit_ref<_AP_W2, _AP_S2> &op) {
+        return ap_concat_ref<1, af_bit_ref, 1,
+               ap_bit_ref<_AP_W2, _AP_S2> >(*this,
+               const_cast<ap_bit_ref<_AP_W2, _AP_S2>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<1, af_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+    operator, (const ap_range_ref<_AP_W2, _AP_S2> &op) {
+        return ap_concat_ref<1, af_bit_ref, _AP_W2,
+               ap_range_ref<_AP_W2, _AP_S2> >(*this,
+               const_cast<ap_range_ref<_AP_W2, _AP_S2>& >(op));
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_concat_ref<1, af_bit_ref, _AP_W2 + _AP_W3,
+                        ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+    operator, (const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &op) {
+        return ap_concat_ref<1, af_bit_ref, _AP_W2 + _AP_W3,
+                 ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this,
+                 const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_concat_ref<1, af_bit_ref, _AP_W2,
+             af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &op) {
+       return ap_concat_ref<1, af_bit_ref,  _AP_W2,
+             af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+             _AP_N2> >(*this, const_cast<af_range_ref<_AP_W2, _AP_I2,
+             _AP_S2, _AP_Q2, _AP_O2,_AP_N2>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_concat_ref<1, af_bit_ref, 1,
+             af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &op) {
+       return ap_concat_ref<1, af_bit_ref, 1,
+             af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+             const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+              _AP_O2, _AP_N2>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator == (const af_bit_ref<_AP_W2, _AP_I2,
+                             _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+        return get() == op.get();
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator != (const af_bit_ref<_AP_W2, _AP_I2,
+                             _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+        return get() != op.get();
+    }
+
+    INLINE bool operator ~ () const {
+        bool bit = (d_bv.V)[d_index];
+        return bit ? false : true;
+    }
+
+    INLINE int length() const {
+        return 1;
+    }
+
+    INLINE bool get() {
+        return d_bv.V[d_index];
+    }
+
+    INLINE bool get() const {
+        return d_bv.V[d_index];
+    }
+
+    INLINE std::string to_string() const {
+        return d_bv.V[d_index] ? "1" : "0";
+    }
+};
+
+///Range(slice)  reference
+//------------------------------------------------------------
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+struct af_range_ref {
+#ifdef _MSC_VER
+    #pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &d_bv;
+    int l_index;
+    int h_index;
+
+public:
+    INLINE af_range_ref(const af_range_ref<_AP_W, _AP_I, _AP_S,
+                                        _AP_Q, _AP_O, _AP_N>& ref):
+           d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {}
+
+    INLINE af_range_ref(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>* bv, int h, int l):
+        d_bv(*bv),l_index(l),h_index(h) {
+        //if (h < l)
+          // fprintf(stderr,
+           //"Warning! The bits selected will be returned in reverse order\n");
+    }
+
+    INLINE operator ap_private<_AP_W, false> () const {
+        if (h_index >= l_index) {
+          ap_private<_AP_W, false> val(d_bv.V);
+          ap_private<_AP_W,false> mask(-1);
+          mask>>=_AP_W-(h_index-l_index+1);
+          val>>=l_index;
+          return val&=mask;
+        } else {
+          ap_private<_AP_W, false> val = 0;
+          for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+            if ((d_bv.V)[j]) val.set(i);
+          return val;
+        }
+    }
+
+    INLINE operator unsigned long long() const {
+        return get().to_uint64();
+    }
+
+    template<int _AP_W2,bool _AP_S2>
+    INLINE af_range_ref& operator =(const ap_private<_AP_W2,_AP_S2>& val) {
+      ap_private<_AP_W, false> vval= ap_private<_AP_W, false>(val);
+        if (l_index > h_index) {
+            for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+                    vval[i]? d_bv.V.set(j):d_bv.V.clear(j);
+        } else {
+          ap_private<_AP_W,false> mask(-1);
+            if (l_index>0) {
+                mask<<=l_index;
+                vval<<=l_index;
+            }
+            if (h_index<_AP_W-1) {
+              ap_private<_AP_W,false> mask2(-1);
+              mask2>>=_AP_W-h_index-1;
+              mask&=mask2;
+              vval&=mask2;
+            }
+            mask.flip();
+            d_bv.V &= mask;
+            d_bv.V |= vval;
+        }
+        return *this;
+    }
+
+    INLINE af_range_ref& operator = (unsigned long long val) {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template<int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+    INLINE af_range_ref& operator =
+        (const ap_concat_ref <_AP_W3, _AP_T3, _AP_W4, _AP_T4>& val) {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref& operator =(const ap_bit_ref<_AP_W3, _AP_S3>& val) {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref& operator =(const ap_range_ref<_AP_W3,_AP_S3>& val) {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator =(tmpVal);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+             ap_o_mode _AP_O2, int _AP_N2>
+    INLINE af_range_ref& operator= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+        const ap_private<_AP_W2, false> tmp= val.get();
+        return operator = (tmp);
+    }
+
+    INLINE af_range_ref& operator= (const af_range_ref<_AP_W, _AP_I, _AP_S,
+                                        _AP_Q, _AP_O, _AP_N>& val) {
+        const ap_private<_AP_W, false> tmp= val.get();
+        return operator = (tmp);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE af_range_ref& operator= (const ap_fixed_base<_AP_W2,
+                          _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=(val.to_ap_private());
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator == (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs==rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator != (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs!=rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator > (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator >= (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>=rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator < (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<rhs;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator <= (const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<=rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator == (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs==rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator != (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs!=rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator > (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator >= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>=rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator < (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<rhs;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator <= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<=rhs;
+    }
+
+    template<int _AP_W2>
+    INLINE void set(const ap_private<_AP_W2,false>& val) {
+        ap_private<_AP_W,_AP_S> vval=val;
+        if (l_index>h_index) {
+            for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+                    vval[i]? d_bv.V.set(j):d_bv.V.clear(j);
+        } else {
+          ap_private<_AP_W,_AP_S> mask(-1);
+            if (l_index>0) {
+                ap_private<_AP_W,false> mask1(-1);
+                mask1>>=_AP_W-l_index;
+                mask1.flip();
+                mask=mask1;
+                //vval&=mask1;
+                vval<<=l_index;
+            }
+            if (h_index<_AP_W-1) {
+                ap_private<_AP_W,false> mask2(-1);
+                mask2<<=h_index+1;
+                mask2.flip();
+                mask&=mask2;
+                vval&=mask2;
+            }
+            mask.flip();
+            d_bv&=mask;
+            d_bv|=vval;
+        }
+
+    }
+
+    INLINE ap_private<_AP_W,false> get() const {
+        if (h_index<l_index) {
+          ap_private<_AP_W, false> val(0);
+          for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+            if ((d_bv.V)[j]) val.set(i);
+          return val;
+        } else {
+          ap_private<_AP_W, false> val = ap_private<_AP_W,false>(d_bv.V);
+          val>>= l_index;
+          if (h_index<_AP_W-1)
+            {
+              ap_private<_AP_W,false> mask(-1);
+              mask>>=_AP_W-(h_index-l_index+1);
+              val&=mask;
+            }
+          return val;
+        }
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2, ap_private<_AP_W2, _AP_S2> >
+    operator, (ap_private<_AP_W2, _AP_S2>& op) {
+        return ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+               ap_private<_AP_W2, _AP_S2> >(*this, op);
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >
+    operator, (const ap_bit_ref<_AP_W2, _AP_S2> &op) {
+        return ap_concat_ref<_AP_W, af_range_ref, 1,
+               ap_bit_ref<_AP_W2, _AP_S2> >(*this,
+               const_cast<ap_bit_ref<_AP_W2, _AP_S2>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_S2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+    operator, (const ap_range_ref<_AP_W2, _AP_S2> &op) {
+        return ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+               ap_range_ref<_AP_W2, _AP_S2> >(*this,
+               const_cast<ap_range_ref<_AP_W2, _AP_S2>& >(op));
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2 + _AP_W3,
+                        ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+    operator, (const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &op) {
+        return ap_concat_ref<_AP_W, af_range_ref, _AP_W2 + _AP_W3,
+                 ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this,
+                 const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3,
+                  _AP_T3>& >(op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+             af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &op) {
+       return ap_concat_ref<_AP_W, af_range_ref,  _AP_W2,
+             af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+             const_cast<af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2,
+             _AP_N2>& > (op));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_concat_ref<_AP_W, af_range_ref, 1,
+             af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &op) {
+       return ap_concat_ref<_AP_W, af_range_ref, 1,
+             af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+             const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+             _AP_O2, _AP_N2>& >(op));
+    }
+
+    INLINE int length() const {
+        return h_index>=l_index?h_index-l_index+1:l_index-h_index+1;
+    }
+
+    INLINE int to_int() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_int();
+    }
+
+    INLINE unsigned int to_uint() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_uint();
+    }
+
+    INLINE long to_long() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_long();
+    }
+
+    INLINE unsigned long to_ulong() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_ulong();
+    }
+
+    INLINE ap_slong to_int64() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_int64();
+    }
+
+    INLINE ap_ulong to_uint64() const {
+        ap_private<_AP_W,false> val=get();
+        return val.to_uint64();
+    }
+
+    INLINE std::string to_string(uint8_t radix) const {
+        return get().to_string(radix);
+    }
+
+};
+
+//-----------------------------------------------------------------------------
+///ap_fixed_base: AutoPilot fixed point
+//-----------------------------------------------------------------------------
+template<int _AP_W, int _AP_I, bool _AP_S=true, ap_q_mode _AP_Q=AP_TRN,
+         ap_o_mode _AP_O=AP_WRAP, int _AP_N=0>
+struct ap_fixed_base {
+#ifdef _MSC_VER
+    #pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+public:
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> friend struct
+ap_fixed_base;
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> friend struct
+af_bit_ref;
+
+    INLINE void overflow_adjust(bool underflow, bool overflow,
+                                bool lD, bool sign) {
+        if (!overflow && !underflow) return;
+        switch (_AP_O) {
+            case AP_WRAP:
+                if (_AP_N == 0)
+                    return;
+                if (_AP_S) {
+                    //signed SC_WRAP
+                    //n_bits == 1;
+                    if (_AP_N > 1) {
+                        ap_private<_AP_W, _AP_S>  mask(-1);
+                        if (_AP_N >= _AP_W) mask = 0;
+                        else mask.lshr(_AP_N);
+                        if (sign)
+                            V &= mask;
+                        else
+                            V |= ~mask;
+                    }
+                    sign ? V.set(_AP_W - 1) : V.clear(_AP_W - 1);
+                } else {
+                    //unsigned SC_WRAP
+                    ap_private<_AP_W, _AP_S> mask(-1);
+                    if (_AP_N >= _AP_W) mask = 0;
+                    else mask.lshr(_AP_N);
+                    mask.flip();
+                    V |= mask;
+                }
+                break;
+            case AP_SAT_ZERO:
+                V.clear();
+                break;
+            case AP_WRAP_SM:
+                {
+                bool Ro = ap_private_ops::get<_AP_W, _AP_S, _AP_W -1>(V); // V[_AP_W -1];
+                if (_AP_N == 0) {
+                    if (lD != Ro) {
+                        V.flip();
+                        lD ? ap_private_ops::set<_AP_W, _AP_S, _AP_W - 1>(V) :
+                            ap_private_ops::clear<_AP_W, _AP_S, _AP_W - 1>(V);
+                    }
+                } else {
+                    if (_AP_N == 1 && sign != Ro) {
+                        V.flip();
+                    } else if (_AP_N > 1) {
+                        bool lNo = ap_private_ops::get<_AP_W, _AP_S, _AP_W - _AP_N> (V); // V[_AP_W - _AP_N];
+                        if (lNo == sign)
+                            V.flip();
+                        ap_private<_AP_W, false> mask(-1);
+                        if (_AP_N >= _AP_W) mask = 0;
+                        else mask.lshr(_AP_N);
+                        if (sign)
+                            V &= mask;
+                        else
+                            V |= mask.flip();
+                        sign ? ap_private_ops::set<_AP_W, _AP_S, _AP_W - 1>(V) : ap_private_ops::clear<_AP_W, _AP_S, _AP_W - 1>(V);
+                    }
+                }
+                }
+                break;
+            default:
+                if (_AP_S) {
+                    if (overflow) {
+                        V.set(); ap_private_ops::clear<_AP_W, _AP_S, _AP_W-1>(V);
+                    } else if (underflow) {
+                        V.clear();
+                        ap_private_ops::set<_AP_W, _AP_S, _AP_W-1>(V);
+                        if (_AP_O == AP_SAT_SYM)
+                            ap_private_ops::set<_AP_W, _AP_S, 0>(V);
+                    }
+                } else {
+                    if (overflow)
+                        V.set();
+                    else if (underflow)
+                        V.clear();
+                }
+        }
+    }
+
+    INLINE bool quantization_adjust(bool qb, bool r, bool s) {
+    	bool carry=ap_private_ops::get<_AP_W, _AP_S, _AP_W-1>(V);
+    	switch (_AP_Q) {
+    	    case AP_TRN:
+    		return false;
+    	    case AP_RND_ZERO:
+    		qb &= s || r;
+    		break;
+    	    case AP_RND_MIN_INF:
+    		qb &= r;
+    		break;
+    	    case AP_RND_INF:
+    		qb &= !s || r;
+    		break;
+    	    case AP_RND_CONV:
+    		qb &= ap_private_ops::get<_AP_W, _AP_S, 0>(V) || r;
+    		break;
+    	    case AP_TRN_ZERO:
+    		qb = s && ( qb || r );
+    		break;
+    	    default:;
+
+    	}
+    	if (qb) ++V;
+    	//only when old V[_AP_W-1]==1 && new V[_AP_W-1]==0
+    	return carry && !(ap_private_ops::get<_AP_W, _AP_S, _AP_W-1>(V)); //(!V[_AP_W-1]);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2>
+    struct RType {
+        enum {
+            _AP_F=_AP_W-_AP_I,
+            F2=_AP_W2-_AP_I2,
+            mult_w = _AP_W+_AP_W2,
+            mult_i = _AP_I+_AP_I2,
+            mult_s = _AP_S||_AP_S2,
+            plus_w = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+1+AP_MAX(_AP_F,F2),
+            plus_i = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+1,
+            plus_s = _AP_S||_AP_S2,
+            minus_w = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+1+AP_MAX(_AP_F,F2),
+            minus_i = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+1,
+            minus_s = true,
+#ifndef __SC_COMPATIBLE__
+            div_w = _AP_W + AP_MAX(_AP_W2 - _AP_I2, 0) + _AP_S2,
+#else
+            div_w = _AP_W + AP_MAX(_AP_W2 - _AP_I2, 0) + _AP_S2 + AP_MAX(_AP_I2, 0),
+#endif /* #ifndef __SC_COMPATIBLE__ */
+            div_i = _AP_I + (_AP_W2-_AP_I2) + _AP_S2,
+            div_s = _AP_S||_AP_S2,
+            logic_w = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2))+AP_MAX(_AP_F,F2),
+            logic_i = AP_MAX(_AP_I+(_AP_S2&&!_AP_S),_AP_I2+(_AP_S&&!_AP_S2)),
+            logic_s = _AP_S||_AP_S2
+        };
+
+        typedef ap_fixed_base<mult_w, mult_i, mult_s> mult;
+        typedef ap_fixed_base<plus_w, plus_i, plus_s> plus;
+        typedef ap_fixed_base<minus_w, minus_i, minus_s> minus;
+        typedef ap_fixed_base<logic_w, logic_i, logic_s> logic;
+        typedef ap_fixed_base<div_w, div_i, div_s> div;
+        typedef ap_fixed_base<_AP_W, _AP_I, _AP_S> arg1;
+    };
+    INLINE void report() {
+#if 0
+        if (_AP_W > 1024 && _AP_W <= 4096) {
+            fprintf(stderr, "[W] W=%d is out of bound (1<=W<=1024):"
+                            " for synthesis, please define macro AP_INT_TYPE_EXT(N) to"
+                            " extend the valid range.\n", _AP_W);
+        } else
+#endif /* #if 0 */
+        if (_AP_W > MAX_MODE(AP_INT_MAX_W) * 1024) {
+            fprintf(stderr, "[E] ap_%sfixed<%d, ...>: Bitwidth exceeds the "
+                   "default max value %d. Please use macro "
+                   "AP_INT_MAX_W to set a larger max value.\n",
+                            _AP_S?"":"u", _AP_W,
+                            MAX_MODE(AP_INT_MAX_W) * 1024);
+            exit(1);
+        }
+    }
+
+    /// Constructors.
+    // -------------------------------------------------------------------------
+#if 0
+    #ifdef __SC_COMPATIBLE__
+    INLINE ap_fixed_base():V(uint32_t(_AP_W), uint64_t(0)) {}
+    #else
+    INLINE ap_fixed_base():V(uint32_t(_AP_W)) {}
+    #endif /* #ifdef __SC_COMPATIBLE__ */
+#else
+    INLINE ap_fixed_base():V(0) {}
+#endif /* #if 0 */
+    //  INLINE ap_fixed_base():V() {}
+    //  INLINE  explicit ap_fixed_base(const ap_private<_AP_W+_AP_I, _AP_S>& _V):V(_V) {}
+    INLINE ap_fixed_base(const ap_fixed_base& op):V(op.V) {}
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed_base(const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op):V(0) {
+	enum {N2=_AP_W2,_AP_F=_AP_W-_AP_I,F2=_AP_W2-_AP_I2,QUAN_INC=F2>_AP_F && !(_AP_Q==AP_TRN ||
+		(_AP_Q==AP_TRN_ZERO && !_AP_S2))};
+	if (!op) return;
+	bool carry=false;
+	//handle quantization
+	enum { sh_amt =(F2>_AP_F)?F2-_AP_F:_AP_F-F2};
+	const ap_private<_AP_W2, _AP_S2>& val = op.V;
+	bool neg_src=val.isNegative();
+	if (F2==_AP_F)
+	    V=val;
+
+	else if (F2>_AP_F) {
+	    if (sh_amt >= _AP_W2)
+		V = neg_src ? -1 : 0;
+	    else
+		V = _AP_S2?val.ashr(sh_amt):val.lshr(sh_amt);
+	    if (_AP_Q!=AP_TRN && !(_AP_Q==AP_TRN_ZERO && !_AP_S2)) {
+		bool qb = false;
+		if (F2-_AP_F>_AP_W2)
+		    qb = neg_src;
+		else
+		    qb = ap_private_ops::get<_AP_W2, _AP_S2, F2-_AP_F-1>(val);
+
+		bool r=false;
+		enum { pos3 = F2-_AP_F-2};
+		if (pos3>=_AP_W2-1)
+		    r=val!=0;
+		else if (pos3>=0)
+		r = (val<<(_AP_W2-1-pos3))!=0;
+		carry = quantization_adjust(qb,r,neg_src);
+	    }
+	} else { //no quantization
+	    if (sh_amt < _AP_W) {
+		V=val;
+		V <<= sh_amt;
+	    }
+	}
+	//hanle overflow/underflow
+	if ((_AP_O!=AP_WRAP || _AP_N != 0) &&
+		((!_AP_S && _AP_S2) || _AP_I-_AP_S <
+		 _AP_I2 - _AP_S2 + (QUAN_INC|| (_AP_S2 &&
+		     _AP_O==AP_SAT_SYM)))) {//saturation
+	    bool deleted_zeros = _AP_S2?true:!carry,
+		 deleted_ones = true;
+	    bool lD=(_AP_I2>_AP_I && _AP_W2-_AP_I2+_AP_I>=0) &&
+		ap_private_ops::get<_AP_W2, _AP_S2, _AP_W2-_AP_I2+_AP_I>(val);
+	    enum { pos1=F2-_AP_F+_AP_W, pos2=F2-_AP_F+_AP_W+1};
+	    if (pos1 < _AP_W2) {
+		bool Range1_all_ones= true;
+		bool Range1_all_zeros= true;
+		if (pos1 >= 0) {
+		    enum { __W = (_AP_W2-pos1) > 0 ? (_AP_W2-pos1) : 1 };
+		    const ap_private<__W, _AP_S2> Range1=ap_private<__W, _AP_S2>(val.lshr(pos1));
+		    Range1_all_ones=Range1.isAllOnesValue();
+		    Range1_all_zeros=Range1.isMinValue();
+		} else {
+		    Range1_all_ones=false;
+		    Range1_all_zeros=val.isMinValue();
+		}
+		bool Range2_all_ones=true;
+		if (pos2<_AP_W2 && pos2>=0) {
+		    enum { __W = (_AP_W2-pos2)>0 ? (_AP_W2-pos2) : 1};
+		    ap_private<__W, true> Range2=ap_private<__W, true>(val.lshr(pos2));
+		    Range2_all_ones=Range2.isAllOnesValue();
+		} else if (pos2<0)
+		    Range2_all_ones=false;
+
+		deleted_zeros=deleted_zeros && (carry?Range1_all_ones:Range1_all_zeros);
+		deleted_ones=carry?Range2_all_ones&&(F2-_AP_F+_AP_W<0||!lD)
+		    :Range1_all_ones;
+		neg_src= neg_src&&!(carry && Range1_all_ones);
+	    } else
+		neg_src = neg_src && V[_AP_W-1];
+
+	    bool neg_trg= V.isNegative();
+	    bool overflow=(neg_trg||!deleted_zeros) && !val.isNegative();
+	    bool underflow=(!neg_trg||!deleted_ones)&&neg_src;
+	    //printf("neg_src = %d, neg_trg = %d, deleted_zeros = %d,
+	    //         deleted_ones = %d, overflow = %d, underflow = %d\n",
+	    //         neg_src, neg_trg, deleted_zeros, deleted_ones,
+	    //         overflow, underflow);
+	    if (_AP_O==AP_SAT_SYM && _AP_S2 && _AP_S)
+		underflow |= neg_src && (_AP_W>1?V.isMinSignedValue():true);
+	    overflow_adjust(underflow, overflow, lD, neg_src);
+	}
+	report();
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed_base(const volatile ap_fixed_base<_AP_W2,_AP_I2,
+		_AP_S2,_AP_Q2,_AP_O2, _AP_N2> &op) : V(op.V) {
+	*this = const_cast<ap_fixed_base<_AP_W2,_AP_I2,
+	_AP_S2,_AP_Q2,_AP_O2, _AP_N2>&>(op);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed_base(const ap_private<_AP_W2,_AP_S2>& op) {
+	ap_fixed_base<_AP_W2,_AP_W2,_AP_S2> f_op;
+	f_op.V=op;
+	*this = f_op;
+    }
+
+    INLINE ap_fixed_base(bool b) {
+	*this=(ap_private<1,false>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(char b) {
+	*this=(ap_private<8,false>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(signed char b) {
+	*this=(ap_private<8,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned char b) {
+	*this=(ap_private<8,false>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(signed short b) {
+	*this=(ap_private<16,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned short b) {
+	*this=(ap_private<16,false>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(signed int b) {
+	*this=(ap_private<32,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned int b) {
+	*this=(ap_private<32,false>)b;
+	report();
+    }
+# if defined __x86_64__
+    INLINE ap_fixed_base(signed long b) {
+	*this=(ap_private<64,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned long  b) {
+	*this=(ap_private<64,false>)b;
+	report();
+    }
+# else
+    INLINE ap_fixed_base(signed long  b) {
+	*this=(ap_private<32,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(unsigned long  b) {
+	*this=(ap_private<32,false>)b;
+	report();
+    }
+# endif
+
+    INLINE ap_fixed_base(ap_slong b) {
+	*this=(ap_private<64,true>)b;
+	report();
+    }
+
+    INLINE ap_fixed_base(ap_ulong b) {
+	*this=(ap_private<64,false>)b;
+	report();
+    }
+
+#if 1
+    INLINE ap_fixed_base(const char* val):V(0) {
+         ap_private<_AP_W, _AP_S> Tmp(val);
+         V = Tmp;
+    }
+
+    INLINE  ap_fixed_base(const char* val, signed char rd): V(0) {
+         ap_private<_AP_W, _AP_S> Tmp(val, rd);
+         V = Tmp;
+    }
+
+#endif
+
+    INLINE ap_fixed_base(const std::string& val) {
+        ap_private<_AP_W, _AP_S> Tmp(val, 2);
+        V = Tmp;
+        report();
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed_base(const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+        *this = ((bool)op);
+        report();
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_fixed_base(const ap_range_ref<_AP_W2, _AP_S2>& op) {
+	*this = ap_private<_AP_W2, _AP_S2>(op);
+	report();
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_fixed_base(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op) {
+	*this = ((const ap_private<_AP_W2 + _AP_W3, false>&)(op));
+	report();
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed_base(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+         *this = (bool(op));
+        report();
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_fixed_base(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+        *this = (ap_private<_AP_W2, false>(op));
+        report();
+    }
+
+    //helper function
+    INLINE unsigned long long doubleToRawBits(double pf)const {
+        union {
+            unsigned long long __L;
+            double __D;
+        }LD;
+        LD.__D=pf;
+        return LD.__L;
+    }
+
+
+    INLINE double rawBitsToDouble(unsigned long long pi) const {
+        union {
+            unsigned long long __L;
+            double __D;
+        }LD;
+        LD.__L=pi;
+        return LD.__D;
+    }
+
+    INLINE float rawBitsToFloat(uint32_t pi) const {
+        union {
+            uint32_t __L;
+            float __D;
+        }LD;
+        LD.__L = pi;
+        return LD.__D;
+    }
+
+    INLINE ap_fixed_base(double d):V(0) {
+	if (!d) return;
+	const bool isneg=d<0;
+
+	const uint64_t ireg=doubleToRawBits(isneg?-d:d);
+	if ((ireg&0x7fffffffffffffffULL)!=0) {
+	    const int32_t exp=(((ireg)>>DOUBLE_MAN)&0x07ff)-DOUBLE_BIAS;
+	    ap_private<DOUBLE_MAN+2, true> man = ireg & DOUBLE_MAN_MASK;
+	    man.clear(DOUBLE_MAN+1);
+	    man.set(DOUBLE_MAN);
+	    if (isneg) {
+		man.flip();
+                man++;
+            }
+
+	    enum {_AP_S2=true,  _AP_W2=DOUBLE_MAN+2,_AP_F=_AP_W -_AP_I };
+	    const int _AP_I2=exp+2;
+            const int F2=_AP_W2-_AP_I2;
+	    const bool QUAN_INC=F2>_AP_F && !(_AP_Q==AP_TRN || (_AP_Q==AP_TRN_ZERO &&
+		    !_AP_S2));
+	    bool carry=false;
+	    //handle quantization
+	    const unsigned sh_amt=abs(F2-_AP_F); // sh_amt = F2>_AP_F ? F2 -_AP_F : _AP_F-F2;
+	    if (F2==_AP_F )
+		V=man;
+	    else if (F2>_AP_F) {
+		if (sh_amt >= DOUBLE_MAN+2)
+		    V=isneg?-1:0;
+		else
+		    V=(man>>sh_amt) | ((man & 1ULL<<(DOUBLE_MAN+1)) ? (DOUBLE_MAN_MASK>>(DOUBLE_MAN+2-sh_amt) <<(DOUBLE_MAN+2-sh_amt)):0);
+
+		if (_AP_Q!=AP_TRN && !(_AP_Q==AP_TRN_ZERO && !_AP_S2)) {
+		    const bool qb=((F2-_AP_F > DOUBLE_MAN+2) ? isneg : (man & (1ULL<<(F2-_AP_F-1))) != 0);
+		    const int pos3=F2-_AP_F-2;
+		    const bool r = (pos3>= 0) ? (man << AP_MAX(0, _AP_W2-pos3-1)& DOUBLE_MAN_MASK)!=0  : false;
+		    carry = quantization_adjust(qb,r,isneg);
+		}
+	    }
+	    else { //no quantization
+		//                V=man;
+		if (sh_amt < _AP_W) {
+		    V = man;
+		    V <<= sh_amt;
+		}
+	    }
+	    //handle overflow/underflow
+	    if ((_AP_O != AP_WRAP || _AP_N != 0) &&
+		    ((!_AP_S && _AP_S2) || _AP_I-_AP_S <
+		     _AP_I2-_AP_S2+(QUAN_INC|| (_AP_S2 &&
+			 _AP_O==AP_SAT_SYM)) )) {// saturation
+		bool deleted_zeros = _AP_S2?true:!carry,
+		     deleted_ones = true;
+		bool neg_src;
+		const bool lD=(_AP_I2>_AP_I) && (_AP_W2-_AP_I2+_AP_I>=0) && (man & (1ULL <<(DOUBLE_MAN+2-_AP_I2+_AP_I)));
+		int pos1=F2+_AP_W-_AP_F;
+		if (pos1 < _AP_W2) {
+		    int pos2=pos1+1;
+		    bool Range1_all_ones=true;
+		    bool Range1_all_zeros=true;
+		    if (pos1>=0) {
+			ap_private<_AP_W,_AP_S> Range1=
+			    ap_private<_AP_W,_AP_S>((man >> pos1) | ((1ULL<<(DOUBLE_MAN+1)&man) ? (DOUBLE_MAN_MASK >> (DOUBLE_MAN+2-pos1) <<(DOUBLE_MAN+2-pos1)):0));
+			Range1_all_ones = Range1.isAllOnesValue(); // Range1.isAllOnesValue();
+			Range1_all_zeros = Range1.isMinValue(); // Range1.isMinValue();
+		    } else {
+			Range1_all_ones=false;
+			Range1_all_zeros = man==0; // man.isMinValue();
+		    }
+		    bool Range2_all_ones=true;
+		    if (pos2<_AP_W2 && pos2>=0) {
+			ap_private<_AP_W, _AP_S> Range2=
+			    ap_private<_AP_W, _AP_S>((man >> pos2) | ((1ULL<<(DOUBLE_MAN+1)&man) ? (DOUBLE_MAN_MASK >> (DOUBLE_MAN+2-pos2) <<(DOUBLE_MAN+2-pos2)):0));
+			Range2_all_ones=Range2.isAllOnesValue(); // Range2.isAllOnesValue();
+		    } else if (pos2<0)
+			Range2_all_ones=false;
+		    deleted_zeros=deleted_zeros && (carry?Range1_all_ones:Range1_all_zeros);
+		    deleted_ones=carry?Range2_all_ones&&(F2-_AP_F+_AP_W<0||!lD) : Range1_all_ones;
+		    neg_src=isneg&&!(carry&Range1_all_ones);
+		} else
+		    neg_src = isneg &&  V[_AP_W -1];
+
+		const bool neg_trg=V.isNegative();
+		const bool overflow=(neg_trg||!deleted_zeros) && !isneg;
+		bool underflow=(!neg_trg||!deleted_ones)&&neg_src;
+		//printf("neg_src = %d, neg_trg = %d, deleted_zeros = %d,
+		//          deleted_ones = %d, overflow = %d, underflow = %d\n",
+		//          neg_src, neg_trg, deleted_zeros, deleted_ones,
+		//          overflow, underflow);
+		if (_AP_O==AP_SAT_SYM && _AP_S2 && _AP_S)
+		    underflow |= neg_src && (_AP_W>1?V.isMinSignedValue():true);
+		overflow_adjust(underflow,overflow,lD, neg_src);
+	    }
+	}
+	report();
+    }
+
+
+        ///assign operators
+    //-------------------------------------------------------------------------
+
+    INLINE volatile ap_fixed_base& operator=(const ap_fixed_base<_AP_W, _AP_I, _AP_S,
+                                    _AP_Q, _AP_O, _AP_N>& op) volatile {
+        V = op.V;
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator=(const ap_fixed_base<_AP_W, _AP_I, _AP_S,
+                                    _AP_Q, _AP_O, _AP_N>& op) {
+        V = op.V;
+        return *this;
+    }
+
+    INLINE volatile ap_fixed_base& operator=(const volatile ap_fixed_base<_AP_W, _AP_I, _AP_S,
+                                    _AP_Q, _AP_O, _AP_N>& op) volatile {
+        V = op.V;
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator=(const volatile ap_fixed_base<_AP_W, _AP_I, _AP_S,
+                                    _AP_Q, _AP_O, _AP_N>& op) {
+        V = op.V;
+        return *this;
+    }
+
+    // Set this ap_fixed_base with a bits string. That means the ssdm_int::V
+    // inside this ap_fixed_base is assigned by bv.
+    // Note the input parameter should be a fixed-point formatted bit string.
+    INLINE ap_fixed_base& setBits(unsigned long long bv) {
+        V=bv;
+        return *this;
+    }
+
+    // Return a ap_fixed_base object whose ssdm_int::V is assigned by bv.
+    // Note the input parameter should be a fixed-point formatted bit string.
+    static INLINE ap_fixed_base bitsToFixed(unsigned long long bv) {
+	ap_fixed_base Tmp=bv;
+	return Tmp;
+    }
+
+    // Explicit conversion functions to ap_private that captures
+    // all integer bits (bits are truncated)
+    INLINE ap_private<AP_MAX(_AP_I,1),_AP_S>
+    to_ap_private(bool Cnative = true) const {
+	ap_private<AP_MAX(_AP_I,1),_AP_S> ret = ap_private<AP_MAX(_AP_I,1),_AP_S> ((_AP_I >= 1) ? (_AP_S==true ? V.ashr(AP_MAX(0,_AP_W - _AP_I)) : V.lshr(AP_MAX(0,_AP_W - _AP_I))) : ap_private<_AP_W, _AP_S>(0));
+
+	if (Cnative) {
+	    bool r = false;
+	    if (_AP_I < _AP_W) {
+		if (_AP_I > 0) r = !(V.getLoBits(_AP_W - _AP_I).isMinValue());
+		else r = !(V.isMinValue());
+	    }
+	    if (r && V.isNegative()) { // if this is negative integer
+		++ret;//ap_private<AP_MAX(_AP_I,1),_AP_S>(1,_AP_S);
+	    }
+	} else {
+	    //Follow OSCI library, conversion from sc_fixed to sc_int
+	}
+	return ret;
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE operator ap_private<_AP_W2,_AP_S2> () const {
+        return (ap_private<_AP_W2,_AP_S2>)to_ap_private();
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_N2>
+    INLINE operator ap_private<_AP_W2,_AP_S2,_AP_N2> () const {
+        return (ap_private<_AP_W2,_AP_S2,_AP_N2>)to_ap_private();
+    }
+
+    //Explict conversion function to C built-in integral type
+    INLINE int to_int() const {
+        return to_ap_private().to_int();
+    }
+
+    INLINE int to_uint() const {
+        return to_ap_private().to_uint();
+    }
+
+    INLINE ap_slong to_int64() const {
+        return to_ap_private().to_int64();
+    }
+
+    INLINE ap_ulong to_uint64() const {
+        return to_ap_private().to_uint64();
+    }
+
+    INLINE double to_double() const {
+        if (!V)
+	    return 0;
+	if (_AP_W>64 || (_AP_W - _AP_I) > 0) {
+	    bool isneg = _AP_S && V[_AP_W-1];
+	    uint64_t res = isneg ? 0x8000000000000000ULL : 0;
+	    ap_private<_AP_W, false>  tmp = V;
+	    if (isneg) tmp = -tmp;
+	    int i = _AP_W -1 - tmp.countLeadingZeros();
+	    int exp = _AP_I-(_AP_W-i);
+	    res|=((uint64_t)(exp+DOUBLE_BIAS))<<DOUBLE_MAN;
+	    if (i!=0) {
+		tmp.clear(i);
+		uint64_t man = ((i>DOUBLE_MAN)?tmp.lshr(i-DOUBLE_MAN):tmp).to_uint64() & DOUBLE_MAN_MASK;
+		res |= i<DOUBLE_MAN ? (man)<<(DOUBLE_MAN-i)& DOUBLE_MAN_MASK  : man;
+	    }
+	    double dp=rawBitsToDouble(res);
+	    return dp;
+	} else if (_AP_W - _AP_I > 0) {
+	    /* This specialization is disabled. It is giving wrong results in some cases.
+	       bool isneg=V.isNegative();
+	       double dp = V.get();
+	       dp /= (1<< (_AP_W - _AP_I));
+	       return dp;*/
+	} else
+	    return double(to_int64());
+    }
+
+    INLINE float to_float() const {
+	uint32_t res=0;
+	if (V==0)
+	    return 0;
+	bool isneg=V.isNegative();
+	ap_private<_AP_W, _AP_S> tmp=V;
+	if (isneg) tmp = -tmp;
+	if (_AP_W-_AP_I>0||_AP_W>64) {
+	    if (isneg)
+		res=0x80000000;
+	    int i=_AP_W-1;
+	    i-=tmp.countLeadingZeros();
+	    int exp=_AP_I-(_AP_W-i);
+	    res|=(exp+FLOAT_BIAS)<<FLOAT_MAN;
+
+	    ap_private<_AP_W, _AP_S> man = 0;
+	    if (i!=0) {
+		tmp.clear(i);
+		if (i>FLOAT_MAN)
+		    man=tmp.lshr(i-FLOAT_MAN);
+		else
+		    man=tmp;
+		res |= i < FLOAT_MAN?man.getZExtValue()<<(FLOAT_MAN-i):man.getZExtValue();
+	    }
+	} else {
+	    return float(to_int64());
+	}
+	float dp=rawBitsToFloat(res);
+	return dp;
+    }
+
+    INLINE operator double () const {
+	return to_double();
+    }
+#ifndef __SC_COMPATIBLE__
+    INLINE operator float () const {
+           return to_float();
+    }
+
+    INLINE operator char () const {
+        return (char) to_int();
+    }
+
+    INLINE operator unsigned char () const {
+        return (unsigned char) to_uint();
+    }
+
+    INLINE operator short () const {
+        return (short) to_int();
+    }
+
+    INLINE operator unsigned short () const {
+        return (unsigned short) to_uint();
+    }
+
+    INLINE operator int () const {
+        return to_int();
+    }
+
+    INLINE operator unsigned int () const {
+        return to_uint();
+    }
+#if 1
+#ifdef __x86_64__
+    INLINE operator long () const {
+        return (long)to_int64();
+    }
+
+    INLINE operator unsigned long () const {
+        return (unsigned long) to_uint64();
+    }
+#else
+    INLINE operator long () const {
+        return to_int64();
+    }
+
+    INLINE operator unsigned long () const {
+        return to_uint64();
+    }
+
+#endif
+#endif
+    INLINE operator unsigned long long () const {
+        return to_uint64();
+    }
+
+    INLINE operator long long () const {
+        return to_int64();
+    }
+#endif
+
+    INLINE std::string to_string(uint8_t radix=2, bool sign=false) const;
+
+    INLINE ap_slong bits_to_int64() const  {
+      ap_private<AP_MIN(_AP_W, 64), _AP_S> res(V);
+        return (ap_slong) res;
+    }
+
+    INLINE ap_ulong bits_to_uint64() const {
+      ap_private<AP_MIN(64,_AP_W), _AP_S> res(V);
+      return (ap_ulong) res;
+    }
+
+    INLINE int length() const {return _AP_W;}
+
+    // Count the number of zeros from the most significant bit
+    // to the first one bit. Note this is only for ap_fixed_base whose
+    // _AP_W <= 64, otherwise will incur assertion.
+    INLINE int countLeadingZeros() {
+        return V.countLeadingZeros();
+    }
+
+    ///Arithmetic:Binary
+    //-------------------------------------------------------------------------
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE typename RType<_AP_W2,_AP_I2,_AP_S2>::mult
+    operator * (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+	typename RType<_AP_W2,_AP_I2,_AP_S2>::mult r;
+	r.V = V * op2.V;
+	return r;
+    }
+
+    template<int _AP_W1, int _AP_I1, bool _AP_S1, int _AP_W2, int _AP_I2, bool _AP_S2>
+    static INLINE ap_fixed_base multiply(const ap_fixed_base<_AP_W1,_AP_I1,_AP_S1>& op1, const
+         ap_fixed_base<_AP_W2,_AP_I2,_AP_S2>& op2) {
+	ap_private<_AP_W+_AP_W2, _AP_S> OP1=op1.V;
+	ap_private<_AP_W2,_AP_S2> OP2=op2.V;
+	return OP1*OP2;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE typename RType<_AP_W2,_AP_I2,_AP_S2>::div
+    operator / (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+        enum {F2 = _AP_W2-_AP_I2, _W1=AP_MAX(_AP_W + AP_MAX(F2, 0), _AP_W2),
+              _W2=AP_MAX(_AP_W2,AP_MAX(_AP_W + AP_MAX(F2, 0), _AP_W2))};
+        ap_private<_W1, _AP_S> dividend = (ap_private<_W1, _AP_S>(V)) << ((_W1>_AP_W)?F2:0);
+        ap_private<_W1, _AP_S2> divisior = ap_private<_W2, _AP_S2>(op2.V);
+        ap_private<_W1, _AP_S> ret = ap_private<_W1,_AP_S> ((_AP_S||_AP_S2) ? dividend.sdiv(divisior): dividend.udiv(divisior));
+        typename RType<_AP_W2, _AP_I2, _AP_S2>::div r;
+        r.V = ret;
+        return r;
+    }
+#define OP_BIN_AF(Sym, Rty, Width, Sign, Fun)                                \
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+    INLINE typename RType<_AP_W2,_AP_I2,_AP_S2>::Rty  \
+    operator Sym (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const \
+    {                                                                        \
+	enum {_AP_F=_AP_W-_AP_I, F2=_AP_W2-_AP_I2};                                \
+	typename RType<_AP_W2,_AP_I2,_AP_S2>::Rty  r, lhs(*this), rhs(op2);        \
+	r.V = lhs.V.Fun(rhs.V);                                                \
+	return r;                                                                \
+    }                                                                        \
+    INLINE typename RType<_AP_W,_AP_I,_AP_S>::Rty                        \
+    operator Sym (const ap_fixed_base& op2) const                        \
+    {                                                                        \
+	typename RType<_AP_W,_AP_I,_AP_S>::Rty  r;                                \
+	r.V = V Sym op2.V;                                                        \
+	return r;                                                                \
+    }                                                                        \
+
+    OP_BIN_AF(+, plus, plus_w, plus_s, Add)
+    OP_BIN_AF(-, minus, minus_w, minus_s, Sub)
+
+#define OP_LOGIC_BIN_AF(Sym, Rty, Width, Sign)                                \
+        template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+        INLINE typename RType<_AP_W2,_AP_I2,_AP_S2>::Rty                \
+        operator Sym (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const \
+    {                                                                        \
+	typename RType<_AP_W2,_AP_I2,_AP_S2>::Rty r, lhs(*this), rhs(op2);  \
+	r.V=lhs.V Sym rhs.V;                                                \
+	return r;                                                                \
+    }                                                                        \
+    INLINE typename RType<_AP_W,_AP_I,_AP_S>::Rty                        \
+    operator Sym (const ap_fixed_base& op2) const                        \
+    {                                                                        \
+	typename RType<_AP_W,_AP_I,_AP_S>::Rty  r; \
+	r.V = V Sym op2.V;                                                        \
+	return r;                                                                \
+    }                                                                        \
+    INLINE typename RType<_AP_W,_AP_I,_AP_S>::Rty  operator Sym(int op2) const \
+    {                                                                        \
+	return V Sym (op2<<(_AP_W - _AP_I));                                \
+    }
+    OP_LOGIC_BIN_AF(&, logic, logic_w, logic_s)
+    OP_LOGIC_BIN_AF(|, logic, logic_w, logic_s)
+    OP_LOGIC_BIN_AF(^, logic, logic_w, logic_s)
+
+    ///Arithmic : assign
+    //-------------------------------------------------------------------------
+#define OP_ASSIGN_AF(Sym) \
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+    INLINE ap_fixed_base& operator Sym##= (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) \
+    { \
+        *this=operator Sym (op2) ; \
+        return *this; \
+    }
+
+    OP_ASSIGN_AF(+)
+    OP_ASSIGN_AF(-)
+    OP_ASSIGN_AF(&)
+    OP_ASSIGN_AF(|)
+    OP_ASSIGN_AF(^)
+    OP_ASSIGN_AF(*)
+    OP_ASSIGN_AF(/)
+
+    ///Prefix increment, decrement
+    //-------------------------------------------------------------------------
+    INLINE ap_fixed_base& operator ++() {
+        operator+=(ap_fixed_base<1,1,false>(1)); //SystemC's semantics
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator --() {
+        operator-=(ap_fixed_base<1,1,false>(1)); //SystemC's semantics
+        return *this;
+    }
+
+    //Postfix increment, decrement
+    //-------------------------------------------------------------------------
+    INLINE const ap_fixed_base operator ++(int) {
+        ap_fixed_base t(*this);
+        operator++();
+        return t;
+    }
+
+    INLINE const ap_fixed_base operator --(int) {
+        ap_fixed_base t = *this;
+        operator--();
+        return t;
+    }
+
+    ///Unary arithmetic
+    //-------------------------------------------------------------------------
+    INLINE ap_fixed_base operator +() {return *this;}
+
+    INLINE ap_fixed_base<_AP_W + 1, _AP_I + 1, true> operator -() const {
+        ap_fixed_base<_AP_W + 1, _AP_I + 1, true> Tmp(*this);
+        Tmp.V = - Tmp.V;
+        return Tmp;
+    }
+
+    INLINE ap_fixed_base<_AP_W,_AP_I,true,_AP_Q,_AP_O, _AP_N> getNeg() {
+        ap_fixed_base<_AP_W,_AP_I,true,_AP_Q,_AP_O, _AP_N> Tmp(*this);
+        Tmp.V=-Tmp.V;
+        return Tmp;
+    }
+
+    ///Not (!)
+    //-------------------------------------------------------------------------
+    INLINE bool operator !() const {
+	return !V;
+    }
+
+    ///Bitwise complement
+    //-------------------------------------------------------------------------
+    INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S>
+         operator ~() const {
+        ap_fixed_base<_AP_W, _AP_I, _AP_S> res(*this);
+        res.V.flip();
+        return res;
+    }
+
+    ///Shift
+    ///template argument as shift value
+    template<int _AP_SHIFT>
+    INLINE ap_fixed_base<_AP_W, _AP_I + _AP_SHIFT, _AP_S> lshift () const {
+        ap_fixed_base<_AP_W, _AP_I + _AP_SHIFT, _AP_S> r;
+        r.V = V;
+        return r;
+    }
+
+    template<int _AP_SHIFT>
+    INLINE ap_fixed_base<_AP_W, _AP_I - _AP_SHIFT, _AP_S> rshift () const {
+        ap_fixed_base<_AP_W, _AP_I - _AP_SHIFT, _AP_S> r;
+        r.V = V;
+        return r;
+    }
+
+    //Because the return type is the type of the the first operand, shift assign
+    //operators do not carry out any quantization or overflow
+    //While systemc, shift assigns for sc_fixed/sc_ufixed will result in
+    //quantization or overflow (depending on the mode of the first operand)
+    //-------------------------------------------------------------------------
+    INLINE ap_fixed_base operator << (int sh) const {
+        ap_fixed_base r;
+        bool isNeg=(sh&0x80000000) != 0;
+        sh=isNeg?-sh:sh;
+        bool shiftoverflow = sh >= _AP_W;
+        bool NegSrc = V.isNegative();
+        if (isNeg) {
+            if (shiftoverflow)
+                NegSrc?r.V.set():r.V.clear();
+            else
+                r.V=_AP_S?V.ashr(sh):V.lshr(sh);
+        } else {
+            if (shiftoverflow)
+                r.V.clear();
+            else
+                r.V=V<<sh;
+        }
+#ifdef __SC_COMPATIBLE__
+        if (sh == 0) return r;
+        if (isNeg == true && _AP_Q != AP_TRN) {
+           bool qb = false;
+           if (sh <= _AP_W) qb = V[sh - 1];
+           bool rb  =  false;
+           if (sh > 1 && sh <= _AP_W)
+                rb = (V << (_AP_W - sh + 1 )) != 0;
+           else if (sh > _AP_W)
+                rb = V != 0;
+           r.quantization_adjust(qb, rb, NegSrc);
+        } else if (isNeg == false && _AP_O != AP_WRAP) {
+             bool allones, allzeros;
+             if (sh < _AP_W ) {
+                 ap_private<_AP_W, _AP_S > range1 = V.lshr(_AP_W - sh - 1);
+                 allones = range1.isAllOnesValue();
+                 allzeros = range1.isMinValue();
+             } else {
+                 allones = false;
+                 allzeros = V.isMinValue();
+             }
+             bool overflow = !allzeros && !NegSrc;
+             bool underflow = !allones && NegSrc;
+             if (_AP_O == AP_SAT_SYM && _AP_S)
+                  underflow |= NegSrc && (_AP_W > 1 ? r.V.isMinSignedValue():true);
+             bool lD = false;
+             if ( sh < _AP_W ) lD = V[_AP_W - sh - 1];
+             r.overflow_adjust(underflow, overflow, lD, NegSrc);
+        }
+#endif
+        return r;
+    }
+
+    template<int _AP_W2>
+    INLINE ap_fixed_base operator<<(const ap_private<_AP_W2,true>& op2) const {
+        int sh = op2.to_int();
+        return operator << (sh);
+    }
+
+    INLINE ap_fixed_base operator << (unsigned int sh ) const {
+        ap_fixed_base r;
+        bool shiftoverflow = sh >= _AP_W;
+        r.V = shiftoverflow ? ap_private<_AP_W, _AP_S >(0) : V << sh;
+        if (sh == 0) return r;
+#ifdef __SC_COMPATIBLE__
+        bool NegSrc = V.isNegative();
+        if (_AP_O != AP_WRAP) {
+             bool allones, allzeros;
+             if (sh < _AP_W ) {
+                 ap_private<_AP_W, _AP_S > range1 = V.lshr(_AP_W - sh -1);
+                 allones = range1.isAllOnesValue();
+                 allzeros = range1.isMinValue();
+             } else {
+                 allones = false;
+                 allzeros = V.isMinValue();
+             }
+             bool overflow = !allzeros && !NegSrc;
+             bool underflow = !allones && NegSrc;
+             if (_AP_O == AP_SAT_SYM && _AP_S)
+                  underflow |= NegSrc && (_AP_W > 1 ? r.V.isMinSignedValue():true);
+             bool lD = false;
+             if ( sh < _AP_W ) lD = V[_AP_W - sh - 1];
+             r.overflow_adjust(underflow, overflow, lD, NegSrc);
+        }
+#endif
+        return r;
+    }
+
+    template<int _AP_W2>
+    INLINE ap_fixed_base operator << (const ap_private<_AP_W2,false>& op2) const {
+        unsigned int sh = op2.to_uint();
+        return operator << (sh);
+    }
+
+    INLINE ap_fixed_base operator >> (int sh) const {
+        ap_fixed_base r;
+        bool isNeg=(sh&0x80000000) != 0;
+        bool NegSrc = V.isNegative();
+        sh=isNeg?-sh:sh;
+        bool shiftoverflow = sh >= _AP_W;
+        if (isNeg && !shiftoverflow) r.V=V<<sh;
+        else {
+            if (shiftoverflow)
+                NegSrc?r.V.set():r.V.clear();
+            else
+                r.V=_AP_S?V.ashr(sh):V.lshr(sh);
+        }
+#ifdef __SC_COMPATIBLE__
+        if (sh == 0) return r;
+        if (isNeg == false && _AP_Q != AP_TRN) {
+           bool qb = false;
+           if (sh <= _AP_W) qb = V[sh - 1];
+           bool rb  =  false;
+           if (sh > 1 && sh <= _AP_W)
+                rb = (V << (_AP_W - sh + 1 )) != 0;
+           else if (sh > _AP_W)
+                rb = V != 0;
+           r.quantization_adjust(qb, rb, NegSrc);
+        } else if (isNeg == true && _AP_O != AP_WRAP) {
+             bool allones, allzeros;
+             if (sh < _AP_W ) {
+                 ap_private<_AP_W, _AP_S > range1 = V.lshr(_AP_W - sh - 1);
+                 allones = range1.isAllOnesValue();
+                 allzeros = range1.isMinValue();
+             } else {
+                 allones = false;
+                 allzeros = V.isMinValue();
+             }
+             bool overflow = !allzeros && !NegSrc;
+             bool underflow = !allones && NegSrc;
+             if (_AP_O == AP_SAT_SYM && _AP_S)
+                  underflow |= NegSrc && (_AP_W > 1 ? r.V.isMinSignedValue():true);
+             bool lD = false;
+             if ( sh < _AP_W ) lD = V[_AP_W - sh - 1];
+             r.overflow_adjust(underflow, overflow, lD, NegSrc);
+        }
+#endif
+        return r;
+    }
+
+    template<int _AP_W2>
+    INLINE ap_fixed_base operator >> (const ap_private<_AP_W2,true>& op2) const {
+        int sh = op2.to_int();
+        return operator >> (sh);
+    }
+
+    INLINE ap_fixed_base operator >> (unsigned int sh) const {
+        ap_fixed_base r;
+        bool NegSrc = V.isNegative();
+        bool shiftoverflow = sh >= _AP_W;
+        if (shiftoverflow)
+            NegSrc?r.V.set():r.V.clear();
+        else
+            r.V=_AP_S?V.ashr(sh):V.lshr(sh);
+#ifdef __SC_COMPATIBLE__
+        if (sh == 0) return r;
+        if (_AP_Q != AP_TRN) {
+           bool qb = false;
+           if (sh <= _AP_W) qb = V[sh - 1];
+           bool rb  =  false;
+           if (sh > 1 && sh <= _AP_W)
+                rb = (V << (_AP_W - sh + 1 )) != 0;
+           else if (sh > _AP_W)
+                rb = V != 0;
+           r.quantization_adjust(qb, rb, NegSrc);
+        }
+#endif
+        return r;
+    }
+
+    template<int _AP_W2>
+    INLINE ap_fixed_base operator >> (const ap_private<_AP_W2,false>& op2) const {
+        unsigned int sh = op2.to_uint();
+        return operator >> (sh);
+    }
+
+    ///shift assign
+    //-------------------------------------------------------------------------
+#define OP_AP_SHIFT_AP_ASSIGN_AF(Sym) \
+    template<int _AP_W2, bool _AP_S2> \
+    INLINE ap_fixed_base& operator Sym##=(const ap_private<_AP_W2,_AP_S2>& op2) \
+    { \
+        *this=operator Sym (op2); \
+        return *this; \
+    }
+
+    OP_AP_SHIFT_AP_ASSIGN_AF(<<)
+    OP_AP_SHIFT_AP_ASSIGN_AF(>>)
+
+    ///Support shift(ap_fixed_base)
+#define OP_AP_SHIFT_AF(Sym) \
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+    INLINE ap_fixed_base operator Sym (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const \
+    { \
+        return operator Sym (op2.to_ap_private()); \
+    } \
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2> \
+    INLINE ap_fixed_base& operator Sym##= (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) \
+    { \
+        *this=operator Sym (op2); \
+        return *this; \
+    }
+
+    OP_AP_SHIFT_AF(<<)
+    OP_AP_SHIFT_AF(>>)
+
+    INLINE ap_fixed_base& operator >>= (unsigned int sh) {
+        *this = operator >> (sh);
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator <<= (unsigned int sh) {
+        *this = operator << (sh);
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator >>= (int sh) {
+        *this = operator >> (sh);
+        return *this;
+    }
+
+    INLINE ap_fixed_base& operator <<= (int sh) {
+        *this = operator << (sh);
+        return *this;
+    }
+
+    ///Comparisons
+    //-------------------------------------------------------------------------
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator == (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+	enum {_AP_F=_AP_W-_AP_I,F2=_AP_W2-_AP_I2, shAmt1 = AP_MAX(F2-_AP_F, 0), shAmt2 = AP_MAX(_AP_F-F2,0), _AP_W3 = (_AP_F==F2) ? AP_MAX(_AP_W,_AP_W2) : AP_MAX(_AP_W+shAmt1, _AP_W2+shAmt2)};
+	ap_private<_AP_W3, _AP_S > OP1= ap_private<_AP_W3, _AP_S >(V)<<shAmt1;
+	ap_private<_AP_W3,_AP_S2 > OP2=ap_private<_AP_W3,_AP_S2 >(op2.V)<<shAmt2;
+	return OP1 == OP2;
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator != (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+        return !(*this==op2);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator > (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+	enum {_AP_F=_AP_W-_AP_I,F2=_AP_W2-_AP_I2, shAmt1 = AP_MAX(F2-_AP_F, 0), shAmt2 = AP_MAX(_AP_F-F2,0), _AP_W3 = (_AP_F==F2) ? AP_MAX(_AP_W,_AP_W2) : AP_MAX(_AP_W+shAmt1, _AP_W2+shAmt2)};
+	ap_private<_AP_W3, _AP_S > OP1= ap_private<_AP_W3, _AP_S >(V)<<shAmt1;
+	ap_private<_AP_W3,_AP_S2 > OP2=ap_private<_AP_W3,_AP_S2 >(op2.V)<<shAmt2;
+	if (_AP_S||_AP_S2)
+	    return OP1.sgt(OP2);
+	else
+	    return OP1.ugt(OP2);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator <= (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+        return !(*this>op2);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator < (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+	enum {_AP_F=_AP_W-_AP_I,F2=_AP_W2-_AP_I2, shAmt1 = AP_MAX(F2-_AP_F, 0), shAmt2 = AP_MAX(_AP_F-F2,0), _AP_W3 = (_AP_F==F2) ? AP_MAX(_AP_W,_AP_W2) : AP_MAX(_AP_W+shAmt1, _AP_W2+shAmt2)};
+	ap_private<_AP_W3, _AP_S > OP1= ap_private<_AP_W3, _AP_S >(V)<<shAmt1;
+	ap_private<_AP_W3,_AP_S2 > OP2=ap_private<_AP_W3,_AP_S2 >(op2.V)<<shAmt2;
+	if (_AP_S||_AP_S2)
+	    return OP1.slt(OP2);
+	else
+	    return OP1.ult(OP2);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE bool operator >= (const ap_fixed_base<_AP_W2,_AP_I2,_AP_S2,_AP_Q2,_AP_O2, _AP_N2>& op2) const {
+        return !(*this<op2);
+    }
+
+#define DOUBLE_CMP_AF(Sym) \
+    INLINE bool operator Sym (double d) const { \
+        return to_double() Sym d; \
+    }
+
+    DOUBLE_CMP_AF(==)
+    DOUBLE_CMP_AF(!=)
+    DOUBLE_CMP_AF(>)
+    DOUBLE_CMP_AF(>=)
+    DOUBLE_CMP_AF(<)
+    DOUBLE_CMP_AF(<=)
+
+    // Bit and Slice Select
+    INLINE af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> operator [] (unsigned int index) {
+        assert(index<_AP_W&&"Attemping to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index);
+    }
+
+    INLINE af_bit_ref<_AP_W, _AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> bit(unsigned int index) {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> bit (const ap_private<_AP_W2,_AP_S2>& index) {
+        assert(index >= 0 && "Attempting to read bit with negative index");
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index.to_int());
+    }
+
+    INLINE bool bit (unsigned int index) const {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return V[index];
+    }
+
+    INLINE bool operator [] (unsigned int index) const {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return V[index];
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool bit (const ap_private<_AP_W2, _AP_S2>& index) const {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return V[index.to_uint()];
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator [] (const ap_private<_AP_W2, _AP_S2>& index) const {
+        assert(index < _AP_W && "Attempting to read bit beyond MSB");
+        return V[index.to_uint()];
+    }
+
+    INLINE af_bit_ref<_AP_W, _AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> get_bit(int index) {
+        assert(index < _AP_I && "Attempting to read bit beyond MSB");
+        assert(index >= _AP_I - _AP_W&& "Attempting to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index + _AP_W - _AP_I);
+    }
+
+    template<int _AP_W2>
+    INLINE af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N> get_bit (const ap_private<_AP_W2, true>& index) {
+        assert(index >= _AP_I - _AP_W && "Attempting to read bit with negative index");
+        assert(index < _AP_I && "Attempting to read bit beyond MSB");
+        return af_bit_ref<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(this, index.to_int() + _AP_W - _AP_I);
+    }
+
+    INLINE bool get_bit (int index) const {
+        assert(index >= _AP_I - _AP_W && "Attempting to read bit with negative index");
+        assert(index < _AP_I && "Attempting to read bit beyond MSB");
+        return V[index + _AP_W - _AP_I];
+    }
+
+    template<int _AP_W2>
+    INLINE bool get_bit (const ap_private<_AP_W2, true>& index) const {
+        assert(index >= _AP_I - _AP_W && "Attempting to read bit with negative index");
+        assert(index < _AP_I && "Attempting to read bit beyond MSB");
+        return V[index.to_int() + _AP_W - _AP_I];
+    }
+
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    range(int Hi, int Lo) {
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    operator () (int Hi, int Lo) {
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    range(int Hi, int Lo) const {
+        assert((Hi < _AP_W) && (Lo < _AP_W) &&"Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(const_cast<ap_fixed_base*>(this), Hi, Lo);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    operator () (int Hi, int Lo) const {
+        return this->range(Hi, Lo);
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    range(const ap_private<_AP_W2, _AP_S2> &HiIdx,
+          const ap_private<_AP_W3, _AP_S3> &LoIdx) {
+        int Hi = HiIdx.to_int();
+        int Lo = LoIdx.to_int();
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    operator () (const ap_private<_AP_W2, _AP_S2> &HiIdx,
+                 const ap_private<_AP_W3, _AP_S3> &LoIdx) {
+        int Hi = HiIdx.to_int();
+        int Lo = LoIdx.to_int();
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    range(const ap_private<_AP_W2, _AP_S2> &HiIdx,
+          const ap_private<_AP_W3, _AP_S3> &LoIdx) const {
+        int Hi = HiIdx.to_int();
+        int Lo = LoIdx.to_int();
+        assert((Hi < _AP_W) && (Lo < _AP_W) && "Out of bounds in range()");
+        return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(const_cast<
+               ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>*>(this),
+               Hi, Lo);
+    }
+
+    template<int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+    INLINE af_range_ref<_AP_W,_AP_I,_AP_S, _AP_Q, _AP_O, _AP_N>
+    operator () (const ap_private<_AP_W2, _AP_S2> &HiIdx,
+                 const ap_private<_AP_W3, _AP_S3> &LoIdx) const {
+        int Hi = HiIdx.to_int();
+        int Lo = LoIdx.to_int();
+        return this->range(Hi, Lo);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    range() {
+        return this->range(_AP_W - 1, 0);
+    }
+
+    INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>
+    range() const {
+        return this->range(_AP_W - 1, 0);
+    }
+
+    INLINE bool is_zero () const {
+        return V.isMinValue();
+    }
+
+    INLINE bool is_neg () const {
+        if (V.isNegative())
+            return true;
+        return false;
+    }
+
+    INLINE int wl () const {
+        return _AP_W;
+    }
+
+    INLINE int iwl () const {
+        return _AP_I;
+    }
+
+    INLINE ap_q_mode q_mode () const {
+        return _AP_Q;
+    }
+
+    INLINE ap_o_mode o_mode () const {
+        return _AP_O;
+    }
+
+    INLINE int n_bits () const {
+        return 0;
+    }
+
+  //private:
+public:
+    ap_private<_AP_W, _AP_S> V;
+};
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+std::string ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>::to_string(
+                                            uint8_t radix, bool sign) const {
+    std::string str;
+    str.clear();
+    char step;
+    std::string prefix;
+    switch (radix) {
+        case 2  : prefix = "0b"; step = 1; break;
+        case 8  : prefix = "0o"; step = 3; break;
+        case 16 : prefix = "0x"; step = 4; break;
+        default : break;
+    }
+    if (_AP_W <= _AP_I)
+        str = this->to_ap_private().to_string(radix,
+               radix == 10 ? _AP_S : sign);
+    else {
+        if (radix == 10) {
+            bool isNeg = _AP_S && V.isNegative();
+            if (_AP_I > 0) {
+                ap_private<AP_MAX(_AP_I, 1),  _AP_S> int_part(0);
+                int_part = this->to_ap_private();
+                str += int_part.to_string(radix, false);
+            } else {
+                if (isNeg) str += '-';
+            }
+            ap_fixed_base<_AP_W, _AP_I, _AP_S> tmp(*this);
+            if (isNeg && _AP_I <= 0) tmp = -tmp;
+            ap_fixed_base<_AP_W - AP_MIN(_AP_I, 0), 0, false> frac_part = tmp;
+            if (frac_part == 0) return str;
+            str += ".";
+            while (frac_part != 0) {
+               char digit = (frac_part * radix).to_ap_private();
+               str += static_cast<char>(digit + '0');
+               frac_part *= radix;
+            }
+        } else {
+            if (_AP_I > 0) {
+                for (signed i = _AP_W - _AP_I; i < _AP_W; i += step) {
+
+                     char digit = (char)(this->range(AP_MIN(i + step - 1, _AP_W - 1), i));
+                     str = (digit < 10 ? static_cast<char>(digit + '0') :
+                                        static_cast<char>(digit - 10 + 'a')) + str;
+                }
+            }
+            str += '.';
+            ap_fixed_base<AP_MAX(_AP_W - _AP_I, 1), 0, _AP_S> tmp(*this);
+            for (signed i = _AP_W - _AP_I - 1; i >= 0; i -= step) {
+                char digit = (char)(tmp.range(i, AP_MAX(0, i - step + 1)));
+                str += digit < 10 ? static_cast<char>(digit + '0') :
+                       static_cast<char>(digit - 10 + 'a');
+            }
+        }
+    }
+    str = prefix + str;
+    return str;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void b_not(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {
+    ret.V = op.V;
+    ret.V.flip();
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void b_and(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+    ret.V =  op1.V & op2.V;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void b_or(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+    ret.V =  op1.V | op2.V;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void b_xor(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+    ret.V =  op1.V ^ op2.V;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+          ap_o_mode _AP_O2, int _AP_N2>
+INLINE void neg(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    ap_fixed_base<_AP_W2+!_AP_S2, _AP_I2+!_AP_S2, true, _AP_Q2, _AP_O2, _AP_N2> Tmp;
+    Tmp.V = - op.V;
+    ret = Tmp;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N>
+INLINE void neg(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {
+    ret.V = -op.V;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+         ap_o_mode _AP_O2, int _AP_N2>
+INLINE void lshift(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op,
+            int i) {
+    ap_fixed_base<_AP_W2 - _AP_I2 + AP_MAX(_AP_I, _AP_I2), AP_MAX(_AP_I, _AP_I2), _AP_S2, _AP_Q2, _AP_O2, _AP_N2> Tmp;
+    Tmp = op;
+    Tmp.V <<= i;
+    ret = Tmp;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N>
+INLINE void lshift(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,
+            int i) {
+    ret.V = op.V << i;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+         ap_o_mode _AP_O2, int _AP_N2>
+INLINE void rshift(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op,
+            int i) {
+    ap_fixed_base<_AP_I2 + AP_MAX(_AP_W - _AP_I, _AP_W2 - _AP_I2), _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> Tmp;
+    Tmp = op;
+    Tmp.V = _AP_S2 ? Tmp.V.ashr(i): Tmp.V.lshr(i);
+    ret = Tmp;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+         int _AP_N>
+INLINE void rshift(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+            const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,
+            int i) {
+    ret.V = _AP_S ? op.V.ashr(i): op.V.lshr(i);
+}
+
+#define AF_CTOR_SPEC_BASE(_AP_W,_AP_S,C_TYPE) \
+  template<> INLINE ap_fixed_base<_AP_W,_AP_W,_AP_S,AP_TRN,AP_WRAP>::ap_fixed_base(C_TYPE i_op):V(i_op) \
+    { \
+  }
+
+#define AF_CTOR_SPEC(__W,C_TYPE) \
+    AF_CTOR_SPEC_BASE(__W,true,C_TYPE) \
+    AF_CTOR_SPEC_BASE(__W,false,C_TYPE)
+
+AF_CTOR_SPEC(1,bool)
+AF_CTOR_SPEC(8, signed char)
+AF_CTOR_SPEC(8, unsigned char)
+AF_CTOR_SPEC(16, signed short)
+AF_CTOR_SPEC(16, unsigned short)
+AF_CTOR_SPEC(32, signed int)
+AF_CTOR_SPEC(32, unsigned int)
+AF_CTOR_SPEC(64, ap_slong)
+AF_CTOR_SPEC(64, ap_ulong)
+
+///Output streaming
+//-----------------------------------------------------------------------------
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE std::ostream&
+operator <<(std::ostream& os, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& x) {
+     os << x.to_double();
+     return os;
+}
+
+///Input streaming
+//-----------------------------------------------------------------------------
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE std::istream&
+operator >> (std::istream& os, ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& x) {
+     double d;
+     os >> d;
+     x = ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>(x);
+     return os;
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void print(const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& x) {
+    ap_private<_AP_W,_AP_S> data=x.V;
+    if (_AP_I>0) {
+        const ap_private<_AP_I,_AP_S> p1=data>>(_AP_W-_AP_I);
+        print(p1);
+
+    } else
+        printf("0");
+    printf(".");
+    if (_AP_I<_AP_W) {
+        const ap_private<_AP_W-_AP_I,false> p2=data;
+        print(p2,false);
+    }
+}
+
+///Operators mixing Integers with ap_fixed_base
+//-----------------------------------------------------------------------------
+#if 1
+#define AF_BIN_OP_WITH_INT_SF(BIN_OP,C_TYPE,_AP_W2,_AP_S2,RTYPE)        \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+  {                                                                        \
+    return op.operator BIN_OP(ap_private<_AP_W2,_AP_S2>(i_op));        \
+  }
+#define AF_BIN_OP_WITH_INT(BIN_OP, C_TYPE, _AP_W2,_AP_S2,RTYPE)                \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+  {                                                                        \
+    return op.operator BIN_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  }                                                                        \
+                                                                        \
+  template<int _AP_W, int _AP_I, bool _AP_S,ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (C_TYPE i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) \
+  {                                                                        \
+    return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator BIN_OP (op); \
+  }
+
+#else
+#define AF_BIN_OP_WITH_INT_SF(BIN_OP,C_TYPE,_AP_W2,_AP_S2,RTYPE)        \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+  {                                                                        \
+    return op BIN_OP (i_op);                                        \
+  }
+#define AF_BIN_OP_WITH_INT(BIN_OP, C_TYPE, _AP_W2,_AP_S2,RTYPE)                \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+  {                                                                        \
+    return op.V BIN_OP (i_op<<(_AP_W-_AP_I));                        \
+  }                                                                        \
+                                                                          \
+                                                                          \
+  template<int _AP_W, int _AP_I, bool _AP_S,ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N > \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP (C_TYPE i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) \
+  {                                                                        \
+    return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator BIN_OP (op);                        \
+  }
+
+#endif
+#if 1
+#define AF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2,_AP_S2)                \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+    INLINE bool operator REL_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+    { \
+        return op.operator REL_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+    } \
+    \
+    \
+    template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+    INLINE bool operator REL_OP (C_TYPE i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) \
+    { \
+        return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator REL_OP (op); \
+    }
+#else
+#define AF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2,_AP_S2) \
+    template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+    INLINE bool operator REL_OP (const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) \
+    { \
+      return op.V.operator REL_OP (i_op<<(_AP_W-_AP_I));        \
+    } \
+    \
+    \
+    template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+    INLINE bool operator REL_OP (C_TYPE i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) \
+    { \
+      return (i_op<<(_AP_W-_AP_I)) REL_OP (op.V.VAL);        \
+    }
+#endif
+#if 1
+#define AF_ASSIGN_OP_WITH_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) { \
+    return op.operator ASSIGN_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  }
+#define AF_ASSIGN_OP_WITH_INT_SF(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) { \
+    return op.operator ASSIGN_OP (ap_private<_AP_W2,_AP_S2>(i_op)); \
+  }
+#else
+#define AF_ASSIGN_OP_WITH_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) { \
+    return op.V.operator ASSIGN_OP (i_op);                                \
+  }
+#define AF_ASSIGN_OP_WITH_INT_SF(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, C_TYPE i_op) { \
+    return op.V.operator ASSIGN_OP (i_op); \
+  }
+#endif
+
+#define AF_OPS_WITH_INT(C_TYPE, WI, SI) \
+  AF_BIN_OP_WITH_INT(+, C_TYPE, WI, SI, plus) \
+  AF_BIN_OP_WITH_INT(-, C_TYPE, WI, SI, minus) \
+  AF_BIN_OP_WITH_INT(*, C_TYPE, WI, SI, mult) \
+  AF_BIN_OP_WITH_INT(/, C_TYPE, WI, SI, div) \
+  AF_BIN_OP_WITH_INT_SF(>>, C_TYPE, WI, SI, arg1) \
+  AF_BIN_OP_WITH_INT_SF(<<, C_TYPE, WI, SI, arg1) \
+  AF_BIN_OP_WITH_INT(&, C_TYPE, WI, SI, logic) \
+  AF_BIN_OP_WITH_INT(|, C_TYPE, WI, SI, logic) \
+  AF_BIN_OP_WITH_INT(^, C_TYPE, WI, SI, logic) \
+  \
+  AF_REL_OP_WITH_INT(==, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(!=, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(>, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(>=, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(<, C_TYPE, WI, SI) \
+  AF_REL_OP_WITH_INT(<=, C_TYPE, WI, SI) \
+  \
+  AF_ASSIGN_OP_WITH_INT(+=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(-=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(*=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(/=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT_SF(>>=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT_SF(<<=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(&=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(|=, C_TYPE, WI, SI) \
+  AF_ASSIGN_OP_WITH_INT(^=, C_TYPE, WI, SI)
+
+AF_OPS_WITH_INT(bool, 1, false)
+AF_OPS_WITH_INT(char, 8, true)
+AF_OPS_WITH_INT(signed char, 8, true)
+AF_OPS_WITH_INT(unsigned char, 8, false)
+AF_OPS_WITH_INT(short, 16, true)
+AF_OPS_WITH_INT(unsigned short, 16, false)
+AF_OPS_WITH_INT(int, 32, true)
+AF_OPS_WITH_INT(unsigned int, 32, false)
+# if defined __x86_64__
+AF_OPS_WITH_INT(long, 64, true)
+AF_OPS_WITH_INT(unsigned long, 64, false)
+# else
+AF_OPS_WITH_INT(long, 32, true)
+AF_OPS_WITH_INT(unsigned long, 32, false)
+# endif
+AF_OPS_WITH_INT(ap_slong, 64, true)
+AF_OPS_WITH_INT(ap_ulong, 64, false)
+
+#define AF_BIN_OP_WITH_AP_INT(BIN_OP, RTYPE) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>::template RType<_AP_W,_AP_I,_AP_S>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W2,_AP_S2>& i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) { \
+    return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator BIN_OP (op); \
+  } \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_fixed_base<_AP_W,_AP_I,_AP_S>::template RType<_AP_W2,_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, const ap_private<_AP_W2,_AP_S2>& i_op) { \
+    return op.operator BIN_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  }
+
+#define AF_REL_OP_WITH_AP_INT(REL_OP) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, const ap_private<_AP_W2,_AP_S2>& i_op) { \
+    return op.operator REL_OP ( ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  } \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_private<_AP_W2,_AP_S2>& i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) { \
+    return ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op).operator REL_OP (op); \
+  }
+
+#define AF_ASSIGN_OP_WITH_AP_INT(ASSIGN_OP) \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& operator ASSIGN_OP ( ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op, const ap_private<_AP_W2,_AP_S2>& i_op) { \
+    return op.operator ASSIGN_OP (ap_fixed_base<_AP_W2,_AP_W2,_AP_S2>(i_op)); \
+  } \
+  template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE ap_private<_AP_W2,_AP_S2>& operator ASSIGN_OP ( ap_private<_AP_W2,_AP_S2>& i_op, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op) { \
+    return i_op.operator ASSIGN_OP (op.to_ap_private()); \
+  }
+
+AF_BIN_OP_WITH_AP_INT(+, plus)
+AF_BIN_OP_WITH_AP_INT(-, minus)
+AF_BIN_OP_WITH_AP_INT(*, mult)
+AF_BIN_OP_WITH_AP_INT(/, div)
+AF_BIN_OP_WITH_AP_INT(&, logic)
+AF_BIN_OP_WITH_AP_INT(|, logic)
+AF_BIN_OP_WITH_AP_INT(^, logic)
+
+AF_REL_OP_WITH_AP_INT(==)
+AF_REL_OP_WITH_AP_INT(!=)
+AF_REL_OP_WITH_AP_INT(>)
+AF_REL_OP_WITH_AP_INT(>=)
+AF_REL_OP_WITH_AP_INT(<)
+AF_REL_OP_WITH_AP_INT(<=)
+
+AF_ASSIGN_OP_WITH_AP_INT(+=)
+AF_ASSIGN_OP_WITH_AP_INT(-=)
+AF_ASSIGN_OP_WITH_AP_INT(*=)
+AF_ASSIGN_OP_WITH_AP_INT(/=)
+AF_ASSIGN_OP_WITH_AP_INT(&=)
+AF_ASSIGN_OP_WITH_AP_INT(|=)
+AF_ASSIGN_OP_WITH_AP_INT(^=)
+
+#define AF_REF_REL_OP_MIX_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE bool operator REL_OP ( const af_range_ref<_AP_W,_AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op, C_TYPE op2) {  \
+    return (ap_private<_AP_W, false>(op)).operator REL_OP (ap_private<_AP_W2,_AP_S2>(op2));  \
+  }  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE bool operator REL_OP ( C_TYPE op2, const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op) {  \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator REL_OP (ap_private<_AP_W, false>(op));  \
+  } \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE bool operator REL_OP ( const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op, C_TYPE op2) {  \
+    return (bool(op)) REL_OP op2;  \
+  }  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> \
+  INLINE bool operator REL_OP ( C_TYPE op2, const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op) {  \
+    return op2 REL_OP (bool(op));  \
+  }
+
+#define AF_REF_REL_MIX_INT(C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(>, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(<, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(>=, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(<=, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(==, C_TYPE, _AP_WI, _AP_SI) \
+AF_REF_REL_OP_MIX_INT(!=, C_TYPE, _AP_WI, _AP_SI)
+
+AF_REF_REL_MIX_INT(bool, 1, false)
+AF_REF_REL_MIX_INT(char, 8, true)
+AF_REF_REL_MIX_INT(signed char, 8, true)
+AF_REF_REL_MIX_INT(unsigned char, 8, false)
+AF_REF_REL_MIX_INT(short, 16, true)
+AF_REF_REL_MIX_INT(unsigned short, 16, false)
+AF_REF_REL_MIX_INT(int, 32, true)
+AF_REF_REL_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+AF_REF_REL_MIX_INT(long, 64, true)
+AF_REF_REL_MIX_INT(unsigned long, 64, false)
+# else
+AF_REF_REL_MIX_INT(long, 32, true)
+AF_REF_REL_MIX_INT(unsigned long, 32, false)
+# endif
+AF_REF_REL_MIX_INT(ap_slong, 64, true)
+AF_REF_REL_MIX_INT(ap_ulong, 64, false)
+
+#define AF_REF_REL_OP_AP_INT(REL_OP)  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const af_range_ref<_AP_W,_AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op, const ap_private<_AP_W2, _AP_S> &op2) {  \
+    return (ap_private<_AP_W, false>(op)).operator REL_OP (op2);  \
+  }  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP (const ap_private<_AP_W2, _AP_S2> &op2, const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op) {  \
+    return op2.operator REL_OP (ap_private<_AP_W, false>(op));  \
+  } \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op, const ap_private<_AP_W2, _AP_S2> &op2) {  \
+    return (ap_private<1, false>(op)).operator REL_OP (op2);  \
+  }  \
+template<int _AP_W, int _AP_I, bool _AP_S, \
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_private<_AP_W2, _AP_S2> &op2, const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op) {  \
+    return op2.operator REL_OP (ap_private<1,false>(op));  \
+  }
+
+AF_REF_REL_OP_AP_INT(>)
+AF_REF_REL_OP_AP_INT(<)
+AF_REF_REL_OP_AP_INT(>=)
+AF_REF_REL_OP_AP_INT(<=)
+AF_REF_REL_OP_AP_INT(==)
+AF_REF_REL_OP_AP_INT(!=)
+
+// Relational Operators with double
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator == ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator == (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator != ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator != (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator > ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator < (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator >= ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator <= (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator < ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator > (op1);
+}
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE bool operator <= ( double op1, const ap_fixed_base<_AP_W,_AP_I,_AP_S,_AP_Q,_AP_O, _AP_N>& op2) {
+    return op2.operator >= (op1);
+}
+
+#endif /* #ifndef __AESL_GCC_AP_FIXED_H__ */
\ No newline at end of file

hls_2018/router_05/etc/ap_int_sim.h

+/*
+ * Copyright 2012 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AESL_GCC_AP_INT_H__
+#define __AESL_GCC_AP_INT_H__
+
+#ifndef __cplusplus
+#error C++ is required to include this header file
+#endif /* #ifndef __cplusplus */
+
+#undef _AP_DEBUG_
+#include <stdio.h>
+#include <iostream>
+
+// for safety
+#if (defined(_AP_N)|| defined(_AP_C))
+#error One or more of the following is defined: _AP_N, _AP_C. Definition conflicts with their usage as template parameters.
+#endif /* #if (defined(_AP_N)|| defined(_AP_C)) */
+
+// for safety
+#if (defined(_AP_W) || defined(_AP_I) || defined(_AP_S) || defined(_AP_Q) || defined(_AP_O) || defined(_AP_W2) || defined(_AP_I2) || defined(_AP_S2) || defined(_AP_Q2) || defined(_AP_O2))
+#error One or more of the following is defined: _AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2. Definition conflicts with their usage as template parameters.
+#endif /* #if (defined(_AP_W) || defined(_AP_I) || defined(_AP_S) || defined(_AP_Q) || defined(_AP_O) || defined(_AP_W2) || defined(_AP_I2) || defined(_AP_S2) || defined(_AP_Q2) || defined(_AP_O2)) */
+
+//for safety
+#if (defined(_AP_W3) || defined(_AP_S3) || defined(_AP_W4) || defined(_AP_S4))
+#error One or more of the following is defined: _AP_W3, _AP_S3, _AP_W4,_AP_S4. Definition conflicts with their usage as template parameters.
+#endif /* #if (defined(_AP_W3) || defined(_AP_S3) || defined(_AP_W4) || defined(_AP_S4)) */
+
+//for safety
+#if (defined(_AP_W1) || defined(_AP_S1) || defined(_AP_I1) || defined(_AP_T) || defined(_AP_T1) || defined(_AP_T2) || defined(_AP_T3) || defined(_AP_T4))
+#error One or more of the following is defined: _AP_W1, _AP_S1, _AP_I1, _AP_T,  _AP_T1, _AP_T2, _AP_T3, _AP_T4. Definition conflicts with their usage as template parameters.
+#endif /* #if (defined(_AP_W1) || defined(_AP_S1) || defined(_AP_I1) || defined(_AP_T) || defined(_AP_T1) || defined(_AP_T2) || defined(_AP_T3) || defined(_AP_T4)) */
+
+#define __AESL_APDT_IN_SCFLOW__
+#ifndef __AESL_APDT_IN_SCFLOW__
+    #include "etc/ap_private.h"
+#else
+    #include "../etc/ap_private.h"
+#endif /* #ifndef __AESL_APDT_IN_SCFLOW__ */
+
+#ifdef _AP_DEBUG_
+    #define AP_DEBUG(s) s
+#else
+    #define AP_DEBUG(s)
+#endif /* #ifdef _AP_DEBUG_ */
+
+#ifndef __SIMULATION__
+    #define __SIMULATION__
+#endif /* #ifndef __SIMULATION__ */
+
+#if !(defined SYSTEMC_H) && !(defined SYSTEMC_INCLUDED)
+    #ifndef SC_TRN
+        #define SC_TRN AP_TRN
+    #endif /* #ifndef SC_TRN */
+    #ifndef SC_RND
+        #define SC_RND AP_RND
+    #endif /* #ifndef SC_RND */
+    #ifndef SC_TRN_ZERO
+        #define SC_TRN_ZERO AP_TRN_ZERO
+    #endif /* #ifndef SC_TRN_ZERO */
+    #ifndef SC_RND_ZERO
+        #define SC_RND_ZERO AP_RND_ZERO
+    #endif /* #ifndef SC_RND_ZERO */
+    #ifndef SC_RND_INF
+        #define SC_RND_INF AP_RND_INF
+    #endif /* #ifndef SC_RND_INF */
+    #ifndef SC_RND_MIN_INF
+        #define SC_RND_MIN_INF AP_RND_MIN_INF
+    #endif /* #ifndef SC_RND_MIN_INF */
+    #ifndef SC_RND_CONV
+        #define SC_RND_CONV AP_RND_CONV
+    #endif /* #ifndef SC_RND_CONV */
+    #ifndef SC_WRAP
+        #define SC_WRAP AP_WRAP
+    #endif /* #ifndef SC_WRAP */
+    #ifndef SC_SAT
+        #define SC_SAT AP_SAT
+    #endif /* #ifndef SC_SAT */
+    #ifndef SC_SAT_ZERO
+        #define SC_SAT_ZERO AP_SAT_ZERO
+    #endif /* #ifndef SC_SAT_ZERO */
+    #ifndef SC_SAT_SYM
+        #define SC_SAT_SYM AP_SAT_SYM
+    #endif /* #ifndef SC_SAT_SYM */
+    #ifndef SC_WRAP_SM
+        #define SC_WRAP_SM AP_WRAP_SM
+    #endif /* #ifndef SC_WRAP_SM */
+    #ifndef SC_BIN
+        #define SC_BIN 	AP_BIN
+    #endif /* #ifndef SC_BIN */
+    #ifndef SC_OCT
+        #define SC_OCT  AP_OCT
+    #endif /* #ifndef SC_OCT */
+    #ifndef SC_DEC
+        #define SC_DEC AP_DEC
+    #endif /* #ifndef SC_DEC */
+    #ifndef SC_HEX
+        #define SC_HEX AP_HEX
+    #endif /* #ifndef SC_HEX */
+#endif /* #if !(defined SYSTEMC_H) && !(defined SYSTEMC_INCLUDED) */
+#ifndef AP_INT_MAX_W
+#define AP_INT_MAX_W 1024
+#endif
+#define BIT_WIDTH_UPPER_LIMIT (1 << 15)
+#if AP_INT_MAX_W > BIT_WIDTH_UPPER_LIMIT
+#error "Bitwidth exceeds 32768 (1 << 15), the maximum allowed value"
+#endif
+#define MAX_MODE(BITS) ((BITS + 1023) / 1024)
+
+///Forward declaration
+template<int _AP_W, bool _AP_S> struct ap_range_ref;
+template<int _AP_W, bool _AP_S> struct ap_bit_ref;
+
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,
+         ap_o_mode _AP_O, int _AP_N> struct ap_fixed_base;
+template<int _AP_W, int _AP_I, bool _AP_S,
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> struct af_range_ref;
+template<int _AP_W, int _AP_I, bool _AP_S,
+         ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N> struct af_bit_ref;
+template<int _AP_W> class ap_uint;
+
+enum {
+    AP_BIN = 2,
+    AP_OCT = 8,
+    AP_DEC = 10,
+    AP_HEX = 16
+};
+
+///Why to use reference?
+///Because we will operate the original object indirectly by operating the
+///result object directly after concating or part selecting
+
+///Proxy class which allows concatination to be used as rvalue(for reading) and
+//lvalue(for writing)
+
+/// Concatination reference.
+// ----------------------------------------------------------------
+template<int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2>
+struct ap_concat_ref {
+#ifdef _MSC_VER
+    #pragma warning(disable: 4521 4522)
+#endif /* #ifdef _MSC_VER */
+    enum {_AP_WR=_AP_W1+_AP_W2,};
+    _AP_T1& mbv1;
+    _AP_T2& mbv2;
+
+    INLINE ap_concat_ref(const ap_concat_ref<_AP_W1, _AP_T1,
+          _AP_W2, _AP_T2>& ref):
+           mbv1(ref.mbv1), mbv2(ref.mbv2) {}
+
+    INLINE ap_concat_ref(_AP_T1& bv1, _AP_T2& bv2):mbv1(bv1),mbv2(bv2) {}
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref& operator = (const ap_private<_AP_W3,_AP_S3>& val) {
+        ap_private<_AP_W1+_AP_W2, false>  vval(val);
+        int W_ref1=mbv1.length();
+        int W_ref2=mbv2.length();
+        ap_private<_AP_W1,false> mask1(-1);
+        mask1>>=_AP_W1-W_ref1;
+        ap_private<_AP_W2,false> mask2(-1);
+        mask2>>=_AP_W2-W_ref2;
+        mbv1.set(ap_private<_AP_W1,false>((vval>>W_ref2)&mask1));
+        mbv2.set(ap_private<_AP_W2,false>(vval&mask2));
+        return *this;
+    }
+
+    INLINE ap_concat_ref& operator = (unsigned long long val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template<int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+    INLINE ap_concat_ref& operator =
+        (const ap_concat_ref <_AP_W3, _AP_T3, _AP_W4, _AP_T4>&  val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    INLINE ap_concat_ref& operator =
+        (const ap_concat_ref <_AP_W1, _AP_T1, _AP_W2, _AP_T2>&  val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref& operator =(const ap_bit_ref<_AP_W3, _AP_S3>& val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref& operator =(const ap_range_ref<_AP_W3,_AP_S3>& val) {
+        ap_private<_AP_W1+_AP_W2, false> tmpVal(val);
+        return operator =(tmpVal);
+    }
+
+    template<int _AP_W3, int _AP_I3, bool _AP_S3,
+             ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE ap_concat_ref& operator= (const af_range_ref<_AP_W3, _AP_I3, _AP_S3,
+                                    _AP_Q3, _AP_O3, _AP_N3>& val) {
+        return operator = ((const ap_private<_AP_W3, false>)(val));
+    }
+
+    template<int _AP_W3, int _AP_I3, bool _AP_S3,
+             ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE ap_concat_ref& operator= (const ap_fixed_base<_AP_W3, _AP_I3, _AP_S3,
+                                    _AP_Q3, _AP_O3, _AP_N3>& val) {
+        return operator = (val.to_ap_private());
+    }
+
+    template<int _AP_W3, int _AP_I3, bool _AP_S3,
+             ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE ap_concat_ref& operator= (const af_bit_ref<_AP_W3, _AP_I3, _AP_S3,
+                                    _AP_Q3, _AP_O3, _AP_N3>& val) {
+        return operator=((unsigned long long)(bool)(val));
+     }
+
+
+    INLINE operator ap_private<_AP_WR, false> () const {
+        return get();
+    }
+
+    INLINE operator unsigned long long () const {
+         return get().to_uint64();
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_range_ref<_AP_W3, _AP_S3> >
+        operator, (const ap_range_ref<_AP_W3, _AP_S3> &a2) {
+        return ap_concat_ref<_AP_WR, ap_concat_ref,
+                           _AP_W3, ap_range_ref<_AP_W3, _AP_S3> >(*this,
+                           const_cast<ap_range_ref<_AP_W3, _AP_S3> &>(a2));
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_private<_AP_W3, _AP_S3> >
+        operator, (ap_private<_AP_W3, _AP_S3> &a2) {
+          return ap_concat_ref<_AP_WR, ap_concat_ref,
+                               _AP_W3, ap_private<_AP_W3, _AP_S3> >(*this, a2);
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_private<_AP_W3, _AP_S3> >
+        operator, (const ap_private<_AP_W3, _AP_S3> &a2) {
+          return ap_concat_ref<_AP_WR, ap_concat_ref,
+                               _AP_W3, ap_private<_AP_W3, _AP_S3> >(*this,
+                               const_cast<ap_private<_AP_W3, _AP_S3>&>(a2));
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, 1, ap_bit_ref<_AP_W3, _AP_S3> >
+        operator, (const ap_bit_ref<_AP_W3, _AP_S3> &a2) {
+        return ap_concat_ref<_AP_WR, ap_concat_ref,
+                               1, ap_bit_ref<_AP_W3, _AP_S3> >(*this,
+                          const_cast<ap_bit_ref<_AP_W3, _AP_S3> &>(a2));
+    }
+
+    template<int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+    INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3+_AP_W4, ap_concat_ref<_AP_W3,_AP_T3,_AP_W4,_AP_T4> >
+        operator, (const ap_concat_ref<_AP_W3,_AP_T3,_AP_W4,_AP_T4> &a2)
+    {
+        return ap_concat_ref<_AP_WR, ap_concat_ref,
+                               _AP_W3+_AP_W4, ap_concat_ref<_AP_W3,_AP_T3,_AP_W4,
+                               _AP_T4> >(*this, const_cast<ap_concat_ref<_AP_W3,
+                               _AP_T3,_AP_W4, _AP_T4>& >(a2));
+    }
+
+    template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE
+    ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >
+    operator, (const af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3,
+               _AP_O3, _AP_N3> &a2) {
+        return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, af_range_ref<_AP_W3,
+                _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >(*this,
+                const_cast<af_range_ref<_AP_W3,_AP_I3, _AP_S3, _AP_Q3,
+                _AP_O3, _AP_N3>& >(a2));
+    }
+
+    template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3, ap_o_mode _AP_O3, int _AP_N3>
+    INLINE
+    ap_concat_ref<_AP_WR, ap_concat_ref, 1, af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >
+    operator, (const af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3,
+               _AP_O3, _AP_N3> &a2) {
+        return ap_concat_ref<_AP_WR, ap_concat_ref, 1, af_bit_ref<_AP_W3,
+                _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >(*this,
+                const_cast<af_bit_ref<_AP_W3,_AP_I3, _AP_S3,
+                _AP_Q3, _AP_O3, _AP_N3>& >(a2));
+    }
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_private<AP_MAX(_AP_WR,_AP_W3), _AP_S3>
+        operator & (const ap_private<_AP_W3,_AP_S3>& a2) {
+        return get() & a2;
+    }
+
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_private<AP_MAX(_AP_WR,_AP_W3), _AP_S3>
+        operator | (const ap_private<_AP_W3,_AP_S3>& a2) {
+        return get() | a2;
+    }
+
+
+    template<int _AP_W3, bool _AP_S3>
+    INLINE ap_private<AP_MAX(_AP_WR,_AP_W3), _AP_S3>
+        operator ^ (const ap_private<_AP_W3,_AP_S3>& a2) {
+      return ap_private<AP_MAX(_AP_WR,_AP_W3), _AP_S3>(get() ^ a2);
+    }
+
+    INLINE const ap_private<_AP_WR, false> get() const
+    {
+      ap_private<_AP_W1+_AP_W2, false> tmpVal = ap_private<_AP_W1+_AP_W2, false> (mbv1.get());
+      ap_private<_AP_W1+_AP_W2, false> tmpVal2 = ap_private<_AP_W1+_AP_W2, false> (mbv2.get());
+        int W_ref2 = mbv2.length();
+        tmpVal <<= W_ref2;
+        tmpVal |= tmpVal2;
+        return tmpVal;
+    }
+
+    INLINE const ap_private<_AP_WR, false> get() {
+      ap_private<_AP_W1+_AP_W2, false> tmpVal = ap_private<_AP_W1+_AP_W2, false> ( mbv1.get());
+      ap_private<_AP_W1+_AP_W2, false> tmpVal2 = ap_private<_AP_W1+_AP_W2, false> (mbv2.get());
+        int W_ref2 = mbv2.length();
+        tmpVal <<= W_ref2;
+        tmpVal |= tmpVal2;
+        return tmpVal;
+    }
+
+    template <int _AP_W3>
+    INLINE void set(const ap_private<_AP_W3,false> & val) {
+        ap_private<_AP_W1+_AP_W2, false> vval(val);
+        int W_ref1=mbv1.length();
+        int W_ref2=mbv2.length();
+        ap_private<_AP_W1,false> mask1(-1);
+        mask1>>=_AP_W1-W_ref1;
+        ap_private<_AP_W2,false> mask2(-1);
+        mask2>>=_AP_W2-W_ref2;
+        mbv1.set(ap_private<_AP_W1,false>((vval>>W_ref2)&mask1));
+        mbv2.set(ap_private<_AP_W2,false>(vval&mask2));
+    }
+
+    INLINE int length() const {
+        return mbv1.length()+mbv2.length();
+    }
+
+    INLINE std::string to_string(uint8_t radix=2) const {
+        return get().to_string(radix);
+    }
+};
+
+///Proxy class, which allows part selection to be used as rvalue(for reading) and
+//lvalue(for writing)
+
+///Range(slice)  reference
+//------------------------------------------------------------
+template<int _AP_W, bool _AP_S>
+struct ap_range_ref {
+#ifdef _MSC_VER
+    #pragma warning( disable : 4521 4522 )
+#endif /* #ifdef _MSC_VER */
+    ap_private<_AP_W,_AP_S> &d_bv;
+    int l_index;
+    int h_index;
+
+public:
+    INLINE ap_range_ref(const ap_range_ref<_AP_W, _AP_S>& ref):
+         d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {}
+
+    INLINE ap_range_ref(ap_private<_AP_W,_AP_S>* bv, int h, int l):
+        d_bv(*bv),l_index(l),h_index(h) {
+        //if (h < l)
+	  //fprintf(stderr, "Warning! The bits selected will be returned in reverse order\n");
+    }
+
+    INLINE operator ap_private<_AP_W, false> () const {
+        ap_private<_AP_W, false> val(0);
+        if(h_index>=l_index) {
+	  if (_AP_W > 64) {
+            val=d_bv;
+            ap_private<_AP_W,false> mask(-1);
+            mask>>=_AP_W-(h_index-l_index+1);
+            val>>=l_index;
+            val&=mask;
+	  } else {
+	    const static uint64_t mask = (~0ULL>> (64>_AP_W ? (64-_AP_W):0));
+	    val = (d_bv >> l_index) & (mask >>(_AP_W-(h_index-l_index+1)));
+	  }
+        } else {
+            for(int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+                    if((d_bv)[j]) val.set(i);
+        }
+        return val;
+    }
+
+    INLINE operator unsigned long long () const {
+        return to_uint64();
+    }
+
+    template<int _AP_W2,bool _AP_S2>
+    INLINE ap_range_ref& operator =(const ap_private<_AP_W2,_AP_S2>& val) {
+        ap_private<_AP_W,false> vval=ap_private<_AP_W,false>(val);
+        if (l_index>h_index) {
+	        for (int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+	            (vval)[i]? d_bv.set(j):d_bv.clear(j);
+        } else {
+	        if (_AP_W > 64) {
+	          ap_private<_AP_W,false> mask(-1);
+	          if (l_index>0) {
+        	      mask<<=l_index;
+        	      vval<<=l_index;
+        	  }
+	  if(h_index<_AP_W-1)
+	    {
+	      ap_private<_AP_W,false> mask2(-1);
+	      mask2>>=_AP_W-h_index-1;
+	      mask&=mask2;
+	      vval&=mask2;
+	    }
+	  mask.flip();
+	  d_bv&=mask;
+	  d_bv|=vval;
+	} else {
+	  unsigned shift = 64-_AP_W;
+	  uint64_t mask = ~0ULL>>(shift);
+	  if(l_index>0)
+	    {
+	      vval = mask & vval << l_index;
+	      mask = mask & mask << l_index;
+	    }
+	  if(h_index<_AP_W-1)
+	    {
+	      uint64_t mask2 = mask;
+	      mask2 >>= (_AP_W-h_index-1);
+	      mask&=mask2;
+	      vval&=mask2;
+	    }
+	  mask = ~mask;
+	  d_bv&=mask;
+	  d_bv|=vval;
+	}
+      }
+      return *this;
+    }
+
+  INLINE ap_range_ref& operator = (unsigned long long val)
+    {
+        const ap_private<_AP_W,_AP_S> vval=val;
+        return operator = (vval);
+    }
+
+
+    INLINE ap_range_ref& operator =(const ap_range_ref<_AP_W, _AP_S>& val)
+    {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator =(tmpVal);
+    }
+
+
+
+    template<int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+    INLINE ap_range_ref& operator =
+        (const ap_concat_ref <_AP_W3, _AP_T3, _AP_W4, _AP_T4>& val)
+    {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator = (tmpVal);
+    }
+
+    template <int _AP_W3, bool _AP_S3>
+    INLINE ap_range_ref& operator =(const ap_range_ref<_AP_W3,_AP_S3>& val)
+    {
+        const ap_private<_AP_W, false> tmpVal(val);
+        return operator =(tmpVal);
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_range_ref& operator= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((const ap_private<_AP_W2, _AP_S2>)(val));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_range_ref& operator= (const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=(val.to_ap_private());
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_range_ref& operator= (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((unsigned long long)(bool)(val));
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_range_ref& operator= (const ap_bit_ref<_AP_W2, _AP_S2>& val) {
+        return operator=((unsigned long long)(bool)(val));
+    }
+
+    template <int _AP_W2, bool _AP_S2>
+    INLINE
+    ap_concat_ref<_AP_W,ap_range_ref,_AP_W2,ap_range_ref<_AP_W2,_AP_S2> >
+    operator, (const ap_range_ref<_AP_W2,_AP_S2> &a2)
+    {
+        return
+            ap_concat_ref<_AP_W, ap_range_ref, _AP_W2,
+                   ap_range_ref<_AP_W2,_AP_S2> >(*this,
+                   const_cast<ap_range_ref<_AP_W2,_AP_S2>& >(a2));
+    }
+
+
+    template <int _AP_W2, bool _AP_S2>
+    INLINE ap_concat_ref<_AP_W,ap_range_ref,_AP_W2,ap_private<_AP_W2,_AP_S2> >
+    operator , (ap_private<_AP_W2,_AP_S2>& a2)
+    {
+        return
+            ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_private<_AP_W2,_AP_S2> >(*this, a2);
+    }
+
+    INLINE ap_concat_ref<_AP_W,ap_range_ref,_AP_W,ap_private<_AP_W,_AP_S> >
+    operator , (ap_private<_AP_W, _AP_S>& a2)
+    {
+        return
+            ap_concat_ref<_AP_W, ap_range_ref, _AP_W,
+                          ap_private<_AP_W,_AP_S> >(*this, a2);
+    }
+
+
+
+    template <int _AP_W2, bool _AP_S2>
+    INLINE
+    ap_concat_ref<_AP_W,ap_range_ref,1,ap_bit_ref<_AP_W2,_AP_S2> >
+    operator, (const ap_bit_ref<_AP_W2,_AP_S2> &a2)
+    {
+        return
+            ap_concat_ref<_AP_W, ap_range_ref, 1,
+                      ap_bit_ref<_AP_W2,_AP_S2> >(*this, const_cast<ap_bit_ref<
+                      _AP_W2,_AP_S2>& >(a2));
+    }
+
+
+    template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE
+    ap_concat_ref<_AP_W, ap_range_ref, _AP_W2+_AP_W3, ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+    operator, (const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2)
+    {
+        return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2+_AP_W3,
+                       ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this,
+                       const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3,
+                       _AP_T3>& >(a2));
+    }
+
+    template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE
+    ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &a2) {
+        return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, af_range_ref<_AP_W2,
+                _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                const_cast<af_range_ref<_AP_W2,_AP_I2, _AP_S2,
+                _AP_Q2, _AP_O2, _AP_N2>& >(a2));
+    }
+
+    template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE
+    ap_concat_ref<_AP_W, ap_range_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &a2) {
+        return ap_concat_ref<_AP_W, ap_range_ref, 1, af_bit_ref<_AP_W2,
+                _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                const_cast<af_bit_ref<_AP_W2,_AP_I2, _AP_S2,
+                _AP_Q2, _AP_O2, _AP_N2>& >(a2));
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator == (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs==rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator != (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs!=rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator > (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator >= (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs>=rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator < (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<rhs;
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator <= (const ap_range_ref<_AP_W2, _AP_S2>& op2)
+    {
+        ap_private<_AP_W,false> lhs=get();
+        ap_private<_AP_W2,false> rhs=op2.get();
+        return lhs<=rhs;
+    }
+
+
+    template<int _AP_W2>
+    INLINE void set(const ap_private<_AP_W2,false>& val)
+    {
+        ap_private<_AP_W,_AP_S> vval=val;
+        if(l_index>h_index)
+        {
+            for(int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+                    (vval)[i]? d_bv.set(j):d_bv.clear(j);
+        } else {
+	  if (_AP_W>64 ) {
+            ap_private<_AP_W,_AP_S> mask(-1);
+            if(l_index>0)
+	      {
+                ap_private<_AP_W,false> mask1(-1);
+                mask1>>=_AP_W-l_index;
+                mask1.flip();
+                mask=mask1;
+                //vval&=mask1;
+                vval<<=l_index;
+	      }
+            if(h_index<_AP_W-1)
+	      {
+                ap_private<_AP_W,false> mask2(-1);
+                mask2<<=h_index+1;
+                mask2.flip();
+                mask&=mask2;
+                vval&=mask2;
+	      }
+            mask.flip();
+            d_bv&=mask;
+            d_bv|=vval;
+	  } else {
+	    uint64_t mask = ~0ULL >> (64-_AP_W);
+            if(l_index>0)
+	      {
+		uint64_t mask1 = mask;
+		mask1=mask & (mask1>>(_AP_W-l_index));
+		vval =mask&( vval <<l_index);
+		mask=~mask1&mask;
+		//vval&=mask1;
+	      }
+            if(h_index<_AP_W-1) {
+		uint64_t mask2 = ~0ULL >> (64-_AP_W);
+		mask2 = mask &(mask2<<(h_index+1));
+		mask&=~mask2;
+		vval&=~mask2;
+	      }
+            d_bv&=(~mask&(~0ULL >> (64-_AP_W)));
+            d_bv|=vval;
+	  }
+	}
+    }
+
+
+    INLINE ap_private<_AP_W,false> get() const
+    {
+      ap_private<_AP_W,false> val(0);
+      if(h_index<l_index) {
+	for(int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+	  if((d_bv)[j]) val.set(i);
+      } else {
+	val=d_bv;
+	val>>=l_index;
+	if(h_index<_AP_W-1)
+	  {
+	    if (_AP_W <= 64) {
+	      const static uint64_t mask = (~0ULL>> (64>_AP_W ? (64-_AP_W):0));
+	      val &=  (mask>> (_AP_W-(h_index-l_index+1)));
+	    } else {
+	      ap_private<_AP_W,false> mask(-1);
+	      mask>>=_AP_W-(h_index-l_index+1);
+	      val&=mask;
+	    }
+	  }
+      }
+      return val;
+    }
+
+
+  INLINE ap_private<_AP_W,false> get()
+  {
+    ap_private<_AP_W,false> val(0);
+    if(h_index<l_index) {
+      for(int i=0, j=l_index;j>=0&&j>=h_index;j--,i++)
+	if((d_bv)[j]) val.set(i);
+    } else {
+      val=d_bv;
+      val>>=l_index;
+      if(h_index<_AP_W-1)
+	{
+	  if (_AP_W <= 64 ) {
+	    static const uint64_t mask = ~0ULL>> (64>_AP_W ? (64-_AP_W):0);
+	    return val &= ( (mask) >> (_AP_W - (h_index-l_index+1)));
+	  } else {
+	    ap_private<_AP_W,false> mask(-1);
+	    mask>>=_AP_W-(h_index-l_index+1);
+	    val&=mask;
+	  }
+	}
+    }
+    return val;
+  }
+
+
+    INLINE int length() const
+    {
+        return h_index>=l_index?h_index-l_index+1:l_index-h_index+1;
+    }
+
+
+    INLINE int to_int() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_int();
+    }
+
+
+    INLINE unsigned int to_uint() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_uint();
+    }
+
+
+    INLINE long to_long() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_long();
+    }
+
+
+    INLINE unsigned long to_ulong() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_ulong();
+    }
+
+
+    INLINE ap_slong to_int64() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_int64();
+    }
+
+
+    INLINE ap_ulong to_uint64() const
+    {
+        ap_private<_AP_W,false> val=get();
+        return val.to_uint64();
+    }
+
+    INLINE std::string to_string(uint8_t radix=2) const {
+        return get().to_string(radix);
+    }
+
+};
+
+///Proxy class, which allows bit selection to be used as rvalue(for reading) and
+//lvalue(for writing)
+
+///Bit reference
+//--------------------------------------------------------------
+template <int _AP_W, bool _AP_S>
+struct ap_bit_ref {
+#ifdef _MSC_VER
+#pragma warning( disable : 4521 4522 )
+#endif
+    ap_private<_AP_W,_AP_S>& d_bv;
+    int d_index;
+
+public:
+    INLINE ap_bit_ref(const ap_bit_ref<_AP_W, _AP_S>& ref):
+            d_bv(ref.d_bv), d_index(ref.d_index) {}
+
+    INLINE ap_bit_ref(ap_private<_AP_W,_AP_S>& bv, int index=0):
+        d_bv(bv),d_index(index)
+    {
+#ifdef _AP_DEBUG_
+        assert(d_index<_AP_W&&"index out of bound");
+#endif
+    }
+
+
+    INLINE operator bool () const
+    {
+      return d_bv.get_bit(d_index);
+    }
+
+
+    INLINE bool to_bool() const
+    {
+        return operator bool ();
+    }
+
+
+    INLINE ap_bit_ref& operator = (unsigned long long val)
+    {
+        if(val)
+            d_bv.set(d_index);
+        else
+            d_bv.clear(d_index);
+        return *this;
+    }
+
+
+#if 0
+    INLINE ap_bit_ref& operator = (bool val)
+    {
+        if(val)
+            d_bv.set(d_index);
+        else
+            d_bv.clear(d_index);
+        return *this;
+    }
+#endif
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_bit_ref& operator =(const ap_private<_AP_W2,_AP_S2>& val)
+    {
+        return operator =((unsigned long long)(val != 0));
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_bit_ref& operator =(const ap_bit_ref<_AP_W2,_AP_S2>& val)
+    {
+        return operator =((unsigned long long)(bool)val);
+    }
+
+    INLINE ap_bit_ref& operator =(const ap_bit_ref<_AP_W,_AP_S>& val)
+    {
+        return operator =((unsigned long long)(bool)val);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_bit_ref& operator =(const ap_range_ref<_AP_W2,_AP_S2>&  val)
+    {
+        return operator =((unsigned long long)(bool) val);
+    }
+
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_bit_ref& operator= (const af_range_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((const ap_private<_AP_W2, false>)(val));
+    }
+
+    template<int _AP_W2, int _AP_I2, bool _AP_S2,
+             ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE ap_bit_ref& operator= (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                                    _AP_Q2, _AP_O2, _AP_N2>& val) {
+        return operator=((unsigned long long)(bool)(val));
+    }
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_bit_ref& operator= (const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) {
+        return operator=((const ap_private<_AP_W2 + _AP_W3, false>)(val));
+    }
+
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_private<_AP_W2,_AP_S2> >
+    operator , (ap_private<_AP_W2, _AP_S2>& a2)
+     {
+        return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_private<_AP_W2,_AP_S2> >(*this, a2);
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_range_ref<_AP_W2,_AP_S2> >
+    operator, (const ap_range_ref<_AP_W2, _AP_S2> &a2)
+    {
+        return
+            ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_range_ref<_AP_W2,_AP_S2> >(*this,
+                    const_cast<ap_range_ref<_AP_W2, _AP_S2> &>(a2));
+    }
+
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref<_AP_W2,_AP_S2> >
+    operator, (const ap_bit_ref<_AP_W2, _AP_S2> &a2)
+    {
+        return
+            ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref<_AP_W2,_AP_S2> >(*this,
+                    const_cast<ap_bit_ref<_AP_W2, _AP_S2> &>(a2));
+    }
+
+
+    INLINE ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref >
+    operator, (const ap_bit_ref &a2)
+    {
+        return
+            ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref >(*this,
+                const_cast<ap_bit_ref&>(a2));
+    }
+
+
+    template<int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+    INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2+_AP_W3, ap_concat_ref<_AP_W2,_AP_T2,_AP_W3,_AP_T3> >
+    operator, (const ap_concat_ref<_AP_W2,_AP_T2,_AP_W3,_AP_T3> &a2)
+    {
+        return
+            ap_concat_ref<1,ap_bit_ref,_AP_W2+_AP_W3,
+                    ap_concat_ref<_AP_W2,_AP_T2,_AP_W3,_AP_T3> >(*this,
+                    const_cast<ap_concat_ref<_AP_W2,_AP_T2,_AP_W3,_AP_T3>& >(a2));
+    }
+
+    template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE
+    ap_concat_ref<1, ap_bit_ref, _AP_W2, af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &a2) {
+        return ap_concat_ref<1, ap_bit_ref, _AP_W2, af_range_ref<_AP_W2,
+                _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                const_cast<af_range_ref<_AP_W2,_AP_I2, _AP_S2, _AP_Q2,
+                _AP_O2, _AP_N2>& >(a2));
+    }
+
+    template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2, int _AP_N2>
+    INLINE
+    ap_concat_ref<1, ap_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+    operator, (const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+               _AP_O2, _AP_N2> &a2) {
+        return ap_concat_ref<1, ap_bit_ref, 1, af_bit_ref<_AP_W2,
+                _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                _AP_Q2, _AP_O2, _AP_N2>& >(a2));
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator == (const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+        return get() == op.get();
+    }
+
+    template<int _AP_W2, bool _AP_S2>
+    INLINE bool operator != (const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+        return get() != op.get();
+    }
+
+
+    INLINE bool get() const
+    {
+        return operator bool ();
+    }
+
+
+    INLINE bool get()
+    {
+        return operator bool ();
+    }
+
+
+    template <int _AP_W3>
+    INLINE void set(const ap_private<_AP_W3, false>& val)
+    {
+        operator = (val);
+    }
+
+    INLINE bool operator ~ () const {
+        bool bit = (d_bv)[d_index];
+        return bit ? false : true;
+    }
+
+    INLINE int length() const { return 1; }
+
+    INLINE std::string to_string() const {
+        bool val = get();
+        return val ? "1" : "0";
+    }
+};
+
+/// Operators mixing Integers with AP_Int
+// ----------------------------------------------------------------
+#if 1
+#define OP_BIN_MIX_INT(BIN_OP, C_TYPE, _AP_WI, _AP_SI, RTYPE)  \
+  template<int _AP_W, bool _AP_S>					\
+  INLINE typename ap_private<_AP_WI,_AP_SI>::template RType<_AP_W,_AP_S>::RTYPE \
+  operator BIN_OP ( C_TYPE i_op, const ap_private<_AP_W,_AP_S> &op) {  \
+    return ap_private<_AP_WI,_AP_SI>(i_op).operator BIN_OP (op);	\
+  }									\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE typename ap_private<_AP_W,_AP_S>::template RType<_AP_WI,_AP_SI>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W,_AP_S> &op, C_TYPE i_op) {	\
+    return op.operator BIN_OP (ap_private<_AP_WI,_AP_SI>(i_op));	\
+  }
+#else
+#define OP_BIN_MIX_INT(BIN_OP, C_TYPE, _AP_WI, _AP_SI, RTYPE)  \
+    template<int _AP_W, bool _AP_S> \
+    INLINE typename ap_private<_AP_WI,_AP_SI>::template RType<_AP_W,_AP_S>::RTYPE \
+    operator BIN_OP ( C_TYPE i_op, const ap_private<_AP_W,_AP_S> &op) {  \
+        return ap_private<_AP_WI,_AP_SI>(i_op).operator BIN_OP (op);  \
+      } \
+    template<int _AP_W, bool _AP_S>   \
+    INLINE typename ap_private<_AP_W,_AP_S>::template RType<_AP_WI,_AP_SI>::RTYPE \
+      operator BIN_OP ( const ap_private<_AP_W,_AP_S> &op, C_TYPE i_op) {  \
+        return op.operator BIN_OP (ap_private<_AP_WI,_AP_SI>(i_op));  \
+    }
+#endif
+#define OP_REL_MIX_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)  \
+  template<int _AP_W, bool _AP_S>					\
+  INLINE bool operator REL_OP ( const ap_private<_AP_W,_AP_S> &op, C_TYPE op2) { \
+    return op.operator REL_OP (ap_private<_AP_W2, _AP_S2>(op2));	\
+  }									\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE bool operator REL_OP ( C_TYPE op2, const ap_private<_AP_W,_AP_S> &op) { \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator REL_OP (op);		\
+  }
+#define OP_ASSIGN_MIX_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)		\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE ap_private<_AP_W,_AP_S> &operator ASSIGN_OP ( ap_private<_AP_W,_AP_S> &op, C_TYPE op2) { \
+    return op.operator ASSIGN_OP (ap_private<_AP_W2,_AP_S2>(op2));	\
+  }
+
+#define OP_BIN_SHIFT_INT(BIN_OP, C_TYPE, _AP_WI, _AP_SI, RTYPE)		\
+  template<int _AP_W, bool _AP_S>					\
+  C_TYPE  operator BIN_OP ( C_TYPE i_op, const ap_private<_AP_W,_AP_S> &op) { \
+    return i_op BIN_OP (op.getVal());					\
+  }									\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE typename ap_private<_AP_W,_AP_S>::template RType<_AP_WI,_AP_SI>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W,_AP_S> &op, C_TYPE i_op) {	\
+    return op.operator BIN_OP (i_op);		\
+  }
+#define OP_ASSIGN_RSHIFT_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)		\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE  ap_private<_AP_W,_AP_S> &operator ASSIGN_OP ( ap_private<_AP_W,_AP_S> &op, C_TYPE op2) { \
+    op = op.operator >> (op2);					\
+    return op;						\
+  }
+#define OP_ASSIGN_LSHIFT_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)		\
+  template<int _AP_W, bool _AP_S>					\
+  INLINE  ap_private<_AP_W,_AP_S> &operator ASSIGN_OP ( ap_private<_AP_W,_AP_S> &op, C_TYPE op2) { \
+    op = op.operator << (op2);					\
+    return op;						\
+  }
+
+#define OPS_MIX_INT(C_TYPE, WI, SI)		\
+  OP_BIN_MIX_INT(*, C_TYPE, WI, SI, mult)	\
+    OP_BIN_MIX_INT(+, C_TYPE, WI, SI, plus)	\
+    OP_BIN_MIX_INT(-, C_TYPE, WI, SI, minus)	\
+    OP_BIN_MIX_INT(/, C_TYPE, WI, SI, div)	\
+    OP_BIN_MIX_INT(%, C_TYPE, WI, SI, mod)	\
+    OP_BIN_MIX_INT(&, C_TYPE, WI, SI, logic)	\
+    OP_BIN_MIX_INT(|, C_TYPE, WI, SI, logic)	\
+    OP_BIN_MIX_INT(^, C_TYPE, WI, SI, logic)	\
+    OP_BIN_SHIFT_INT(>>, C_TYPE, WI, SI, arg1)	\
+    OP_BIN_SHIFT_INT(<<, C_TYPE, WI, SI, arg1)	\
+						\
+    OP_REL_MIX_INT(==, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(!=, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(>, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(>=, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(<, C_TYPE, WI, SI)		\
+    OP_REL_MIX_INT(<=, C_TYPE, WI, SI)		\
+						\
+    OP_ASSIGN_MIX_INT(+=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(-=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(*=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(/=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(%=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(&=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(|=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_MIX_INT(^=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_RSHIFT_INT(>>=, C_TYPE, WI, SI)	\
+    OP_ASSIGN_LSHIFT_INT(<<=, C_TYPE, WI, SI)
+
+
+OPS_MIX_INT(bool, 1, false)
+OPS_MIX_INT(char, 8, true)
+OPS_MIX_INT(signed char, 8, true)
+OPS_MIX_INT(unsigned char, 8, false)
+OPS_MIX_INT(short, 16, true)
+OPS_MIX_INT(unsigned short, 16, false)
+OPS_MIX_INT(int, 32, true)
+OPS_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+OPS_MIX_INT(long, 64, true)
+OPS_MIX_INT(unsigned long, 64, false)
+# else
+OPS_MIX_INT(long, 32, true)
+OPS_MIX_INT(unsigned long, 32, false)
+# endif
+OPS_MIX_INT(ap_slong, 64, true)
+OPS_MIX_INT(ap_ulong, 64, false)
+
+#define OP_BIN_MIX_RANGE(BIN_OP, RTYPE) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_private<_AP_W1,_AP_S1>::template RType<_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_range_ref<_AP_W1,_AP_S1>& op1, const ap_private<_AP_W2,_AP_S2>& op2) { \
+      return ap_private<_AP_W1, false>(op1).operator BIN_OP (op2); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_private<_AP_W1,_AP_S1>::template RType<_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W1,_AP_S1>& op1, const ap_range_ref<_AP_W2,_AP_S2>& op2) { \
+      return op1.operator BIN_OP (ap_private<_AP_W2, false>(op2)); \
+  }
+
+#define OP_REL_MIX_RANGE(REL_OP) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>   \
+  INLINE bool operator REL_OP ( const ap_range_ref<_AP_W1,_AP_S1>& op1, const ap_private<_AP_W2,_AP_S2>& op2) { \
+    return ap_private<_AP_W1,false>(op1).operator REL_OP (op2); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_private<_AP_W1,_AP_S1>& op1, const ap_range_ref<_AP_W2,_AP_S2>& op2) { \
+    return op1.operator REL_OP (op2.operator ap_private<_AP_W2, false>()); \
+  }
+
+#define OP_ASSIGN_MIX_RANGE(ASSIGN_OP) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE ap_private<_AP_W1,_AP_S1>& operator ASSIGN_OP ( ap_private<_AP_W1,_AP_S1>& op1, const ap_range_ref<_AP_W2,_AP_S2>& op2) { \
+    return op1.operator ASSIGN_OP (ap_private<_AP_W2, false>(op2)); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE ap_range_ref<_AP_W1,_AP_S1>& operator ASSIGN_OP (ap_range_ref<_AP_W1,_AP_S1>& op1, ap_private<_AP_W2,_AP_S2>& op2) { \
+    ap_private<_AP_W1, false> tmp(op1); \
+    tmp.operator ASSIGN_OP (op2); \
+    op1 = tmp; \
+    return op1; \
+  }
+
+
+OP_ASSIGN_MIX_RANGE(+=)
+OP_ASSIGN_MIX_RANGE(-=)
+OP_ASSIGN_MIX_RANGE(*=)
+OP_ASSIGN_MIX_RANGE(/=)
+OP_ASSIGN_MIX_RANGE(%=)
+OP_ASSIGN_MIX_RANGE(>>=)
+OP_ASSIGN_MIX_RANGE(<<=)
+OP_ASSIGN_MIX_RANGE(&=)
+OP_ASSIGN_MIX_RANGE(|=)
+OP_ASSIGN_MIX_RANGE(^=)
+
+OP_REL_MIX_RANGE(==)
+OP_REL_MIX_RANGE(!=)
+OP_REL_MIX_RANGE(>)
+OP_REL_MIX_RANGE(>=)
+OP_REL_MIX_RANGE(<)
+OP_REL_MIX_RANGE(<=)
+
+OP_BIN_MIX_RANGE(+, plus)
+OP_BIN_MIX_RANGE(-, minus)
+OP_BIN_MIX_RANGE(*, mult)
+OP_BIN_MIX_RANGE(/, div)
+OP_BIN_MIX_RANGE(%, mod)
+OP_BIN_MIX_RANGE(>>, arg1)
+OP_BIN_MIX_RANGE(<<, arg1)
+OP_BIN_MIX_RANGE(&, logic)
+OP_BIN_MIX_RANGE(|, logic)
+OP_BIN_MIX_RANGE(^, logic)
+
+#define OP_BIN_MIX_BIT(BIN_OP, RTYPE) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_private<1, false>::template RType<_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_bit_ref<_AP_W1,_AP_S1>& op1, const ap_private<_AP_W2,_AP_S2>& op2) { \
+      return ap_private<1, false>(op1).operator BIN_OP (op2); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE typename ap_private<_AP_W1,_AP_S1>::template RType<1,false>::RTYPE \
+  operator BIN_OP ( const ap_private<_AP_W1,_AP_S1>& op1, const ap_bit_ref<_AP_W2,_AP_S2>& op2) { \
+      return op1.operator BIN_OP (ap_private<1, false>(op2)); \
+  }
+
+#define OP_REL_MIX_BIT(REL_OP) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>   \
+  INLINE bool operator REL_OP ( const ap_bit_ref<_AP_W1,_AP_S1>& op1, const ap_private<_AP_W2,_AP_S2>& op2) { \
+    return ap_private<_AP_W1,false>(op1).operator REL_OP (op2); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE bool operator REL_OP ( const ap_private<_AP_W1,_AP_S1>& op1, const ap_bit_ref<_AP_W2,_AP_S2>& op2) { \
+    return op1.operator REL_OP (ap_private<1, false>(op2)); \
+  }
+
+#define OP_ASSIGN_MIX_BIT(ASSIGN_OP) \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE ap_private<_AP_W1,_AP_S1>& operator ASSIGN_OP ( ap_private<_AP_W1,_AP_S1>& op1, ap_bit_ref<_AP_W2,_AP_S2>& op2) { \
+    return op1.operator ASSIGN_OP (ap_private<1, false>(op2)); \
+  } \
+  template<int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2> \
+  INLINE ap_bit_ref<_AP_W1,_AP_S1>& operator ASSIGN_OP ( ap_bit_ref<_AP_W1,_AP_S1>& op1, ap_private<_AP_W2,_AP_S2>& op2) { \
+    ap_private<1, false> tmp(op1); \
+    tmp.operator ASSIGN_OP (op2); \
+    op1 = tmp; \
+    return op1; \
+  }
+
+
+OP_ASSIGN_MIX_BIT(+=)
+OP_ASSIGN_MIX_BIT(-=)
+OP_ASSIGN_MIX_BIT(*=)
+OP_ASSIGN_MIX_BIT(/=)
+OP_ASSIGN_MIX_BIT(%=)
+OP_ASSIGN_MIX_BIT(>>=)
+OP_ASSIGN_MIX_BIT(<<=)
+OP_ASSIGN_MIX_BIT(&=)
+OP_ASSIGN_MIX_BIT(|=)
+OP_ASSIGN_MIX_BIT(^=)
+
+OP_REL_MIX_BIT(==)
+OP_REL_MIX_BIT(!=)
+OP_REL_MIX_BIT(>)
+OP_REL_MIX_BIT(>=)
+OP_REL_MIX_BIT(<)
+OP_REL_MIX_BIT(<=)
+
+OP_BIN_MIX_BIT(+, plus)
+OP_BIN_MIX_BIT(-, minus)
+OP_BIN_MIX_BIT(*, mult)
+OP_BIN_MIX_BIT(/, div)
+OP_BIN_MIX_BIT(%, mod)
+OP_BIN_MIX_BIT(>>, arg1)
+OP_BIN_MIX_BIT(<<, arg1)
+OP_BIN_MIX_BIT(&, logic)
+OP_BIN_MIX_BIT(|, logic)
+OP_BIN_MIX_BIT(^, logic)
+
+#define REF_REL_OP_MIX_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)  \
+  template<int _AP_W, bool _AP_S>   \
+  INLINE bool operator REL_OP ( const ap_range_ref<_AP_W,_AP_S> &op, C_TYPE op2) {  \
+    return (ap_private<_AP_W, false>(op)).operator REL_OP (ap_private<_AP_W2,_AP_S2>(op2));  \
+  }  \
+  template<int _AP_W, bool _AP_S> \
+  INLINE bool operator REL_OP ( C_TYPE op2, const ap_range_ref<_AP_W,_AP_S> &op) {  \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator REL_OP (ap_private<_AP_W, false>(op));  \
+  } \
+  template<int _AP_W, bool _AP_S>   \
+  INLINE bool operator REL_OP ( const ap_bit_ref<_AP_W,_AP_S> &op, C_TYPE op2) {  \
+    return (bool(op)) REL_OP op2;  \
+  }  \
+  template<int _AP_W, bool _AP_S> \
+  INLINE bool operator REL_OP ( C_TYPE op2, const ap_bit_ref<_AP_W,_AP_S> &op) {  \
+    return op2 REL_OP (bool(op));  \
+  } \
+  template<int _AP_W, typename _AP_T, int _AP_W1, typename _AP_T1>   \
+  INLINE bool operator REL_OP ( const ap_concat_ref<_AP_W,_AP_T, _AP_W1, _AP_T1> &op, C_TYPE op2) {  \
+    return (ap_private<_AP_W + _AP_W1, false>(op)).operator REL_OP (ap_private<_AP_W2,_AP_S2>(op2));  \
+  }  \
+  template<int _AP_W, typename _AP_T, int _AP_W1, typename _AP_T1>   \
+  INLINE bool operator REL_OP ( C_TYPE op2, const ap_concat_ref<_AP_W,_AP_T, _AP_W1, _AP_T1> &op) {  \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator REL_OP (ap_private<_AP_W + _AP_W1, false>(op));  \
+  }
+
+#define REF_REL_MIX_INT(C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(>, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(<, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(>=, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(<=, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(==, C_TYPE, _AP_WI, _AP_SI) \
+REF_REL_OP_MIX_INT(!=, C_TYPE, _AP_WI, _AP_SI)
+
+REF_REL_MIX_INT(bool, 1, false)
+REF_REL_MIX_INT(char, 8, true)
+REF_REL_MIX_INT(signed char, 8, true)
+REF_REL_MIX_INT(unsigned char, 8, false)
+REF_REL_MIX_INT(short, 16, true)
+REF_REL_MIX_INT(unsigned short, 16, false)
+REF_REL_MIX_INT(int, 32, true)
+REF_REL_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+REF_REL_MIX_INT(long, 64, true)
+REF_REL_MIX_INT(unsigned long, 64, false)
+# else
+REF_REL_MIX_INT(long, 32, true)
+REF_REL_MIX_INT(unsigned long, 32, false)
+# endif
+REF_REL_MIX_INT(ap_slong, 64, true)
+REF_REL_MIX_INT(ap_ulong, 64, false)
+
+#define REF_BIN_OP_MIX_INT(BIN_OP, RTYPE, C_TYPE, _AP_W2, _AP_S2)  \
+  template<int _AP_W, bool _AP_S>   \
+  INLINE typename ap_private<_AP_W, false>::template RType<_AP_W2,_AP_S2>::RTYPE \
+  operator BIN_OP ( const ap_range_ref<_AP_W,_AP_S> &op, C_TYPE op2) {  \
+    return (ap_private<_AP_W, false>(op)).operator BIN_OP (ap_private<_AP_W2,_AP_S2>(op2));  \
+  }  \
+  template<int _AP_W, bool _AP_S> \
+  INLINE typename ap_private<_AP_W2, _AP_S2>::template RType<_AP_W,false>::RTYPE \
+  operator BIN_OP ( C_TYPE op2, const ap_range_ref<_AP_W,_AP_S> &op) {  \
+    return ap_private<_AP_W2,_AP_S2>(op2).operator BIN_OP (ap_private<_AP_W, false>(op));  \
+  }
+
+#define REF_BIN_MIX_INT(C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(+, plus, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(-, minus, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(*, mult, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(/, div, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(%, mod, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(>>, arg1, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(<<, arg1, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(&, logic, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(|, logic, C_TYPE, _AP_WI, _AP_SI) \
+REF_BIN_OP_MIX_INT(^, logic, C_TYPE, _AP_WI, _AP_SI)
+
+REF_BIN_MIX_INT(bool, 1, false)
+REF_BIN_MIX_INT(char, 8, true)
+REF_BIN_MIX_INT(signed char, 8, true)
+REF_BIN_MIX_INT(unsigned char, 8, false)
+REF_BIN_MIX_INT(short, 16, true)
+REF_BIN_MIX_INT(unsigned short, 16, false)
+REF_BIN_MIX_INT(int, 32, true)
+REF_BIN_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+REF_BIN_MIX_INT(long, 64, true)
+REF_BIN_MIX_INT(unsigned long, 64, false)
+#else
+REF_BIN_MIX_INT(long, 32, true)
+REF_BIN_MIX_INT(unsigned long, 32, false)
+#endif
+REF_BIN_MIX_INT(ap_slong, 64, true)
+REF_BIN_MIX_INT(ap_ulong, 64, false)
+
+#define REF_BIN_OP(BIN_OP, RTYPE) \
+template<int _AP_W, bool _AP_S, int _AP_W2, bool _AP_S2> \
+INLINE typename ap_private<_AP_W, false>::template RType<_AP_W2, false>::RTYPE \
+operator BIN_OP (const ap_range_ref<_AP_W,_AP_S> &lhs, const ap_range_ref<_AP_W2,_AP_S2> &rhs) {  \
+  return ap_private<_AP_W,false>(lhs).operator BIN_OP (ap_private<_AP_W2, false>(rhs));  \
+}
+
+REF_BIN_OP(+, plus)
+REF_BIN_OP(-, minus)
+REF_BIN_OP(*, mult)
+REF_BIN_OP(/, div)
+REF_BIN_OP(%, mod)
+REF_BIN_OP(>>, arg1)
+REF_BIN_OP(<<, arg1)
+REF_BIN_OP(&, logic)
+REF_BIN_OP(|, logic)
+REF_BIN_OP(^, logic)
+
+#if 1
+#define CONCAT_OP_MIX_INT(C_TYPE, _AP_WI, _AP_SI) \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private< _AP_W +  _AP_WI, false > \
+  operator, (const ap_private<_AP_W, _AP_S> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + _AP_W, false> val(op2); \
+  ap_private<_AP_WI + _AP_W, false> ret(op1); \
+  ret <<= _AP_WI; \
+  if (_AP_SI) { \
+      val <<= _AP_W; val >>= _AP_W; \
+  }\
+  ret |= val; \
+  return ret;\
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private< _AP_W +  _AP_WI, false > \
+  operator, (C_TYPE op1, const ap_private<_AP_W, _AP_S>& op2)  { \
+  ap_private<_AP_WI + _AP_W, false> val(op1); \
+  ap_private<_AP_WI + _AP_W, false> ret(op2); \
+  if (_AP_S) { \
+     ret <<= _AP_WI; ret >>= _AP_WI; \
+  } \
+  ret |= val << _AP_W; \
+  return ret; \
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private< _AP_W +  _AP_WI, false > \
+  operator, (const ap_range_ref<_AP_W, _AP_S> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + _AP_W, false> val(op2); \
+  ap_private<_AP_WI + _AP_W, false> ret(op1); \
+  ret <<= _AP_WI; \
+  if (_AP_SI) { \
+      val <<= _AP_W; val >>= _AP_W; \
+  } \
+  ret |= val; \
+  return ret; \
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private< _AP_W +  _AP_WI, false > \
+  operator, (C_TYPE op1, const ap_range_ref<_AP_W, _AP_S> &op2)  { \
+  ap_private<_AP_WI + _AP_W, false> val(op1); \
+  ap_private<_AP_WI + _AP_W, false> ret(op2); \
+  int len = op2.length(); \
+  val <<= len; \
+  ret |= val; \
+  return ret; \
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private<_AP_WI + 1, false > \
+  operator, (const ap_bit_ref<_AP_W, _AP_S> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + 1, false> val(op2); \
+  val[_AP_WI] = op1; \
+  return val; \
+} \
+template<int _AP_W, bool _AP_S> \
+INLINE \
+ap_private<_AP_WI + 1, false > \
+  operator, (C_TYPE op1, const ap_bit_ref<_AP_W, _AP_S> &op2)  { \
+  ap_private<_AP_WI + 1, false> val(op1); \
+  val <<= 1; \
+  val[0] = op2; \
+  return val; \
+} \
+template<int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2> \
+INLINE \
+ap_private<_AP_W + _AP_W2 + _AP_WI, false > \
+   operator, (const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op1, C_TYPE op2) {\
+   ap_private<_AP_WI + _AP_W + _AP_W2, _AP_SI> val(op2);\
+   ap_private<_AP_WI + _AP_W + _AP_W2, _AP_SI> ret(op1);\
+   if (_AP_SI) { \
+       val <<= _AP_W + _AP_W2; val >>= _AP_W + _AP_W2; \
+   } \
+   ret <<= _AP_WI; \
+   ret |= val; \
+   return ret; \
+}\
+template<int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2> \
+INLINE \
+ap_private<_AP_W + _AP_W2 + _AP_WI, false > \
+   operator, (C_TYPE op1, const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op2) {\
+   ap_private<_AP_WI + _AP_W + _AP_W2, _AP_SI> val(op1);\
+   ap_private<_AP_WI + _AP_W + _AP_W2, _AP_SI> ret(op2);\
+   int len = op2.length(); \
+   val <<= len; \
+   ret |= val;\
+   return ret; \
+}\
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, \
+         int _AP_N > \
+INLINE \
+ap_private< _AP_W + _AP_WI, false > \
+  operator, (const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + _AP_W, false> val(op2); \
+  ap_private<_AP_WI + _AP_W, false> ret(op1); \
+  if (_AP_SI) { \
+      val <<= _AP_W; val >>= _AP_W; \
+  }\
+  ret <<= _AP_WI; \
+  ret |= val; \
+  return ret; \
+} \
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, \
+         int _AP_N > \
+INLINE \
+ap_private< _AP_W + _AP_WI, false > \
+  operator, (C_TYPE op1, const af_range_ref<_AP_W, _AP_I, _AP_S, \
+             _AP_Q, _AP_O, _AP_N> &op2) { \
+  ap_private<_AP_WI + _AP_W, false> val(op1); \
+  ap_private<_AP_WI + _AP_W, false> ret(op2); \
+  int len = op2.length(); \
+  val <<= len; \
+  ret |= val; \
+  return ret; \
+} \
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, \
+         int _AP_N > \
+INLINE \
+ap_private< 1 + _AP_WI, false> \
+  operator, (const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, \
+             _AP_N> &op1, C_TYPE op2) { \
+  ap_private<_AP_WI + 1, _AP_SI> val(op2); \
+  val[_AP_WI] = op1; \
+  return val; \
+} \
+template<int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, \
+         int _AP_N > \
+INLINE \
+ap_private< 1 + _AP_WI, false> \
+  operator, (C_TYPE op1, const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q,\
+        _AP_O, _AP_N> &op2) { \
+  ap_private<_AP_WI + 1, _AP_SI> val(op1); \
+  val <<= 1; \
+  val[0] = op2; \
+  return val; \
+}
+
+CONCAT_OP_MIX_INT(bool, 1, false)
+CONCAT_OP_MIX_INT(char, 8, true)
+CONCAT_OP_MIX_INT(signed char, 8, true)
+CONCAT_OP_MIX_INT(unsigned char, 8, false)
+CONCAT_OP_MIX_INT(short, 16, true)
+CONCAT_OP_MIX_INT(unsigned short, 16, false)
+CONCAT_OP_MIX_INT(int, 32, true)
+CONCAT_OP_MIX_INT(unsigned int, 32, false)
+# if defined __x86_64__
+CONCAT_OP_MIX_INT(long, 64, true)
+CONCAT_OP_MIX_INT(unsigned long, 64, false)
+# else
+CONCAT_OP_MIX_INT(long, 32, true)
+CONCAT_OP_MIX_INT(unsigned long, 32, false)
+# endif
+CONCAT_OP_MIX_INT(ap_slong, 64, true)
+CONCAT_OP_MIX_INT(ap_ulong, 64, false)
+#endif
+
+#if 1
+#define CONCAT_SHIFT_MIX_INT(C_TYPE, op) \
+template<int _AP_W, typename _AP_T, int _AP_W1, typename _AP_T1>   \
+INLINE ap_uint<_AP_W+_AP_W1> operator op (const ap_concat_ref<_AP_W, _AP_T, _AP_W1, _AP_T1> lhs, C_TYPE rhs) { \
+  return ((ap_uint<_AP_W+_AP_W1>)lhs.get()) op ((int)rhs); \
+}
+
+CONCAT_SHIFT_MIX_INT(long, <<)
+CONCAT_SHIFT_MIX_INT(unsigned long, <<)
+CONCAT_SHIFT_MIX_INT(unsigned int, <<)
+CONCAT_SHIFT_MIX_INT(ap_ulong, <<)
+CONCAT_SHIFT_MIX_INT(ap_slong, <<)
+CONCAT_SHIFT_MIX_INT(long, >>)
+CONCAT_SHIFT_MIX_INT(unsigned long, >>)
+CONCAT_SHIFT_MIX_INT(unsigned int, >>)
+CONCAT_SHIFT_MIX_INT(ap_ulong, >>)
+CONCAT_SHIFT_MIX_INT(ap_slong, >>)
+#endif
+
+#if defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED)
+template<int _AP_W, bool _AP_S>
+INLINE void sc_trace(sc_core::sc_trace_file *tf, const ap_private<_AP_W, _AP_S> &op,
+                     const std::string &name) {
+    if (tf)
+        tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+#endif
+
+template<int _AP_W, bool _AP_S>
+INLINE std::ostream& operator<<(std::ostream& out, const ap_private<_AP_W,_AP_S> &op)
+{
+  ap_private<_AP_W, _AP_S> v=op;
+    const std::ios_base::fmtflags basefield = out.flags() & std::ios_base::basefield;
+    unsigned radix = (basefield == std::ios_base::hex) ? 16 :
+                     ((basefield == std::ios_base::oct) ? 8 : 10);
+    std::string str=v.toString(radix,_AP_S);
+    out<<str;
+    return out;
+
+}
+
+template<int _AP_W, bool _AP_S>
+INLINE std::istream& operator >> (std::istream& in, ap_private<_AP_W,_AP_S> &op)
+{
+    std::string str;
+    in >> str;
+    op = ap_private<_AP_W, _AP_S>(str.c_str());
+    return in;
+
+}
+
+template<int _AP_W, bool _AP_S>
+INLINE std::ostream& operator<<(std::ostream& out, const ap_range_ref<_AP_W,_AP_S> &op)
+{
+    return operator<<(out, ap_private<_AP_W, _AP_S>(op));
+}
+
+template<int _AP_W, bool _AP_S>
+INLINE std::istream& operator >> (std::istream& in, ap_range_ref<_AP_W,_AP_S> &op)
+{
+    return operator>>(in, ap_private<_AP_W, _AP_S>(op));;
+}
+
+template<int _AP_W, bool _AP_S>
+INLINE void print(const ap_private<_AP_W,_AP_S> &op, bool fill=true )
+{
+    ap_private<_AP_W, _AP_S> v=op;
+    uint32_t ws=v.getNumWords();
+    const uint64_t *ptr=v.getRawData();
+    int i=ws-1;
+#if 0
+    if(fill)
+        printf("%016llx",*(ptr+i));
+    else
+        printf("%llx",*(ptr+i));
+#else
+//match SystemC output
+    if(_AP_W%64 != 0) {
+        uint32_t offset=_AP_W%64;
+        uint32_t count=(offset+3)/4;
+        int64_t data=*(ptr+i);
+        if(_AP_S)
+            data=(data<<(64-offset))>>(64-offset);
+        else
+            count=(offset+4)/4;
+        while(count-->0)
+            printf("%llx",(data>>(count*4))&0xf);
+    } else {
+        if(_AP_S==false)
+            printf("0");
+        printf("%016llx",*(ptr+i));
+    }
+#endif
+    for(--i;i>=0;i--)
+        printf("%016llx",*(ptr+i));
+    printf("\n");
+
+}
+#endif /* #ifndef __AESL_GCC_AP_INT_H__ */
\ No newline at end of file

hls_2018/router_05/main.cpp

+/**
+ * main.cpp
+ *
+ * for Vivado HLS
+ */
+
+#ifdef SOFTWARE
+#include "ap_int.h"
+#else
+#include <ap_int.h>
+#endif
+
+#ifdef CALCTIME
+#include <stdio.h>
+#include <time.h>
+#endif
+
+#include "router.hpp"
+
+#define PRINT_SOLUTION
+
+
+int main(int argc, char *argv[]) {
+    using namespace std;
+
+    // Test data // 
+    // NL_Q00.txt
+    //char boardstr[BOARDSTR_SIZE] = "X10Y05Z3L0000107041L0004107002L0102102021L0900100003";
+    // NL_Q06.txt
+    char boardstr[BOARDSTR_SIZE] = "X10Y18Z2L0900109002L0901105012L0902103052L0903103062L0904100102L0905106012L0906109022L0717109102L0808109112L0017209172L0401200072L0912208152L0009201092L0709209092L0901206052L0309204092L0701209072L0101201022L0011202152L0016202162";
+    // NL_Q08.txt
+    //char boardstr[BOARDSTR_SIZE] = "X17Y20Z2L0000103022L1603115052L0916107032L0302108012L1104111042L1002100002L0919116162L1616113182L1001115012L0500201182L1603213152L0600210022";
+    char boardstr_high[BOARDSTR_SIZE] = {};
+
+    // Read boardstr from command line
+    if (1 < argc) {
+        // From stdin
+        if(argv[1][0]!='X')
+        {
+            char* c_p=fgets(boardstr, BOARDSTR_SIZE, stdin);
+            int length=strlen(c_p);
+            boardstr[length-1]=0;
+        }
+        else
+        {
+            strcpy(boardstr, argv[1]);
+        }
+    }
+
+    // Seed value
+    int seed = 12345;
+    if (2 < argc) {
+        seed = atoi(argv[2]);
+    }
+
+#ifdef PRINT_SOLUTION
+    int size_x = (boardstr[1] - '0') * 10 + (boardstr[2] - '0');
+    int size_y = (boardstr[4] - '0') * 10 + (boardstr[5] - '0');
+    int size_z = (boardstr[7] - '0');
+#endif
+
+    // Solver
+    ap_int<32> status;
+    clock_t clock_start, clock_done;
+    clock_start = clock();
+    bool result = pynqrouter(boardstr, boardstr_high, seed, &status);
+    clock_done = clock();
+    if (result) {
+        cout << endl << "Test Passed!" << endl;
+    } else {
+        cout << endl << "Test Failed!" << endl;
+    }
+    cout << "status = " << (int)status << endl;
+    cout << "elapsed = " << ((double)(clock_done - clock_start) / CLOCKS_PER_SEC) << endl << endl;
+
+#ifdef PRINT_SOLUTION
+    cout << "SOLUTION" << endl;
+    cout << "========" << endl;
+    cout << "SIZE " << size_x << "X" << size_y << "X" << size_z << endl;
+    for (int z = 0; z < size_z; z++) {
+        cout << "LAYER " << (z + 1) << endl;
+        for (int y = 0; y < size_y; y++) {
+            for (int x = 0; x < size_x; x++) {
+                if (x != 0) {
+                    cout << ",";
+                }
+                int i = ((x * MAX_WIDTH + y) << BITWIDTH_Z) | z;
+                unsigned int num = (unsigned char)(boardstr[i]) + ((unsigned char)(boardstr_high[i]) << 8);
+                cout << setfill('0') << setw(5) << right << num;
+                //cout << (unsigned int)(unsigned char)(boardstr[i]);
+            }
+            cout << endl;
+        }
+    }
+#endif
+
+    return 0;
+}
+

hls_2018/router_05/router.cpp

+/**
+ * router.cpp
+ *
+ * for Vivado HLS
+*/
+
+#ifdef SOFTWARE
+#include "ap_int.h"
+#else
+#include <ap_int.h>
+#endif
+
+#include "./router.hpp"
+
+
+
+static ap_uint<32> lfsr;
+
+void lfsr_random_init(ap_uint<32> seed) {
+
+    lfsr = seed;
+}
+
+ap_uint<32> lfsr_random() {
+
+    bool b_32 = lfsr.get_bit(32-32);
+    bool b_22 = lfsr.get_bit(32-22);
+    bool b_2 = lfsr.get_bit(32-2);
+    bool b_1 = lfsr.get_bit(32-1);
+    bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
+    lfsr = lfsr >> 1;
+    lfsr.set_bit(31, new_bit);
+
+    return lfsr.to_uint();
+}
+
+
+
+// Global values
+static ap_uint<7> size_x;    // X
+static ap_uint<7> size_y;    // Y
+static ap_uint<4> size_z;    // Z
+
+static ap_uint<LINE_BIT> line_num = 0; // #Lines
+
+bool pynqrouter(char boardstr[BOARDSTR_SIZE], char boardstr_high[BOARDSTR_SIZE], ap_uint<32> seed, ap_int<32> *status) {
+#pragma HLS INTERFACE s_axilite port=boardstr bundle=AXI4LS
+#pragma HLS INTERFACE s_axilite port=boardstr_high bundle=AXI4LS
+#pragma HLS INTERFACE s_axilite port=seed bundle=AXI4LS
+#pragma HLS INTERFACE s_axilite port=status bundle=AXI4LS
+#pragma HLS INTERFACE s_axilite port=return bundle=AXI4LS
+
+    // status(0:Solved, 1:Not solved)
+    *status = -1;
+
+    // board
+    ap_int<LINE_BIT+1> board[MAX_CELLS]; // -1024 ~ 1023 (Negative values mean terminals)
+    INIT_BOARD_ARRAY:
+    for (ap_uint<CELL_BIT> i = 0; i < (ap_uint<CELL_BIT>)(BOARDSTR_SIZE); i++) {
+        board[i] = 0;
+    }
+
+
+    // ================================
+    // (Step.0) Initialization (BEGIN)
+    // ================================
+
+    // Note: Loop counter -> need an extra bit (for condition determination)
+
+    /// Parse ///
+    size_x = (boardstr[1] - '0') * 10 + (boardstr[2] - '0');
+    size_y = (boardstr[4] - '0') * 10 + (boardstr[5] - '0');
+    size_z = (boardstr[7] - '0');
+
+    INIT_BOARDS:
+    for (ap_uint<CELL_BIT> idx = 8; idx < (ap_uint<CELL_BIT>)(BOARDSTR_SIZE); idx+=11) {
+
+    	// NULL-terminated
+        if (boardstr[idx] == 0) break;
+
+        line_num++;
+
+        // Start & Goal of each line
+        ap_uint<7> s_x = (boardstr[idx+1] - '0') * 10 + (boardstr[idx+2] - '0');
+        ap_uint<7> s_y = (boardstr[idx+3] - '0') * 10 + (boardstr[idx+4] - '0');
+        ap_uint<3> s_z = (boardstr[idx+5] - '0') - 1;
+        ap_uint<7> g_x = (boardstr[idx+6] - '0') * 10 + (boardstr[idx+7] - '0');
+        ap_uint<7> g_y = (boardstr[idx+8] - '0') * 10 + (boardstr[idx+9] - '0');
+        ap_uint<3> g_z = (boardstr[idx+10] - '0') - 1;
+
+        ap_uint<CELL_BIT> start_id = (((ap_uint<CELL_BIT>)s_x * MAX_WIDTH + (ap_uint<CELL_BIT>)s_y) << BITWIDTH_Z) | (ap_uint<CELL_BIT>)s_z;
+        ap_uint<CELL_BIT> goal_id  = (((ap_uint<CELL_BIT>)g_x * MAX_WIDTH + (ap_uint<CELL_BIT>)g_y) << BITWIDTH_Z) | (ap_uint<CELL_BIT>)g_z;
+        board[start_id] = -line_num;
+        board[goal_id]  = -line_num;
+    }
+
+    // For each line
+    ap_uint<LINE_BIT> connected_line_num = 0;
+    bool connected[MAX_LINES];
+    INIT_CONNECTED:
+    for (ap_uint<LINE_BIT> i = 1; i <= (ap_uint<LINE_BIT>)(line_num); i++) {
+        connected[i] = false;
+    }
+
+    lfsr_random_init(seed);
+
+    // ================================
+    // (Step.0) Initialization (END)
+    // ================================
+
+	
+    // ================================
+    // (Step.2) Rip-up Routing (BEGIN)
+    // ================================
+
+#ifdef DEBUG_PRINT
+    cout << "Routing ..." << endl;
+#endif
+
+    bool solved = false;
+
+    ROUTING:
+    for (ap_uint<16> round = 0; round < 32768 ; round++) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=32768
+
+        // Target line
+        ap_uint<LINE_BIT> target = lfsr_random() % line_num + 1;
+
+#ifdef DEBUG_PRINT
+        cout << "(round " << round << ") LINE #" << (int)target << " " << lfsr_random() << endl;
+#endif
+
+        if (connected[target]) continue;
+
+        if (connectable(board, target, 0)) {
+            connected[target] = true; connected_line_num++;
+        }
+        else {
+            ap_uint<16> j;
+            for (j = 0; j < 10000; j++) {
+
+                // Ripped-up line
+                ap_uint<CELL_BIT> rip_up = lfsr_random() % line_num + 1;
+                if (connectable(board, target, rip_up)) {
+                    connected[target] = true;
+                    connected[rip_up] = false;
+                    break;
+                }
+            }
+            if (j == 10000) break;
+        }
+        if (connected_line_num == line_num) {
+            solved = true;
+            break;
+        }
+    }
+
+    // Not solved
+    if (!solved) {
+        *status = 1;  return false;
+    }
+
+    // ================================
+    // (Step.2) Rip-up Routing (END)
+    // ================================
+
+
+    // ================================
+    // (Step.3) Output (BEGIN)
+    // ================================
+
+#ifdef DEBUG_PRINT
+    cout << "Output ..." << endl;
+#endif
+
+    // Init: Blank = 0
+    OUTPUT_INIT:
+    for (ap_uint<CELL_BIT> i = 0; i < (ap_uint<CELL_BIT>)(MAX_CELLS); i++) {
+
+        if (board[i] < 0) {
+            boardstr[i] = (unsigned char)(((-1) * board[i]));
+            boardstr_high[i] = (unsigned char)(((-1) * board[i]) >> 8);
+        }
+        else {
+            boardstr[i] = (unsigned char)((board[i]));
+            boardstr_high[i] = (unsigned char)((board[i]) >> 8);
+        }
+    }
+
+    // ================================
+    // (Step.3) Output (END)
+    // ================================
+
+    *status = 0;  return true;
+}
+
+
+// ================================ //
+// For Routing
+// ================================ //
+
+bool inside_board(ap_uint<CELL_BIT> cell_id) {
+
+    ap_uint<13> cell_xy = (ap_uint<13>)(cell_id >> BITWIDTH_Z);
+    ap_uint<7> cell_x = (ap_uint<7>)(cell_xy / MAX_WIDTH);
+    ap_uint<7> cell_y = (ap_uint<7>)(cell_xy - cell_x * MAX_WIDTH);
+    ap_uint<3> cell_z = (ap_uint<3>)(cell_id & BITMASK_Z);
+
+    bool ret = false;
+    if (cell_x < size_x && cell_y < size_y && cell_z < size_z) {
+        ret = true;
+    }
+    else {
+        ret = false;
+    }
+
+    return ret;
+}
+
+bool connectable(ap_int<LINE_BIT+1> board[MAX_CELLS], ap_uint<LINE_BIT> target, ap_uint<LINE_BIT> rip_up) {
+
+    ap_uint<2> avail[MAX_CELLS];
+    ap_uint<CELL_BIT> prev[MAX_CELLS];
+
+    ap_uint<CELL_BIT> start_id = 65535, goal_id = 65535;
+    for (ap_uint<CELL_BIT> i = 0; i < (ap_uint<CELL_BIT>)(MAX_CELLS); i++) {
+
+        if (!inside_board(i)) continue;
+
+        prev[i] = 65535; // init.
+
+        if (board[i] == target * (-1)) {
+            if (start_id == 65535) {
+                start_id = i;
+                avail[i] = 3;
+            }
+            else {
+                goal_id = i;
+                avail[i] = 0;
+            }
+        }
+        else if (board[i] == 0 || board[i] == rip_up || board[i] == target) {
+            avail[i] = 1;
+        }
+        else {
+            avail[i] = 0;
+        }
+    }
+
+    bool try_connect = available(avail, prev, start_id, goal_id);
+    if (try_connect) {
+        if (rip_up > 0) {
+            remove_line(board, rip_up);
+        }
+        // Connect line for target
+        ap_uint<CELL_BIT> id = prev[goal_id];
+        BACKTRACK:
+        while (id != start_id) {
+            board[id] = target; id = prev[id];
+        }
+    }
+
+    return try_connect;
+}
+
+void remove_line(ap_int<LINE_BIT+1> board[MAX_CELLS], ap_uint<LINE_BIT> rip_up) {
+
+    for (ap_uint<CELL_BIT> i = 0; i < (ap_uint<CELL_BIT>)(MAX_CELLS); i++) {
+
+        if (!inside_board(i)) continue;
+        if (board[i] == rip_up) board[i] = 0;
+    }
+}
+
+bool available(ap_uint<2> avail[MAX_CELLS], ap_uint<CELL_BIT> prev[MAX_CELLS], ap_uint<CELL_BIT> start_id, ap_uint<CELL_BIT> goal_id) {
+
+    // Priority queue (Circular list)
+    ap_uint<PQ_BIT> top = 1, bottom = 0;
+    bool is_empty = true;
+    ap_uint<CELL_BIT> qu_nodes[MAX_PQ];
+
+    // Point of goal terminal
+    ap_uint<13> goal_xy = (ap_uint<13>)(goal_id >> BITWIDTH_Z);
+    ap_uint<7> goal_x = (ap_uint<7>)(goal_xy / MAX_WIDTH);
+    ap_uint<7> goal_y = (ap_uint<7>)(goal_xy - goal_x * MAX_WIDTH);
+    ap_uint<3> goal_z = (ap_uint<3>)(goal_id & BITMASK_Z);
+
+    qu_push(qu_nodes, start_id, &top, &bottom, &is_empty);
+
+    bool complete = false;
+
+    SEARCH_QUEUE:
+    while (!is_empty) {
+#pragma HLS LOOP_TRIPCOUNT min=1 max=1000
+#pragma HLS LOOP_FLATTEN off
+
+        ap_uint<CELL_BIT> src_id; // target cell
+        qu_pop(qu_nodes, &src_id, &top, &bottom, &is_empty);
+
+
+        // End routing
+        //if (avail[src_id] == -1) { complete = true; break; } // goal
+
+        if (avail[src_id] != 1 && avail[src_id] != 3) continue; // Keep searching
+
+        // Point of target cell
+        ap_uint<13> src_xy = (ap_uint<13>)(src_id >> BITWIDTH_Z);
+        ap_uint<7> src_x = (ap_uint<7>)(src_xy / MAX_WIDTH);
+        ap_uint<7> src_y = (ap_uint<7>)(src_xy - src_x * MAX_WIDTH);
+        ap_uint<3> src_z = (ap_uint<3>)(src_id & BITMASK_Z);
+	
+        ap_uint<3> isbranch = 0;
+        ap_uint<CELL_BIT> tmp_dest_id = 65535;
+        // Search adjacent cells (1)
+        SEARCH_ADJACENTS_1:
+        for (ap_uint<3> a = 0; a < 6; a++) {
+            ap_int<8> dest_x = (ap_int<8>)src_x; // Min: -1, Max: 72 (Signed 8bit)
+            ap_int<8> dest_y = (ap_int<8>)src_y; // Min: -1, Max: 72 (Signed 8bit)
+            ap_int<5> dest_z = (ap_int<5>)src_z; // Min: -1, Max:  8 (Signed 5bit)
+            if (a == 0) { dest_x -= 1; }
+            if (a == 1) { dest_x += 1; }
+            if (a == 2) { dest_y -= 1; }
+            if (a == 3) { dest_y += 1; }
+            if (a == 4) { dest_z -= 1; }
+            if (a == 5) { dest_z += 1; }
+
+            // Inside the board ? //
+            if (0 <= dest_x && dest_x < (ap_int<8>)size_x && 0 <= dest_y && dest_y < (ap_int<8>)size_y && 0 <= dest_z && dest_z < (ap_int<5>)size_z) {
+
+                // Adjacent cell
+                ap_uint<CELL_BIT> dest_id = (((ap_uint<CELL_BIT>)dest_x * MAX_WIDTH + (ap_uint<CELL_BIT>)dest_y) << BITWIDTH_Z) | (ap_uint<CELL_BIT>)dest_z;
+                if (avail[dest_id] >= 2) {
+                    isbranch++;
+                    tmp_dest_id = dest_id;
+                }
+            }
+        }
+        if (isbranch > 1) { avail[src_id] = 0; continue; }
+        if (avail[src_id] == 1) {
+            avail[src_id] = 2;
+            prev[src_id] = tmp_dest_id;
+        }
+
+        ap_uint<3> p = 0;
+        ap_uint<3> search_order[6];
+        if (src_x > goal_x) {
+            search_order[p++] = 0; // To src_x--
+        }
+        else {
+            search_order[5+p] = 0;
+        }
+        if (src_y > goal_y) {
+            search_order[p++] = 1; // To src_y--
+        }
+        else {
+            search_order[4+p] = 1;
+        }
+        if (src_z > goal_z) {
+            search_order[p++] = 2; // To src_z--
+        }
+        else {
+            search_order[3+p] = 2;
+        }
+        if (src_x < goal_x) {
+            search_order[p++] = 3; // To src_x++
+        }
+        else {
+            search_order[2+p] = 3;
+        }
+        if (src_y < goal_y) {
+            search_order[p++] = 4; // To src_y++
+        }
+        else {
+            search_order[1+p] = 4;
+        }
+        if (src_z < goal_z) {
+            search_order[p++] = 5; // To src_z++
+        }
+        else {
+            search_order[0+p] = 5;
+        }
+
+        ap_uint<3> j, t;
+        SHUFFLE_1:
+        for (ap_uint<3> a = 0; a < p; a++) {
+            j = lfsr_random() % p;
+            t = search_order[a];
+            search_order[a] = search_order[j];
+            search_order[j] = t;
+        }
+        SHUFFLE_2:
+        for (ap_uint<3> a = p; a < 6; a++) {
+            j = lfsr_random() % (6-p) + p;
+            t = search_order[a];
+            search_order[a] = search_order[j];
+            search_order[j] = t;
+        }
+
+        //cout << "(" << src_x << ", " << src_y << ", " << src_z << ")->";
+        //cout << "(" << goal_x << ", " << goal_y << ", " << goal_z << "): p = " << p << " [";
+        //for (ap_uint<3> a = 0; a < 6; a++) {
+        //    cout << search_order[a];
+        //    if (a != 5) cout << " ";
+        //}
+        //cout << "]" << endl;
+        
+        // Search adjacent cells (2)
+        SEARCH_ADJACENTS_2:
+        for (ap_uint<3> a = 0; a < 6; a++) {
+            ap_int<8> dest_x = (ap_int<8>)src_x; // Min: -1, Max: 72 (Signed 8bit)
+            ap_int<8> dest_y = (ap_int<8>)src_y; // Min: -1, Max: 72 (Signed 8bit)
+            ap_int<5> dest_z = (ap_int<5>)src_z; // Min: -1, Max:  8 (Signed 5bit)
+            if (search_order[5-a] == 0) { dest_x -= 1; }
+            if (search_order[5-a] == 1) { dest_y -= 1; }
+            if (search_order[5-a] == 2) { dest_z -= 1; }
+            if (search_order[5-a] == 3) { dest_x += 1; }
+            if (search_order[5-a] == 4) { dest_y += 1; }
+            if (search_order[5-a] == 5) { dest_z += 1; }
+
+            // Inside the board ? //
+            if (0 <= dest_x && dest_x < (ap_int<8>)size_x && 0 <= dest_y && dest_y < (ap_int<8>)size_y && 0 <= dest_z && dest_z < (ap_int<5>)size_z) {
+
+                // Adjacent cell
+                ap_uint<CELL_BIT> dest_id = (((ap_uint<CELL_BIT>)dest_x * MAX_WIDTH + (ap_uint<CELL_BIT>)dest_y) << BITWIDTH_Z) | (ap_uint<CELL_BIT>)dest_z;
+                if (dest_id == goal_id) {
+                    prev[dest_id] = src_id;
+                    complete = true;
+                }
+                qu_push(qu_nodes, dest_id, &top, &bottom, &is_empty);
+            }
+        }
+        if (complete) break;
+    }
+
+    return complete;
+}
+
+// Queue push (Enqueue)
+// First In Last Out
+void qu_push(ap_uint<CELL_BIT> qu_nodes[MAX_PQ], ap_uint<CELL_BIT> id, ap_uint<PQ_BIT> *top, ap_uint<PQ_BIT> *bottom, bool *is_empty) {
+#pragma HLS INLINE
+
+    (*bottom)++;
+    if ((*bottom) == (*top) && !(*is_empty)) { (*top)++; } // Queue is full -> First element is automatically removed
+    qu_nodes[(*bottom)] = id;
+    *is_empty = false;
+}
+
+// Queue pop (Dequeue)
+// First In Last Out
+void qu_pop(ap_uint<CELL_BIT> qu_nodes[MAX_PQ], ap_uint<CELL_BIT> *id, ap_uint<PQ_BIT> *top, ap_uint<PQ_BIT> *bottom, bool *is_empty) {
+#pragma HLS INLINE
+
+    *id = qu_nodes[(*bottom)];
+    (*bottom)--;
+    if (((*bottom)-(*top)+1) == 0) { *is_empty = true; }
+}

hls_2018/router_05/router.hpp

+/**
+ * router.hpp
+ *
+ * for Vivado HLS
+ */
+
+#ifndef __ROUTER_HPP__
+#define __ROUTER_HPP__
+
+#ifdef SOFTWARE
+#include "ap_int.h"
+#else
+#include <ap_int.h>
+#endif
+
+//#define DEBUG_PRINT // for debug
+
+#ifdef DEBUG_PRINT
+using namespace std;
+#endif
+
+// Parameters
+#define MAX_WIDTH   72      // Max of X, Y
+#define BITWIDTH_XY 13
+#define BITMASK_XY  65528   // 1111 1111 1111 1000
+#define MAX_LAYER   8       // Max of Z
+#define BITWIDTH_Z  3
+#define BITMASK_Z   7       // 0000 0000 0000 0111
+
+#define MAX_CELLS	41472    // Max #cells (16bit)
+#define MAX_LINES	32768    // Max #lines (15bit)
+#define MAX_PQ		16384    // Queue size (14bit)
+#define MAX_BUFFER	16384    // Line buffer size (14bit)
+#define CELL_BIT	16
+#define LINE_BIT	15
+#define PQ_BIT		14
+#define BUFF_BIT	14
+
+#define BOARDSTR_SIZE 41472      // Size of I/O
+
+// For random num generation
+void lfsr_random_init(ap_uint<32> seed);
+ap_uint<32> lfsr_random();
+
+bool pynqrouter(char boardstr[BOARDSTR_SIZE], char boardstr_high[BOARDSTR_SIZE], ap_uint<32> seed, ap_int<32> *status);
+bool inside_board(ap_uint<CELL_BIT> cell_id);
+bool connectable(ap_int<LINE_BIT+1> board[MAX_CELLS], ap_uint<LINE_BIT> target, ap_uint<LINE_BIT> rip_up);
+void remove_line(ap_int<LINE_BIT+1> board[MAX_CELLS], ap_uint<LINE_BIT> rip_up);
+bool available(ap_uint<2> avail[MAX_CELLS], ap_uint<CELL_BIT> prev[MAX_CELLS], ap_uint<CELL_BIT> start_id, ap_uint<CELL_BIT> goal_id);
+void qu_push(ap_uint<CELL_BIT> qu_nodes[MAX_PQ], ap_uint<CELL_BIT> id, ap_uint<PQ_BIT> *top, ap_uint<PQ_BIT> *bottom, bool *is_empty);
+void qu_pop(ap_uint<CELL_BIT> qu_nodes[MAX_PQ], ap_uint<CELL_BIT> *id, ap_uint<PQ_BIT> *top, ap_uint<PQ_BIT> *bottom, bool *is_empty);
+
+#endif /* __ROUTER_HPP__ */

hls_2018/router_05/solver.c

-/* solver.c */
-/* Last Change: 2018/08/26 (Sun) 23:31:34. */
-
-#define MAX_ATTEMPS 100000
-
-#include<stdio.h>
-#include<stdlib.h>
-#include<string.h>
-/* #include<limits.h> */
-/* #include<math.h> */
-#include<time.h>
-
-int board[8][72][72]={};
-int avail[8][72][72]={}; //start=3,path=2,avail=1,nonavail=0,goal=-1
-int connected[8*72*72/2+1]={}; //connected[0]=(number of connected lines)
-int depth,height,width;
-int goalx,goaly,goalz;
-int lines;
-//z,y,x
-
-void read(void){ //read problem
-	int x,y,z,i;
-	char c,str[8];
-	scanf(" %s",str); //SIZE
-	scanf(" %d",&width);
-	if(width>72||width<=0)
-		printf("Error: width\n");
-	scanf(" %c",&c); //X
-	scanf(" %d",&height);
-	if(height>72||height<=0)
-		printf("Error: height\n");
-	scanf(" %c",&c); //X
-	scanf(" %d",&depth);
-	if(depth>8||depth<=0)
-		printf("Error: depth\n");
-	scanf(" %s",str); //LINE_NUM
-	scanf(" %d",&lines);
-	if(lines<=0)
-		printf("Error: lines\n");
-	for(i=1;i<=lines;i++){
-		scanf(" %s",str); //LINE#X
-		scanf(" %c",&c); //(
-		scanf(" %d",&x);
-		if(x>=72||x<0)
-			printf("Error: x\n");
-		scanf(" %c",&c); //,
-		scanf(" %d",&y);
-		if(y>=72||y<0)
-			printf("Error: y\n");
-		scanf(" %c",&c); //,
-		scanf(" %d",&z);
-		if(z>=72||z<0)
-			printf("Error: z\n");
-		scanf(" %c",&c); //)
-		board[z-1][y][x]=-i;
-		scanf("%c",&c); //)
-		/* scanf(" %[ -]",&c); //space or - */
-		scanf(" %c",&c); //(
-		scanf(" %d",&x);
-		if(x>=72||x<0)
-			printf("Error: x\n");
-		scanf(" %c",&c); //,
-		scanf(" %d",&y);
-		if(y>=72||y<0)
-			printf("Error: y\n");
-		scanf(" %c",&c); //,
-		scanf(" %d",&z);
-		if(z>=72||z<0)
-			printf("Error: z\n");
-		scanf(" %c",&c); //)
-		board[z-1][y][x]=-i;
-	}
-	return;
-}
-
-int randline(void){ //return random line number
-	return rand()%lines+1;
-}
-
-void shuffle(int array[],int start,int end){
-	int i,j,t;
-	if(end==start)
-		return;
-	for(i=start;i<end;i++){
-		j=start+rand()%(end-start);
-		t=array[i];
-		array[i]=array[j];
-		array[j]=t;
-	}
-}
-
-int available(int nowx,int nowy, int nowz,int flag){ //return 1 when (nowx,nowy,nowz) can be connected to goal
-	if(avail[nowz][nowy][nowx]==-1) //goal
-		return 1;
-	if(avail[nowz][nowy][nowx]!=1&&flag==0)
-		return 0;
-	int isbranch=-1;
-	if(nowx>0&&avail[nowz][nowy][nowx-1]>=2)
-		isbranch++;
-	if(nowy>0&&avail[nowz][nowy-1][nowx]>=2)
-		isbranch++;
-	if(nowz>0&&avail[nowz-1][nowy][nowx]>=2)
-		isbranch++;
-	if(nowx<width-1&&avail[nowz][nowy][nowx+1]>=2)
-		isbranch++;
-	if(nowy<height-1&&avail[nowz][nowy+1][nowx]>=2)
-		isbranch++;
-	if(nowz<depth-1&&avail[nowz+1][nowy][nowx]>=2)
-		isbranch++;
-	if(isbranch>0){
-		avail[nowz][nowy][nowx]=1;
-		return 0;
-	}
-	if(avail[nowz][nowy][nowx]==1)
-		avail[nowz][nowy][nowx]=2;
-	int i,src=0;
-	int searchorder[6]; //x+-,y+-,z+-
-	/* for(i=0;i<6;i++) */
-	/* searchorder[i]=-1; */
-	if(nowx>goalx){
-		searchorder[src]=0;
-		src++;
-	}else
-		searchorder[5+src]=0;
-	if(nowy>goaly){
-		searchorder[src]=1;
-		src++;
-	}else
-		searchorder[4+src]=1;
-	if(nowz>goalz){
-		searchorder[src]=2;
-		src++;
-	}else
-		searchorder[3+src]=2;
-	if(nowx<goalx){
-		searchorder[src]=3;
-		src++;
-	}else
-		searchorder[2+src]=3;
-	if(nowy<goaly){
-		searchorder[src]=4;
-		src++;
-	}else
-		searchorder[1+src]=4;
-	if(nowz<goalz){
-		searchorder[src]=5;
-		src++;
-	}else
-		searchorder[src]=5;
-	/* shuffle(searchorder,0,src); */
-	/* shuffle(searchorder,src,6); */
-	int j,t;
-	for(i=0;i<src;i++){
-		j=rand()%(src);
-		t=searchorder[i];
-		searchorder[i]=searchorder[j];
-		searchorder[j]=t;
-	}
-	for(i=src;i<6;i++){
-		j=src+rand()%(6-src);
-		t=searchorder[i];
-		searchorder[i]=searchorder[j];
-		searchorder[j]=t;
-	}
-	/* for(i=0;i<6;i++) */
-	/* 	printf("%d ",searchorder[i]); */
-	/* printf("\n"); */
-	for(i=0;i<6;i++)
-		switch(searchorder[i]){
-			case 0:
-				if(nowx>0&&available(nowx-1,nowy,nowz,0))
-					return 1;
-				break;
-			case 1:
-				if(nowy>0&&available(nowx,nowy-1,nowz,0))
-					return 1;
-				break;
-			case 2:
-				if(nowz>0&&available(nowx,nowy,nowz-1,0))
-					return 1;
-				break;
-			case 3:
-				if(nowx<width-1&&available(nowx+1,nowy,nowz,0))
-					return 1;
-				break;
-			case 4:
-				if(nowy<height-1&&available(nowx,nowy+1,nowz,0))
-					return 1;
-				break;
-			case 5:
-				if(nowz<depth-1&&available(nowx,nowy,nowz+1,0))
-					return 1;
-				break;
-			default:
-				break;
-		}
-	if(avail[nowz][nowy][nowx]==2)
-		avail[nowz][nowy][nowx]=1;
-	return 0;
-}
-
-int connectable(int linea,int lineb){ //return 1 if linea can be connected when lineb is deleted
-	int startx=-1,starty=-1,startz=-1,notfound=1;
-	int i,j,k;
-	for(i=0;i<depth;i++)
-		for(j=0;j<height;j++)
-			for(k=0;k<width;k++)
-				if(board[i][j][k]==linea*(-1)){
-					if(notfound){ //start
-						startz=i;
-						starty=j;
-						startx=k;
-						avail[i][j][k]=3;
-						notfound=0;
-					}else{ //goal
-						goalz=i;
-						goaly=j;
-						goalx=k;
-						avail[i][j][k]=-1;
-						notfound=2;
-					}
-				}else if(board[i][j][k]==0||board[i][j][k]==lineb||board[i][j][k]==linea){
-					avail[i][j][k]=1;
-				}else{
-					avail[i][j][k]=0;
-				}
-	if(startx==-1||starty==-1||startz==-1||notfound!=2){
-		printf("Error: Line %d\n",linea);
-		return 0;
-	}
-	return available(startx,starty,startz,1);
-}
-
-void connect(int line){ //connect line
-	int i,j,k;
-	for(i=0;i<depth;i++)
-		for(j=0;j<height;j++)
-			for(k=0;k<width;k++)
-				if(avail[i][j][k]==2){
-					if(board[i][j][k]==0)
-						board[i][j][k]=line;
-					else
-						printf("something wrong");
-				}
-	return;
-}
-
-void delete(int line){ //delete line
-	int i,j,k;
-	for(i=0;i<depth;i++)
-		for(j=0;j<height;j++)
-			for(k=0;k<width;k++)
-				if(board[i][j][k]==line)
-					board[i][j][k]=0;
-	return;
-}
-
-int solve(void){ //return 1 when solved, 0 when cannot
-	int i,j,linea,lineb;
-	for(i=0;i<MAX_ATTEMPS;i++){ //try to connect MAX_ATTEMPS times
-		linea=randline();
-		if(connected[linea])
-			continue;
-		if(connectable(linea,0)){ //if linea canbe conneced without deleting lines
-			connect(linea);
-			connected[linea]=1;
-			connected[0]++;
-			if(connected[0]==lines)
-				return 1;
-		}
-		else{
-			for(j=0;j<MAX_ATTEMPS;j++){ //try to find a line to delete
-				lineb=randline();
-				if(connectable(linea,lineb)){
-					delete(lineb);
-					connect(linea);
-					connected[linea]=1;
-					connected[lineb]=0;
-					break;
-				}
-				if(j==MAX_ATTEMPS-1)
-					return 0;
-			}
-		}
-	}
-	return 0;
-}
-
-void write(void){
-	int i,j,k;
-	printf("SIZE %dX%dX%d\n",width,height,depth);
-	for(k=0;k<depth;k++){
-		printf("LAYER %d\n",k+1);
-		for(j=0;j<height;j++){
-			for(i=0;i<width-1;i++){
-				if(board[k][j][i]<0)
-					board[k][j][i]=-board[k][j][i];
-				printf("%d, ",board[k][j][i]);
-			}
-			if(board[k][j][i]<0)
-				board[k][j][i]=-board[k][j][i];
-			printf("%d",board[k][j][i]);
-			printf("\n");
-		}
-	}
-	return;
-}
-
-int main(void){
-	srand((unsigned)time(NULL));
-	read();
-	if(solve())
-		write();
-	else
-		printf("Cannot solve!\n");
-	return 0;
-}