Fix a little

hls_2018/README.md

@@ -17,11 +17,11 @@ PYNQ-router for Vivado-HLS (2018 ver.)
 * Vivado 2018.2
 
 Options:
-* Part: xc7z020clg400-1 (PYNQ-Z1), xczu3eg-sbva484-1-i (AVNET-Ultra96)
+* Part: xc7z020clg400-1 (PYNQ-Z1), xczu3eg-sbva484-1-e (AVNET-Ultra96)
 * Clock Period: 10.0 ns
-* Clock Uncertainty: 3.0 ns
-* Synthesis strategy: Vivado Synthesis Defaults
-* Implementation strategy: Vivado Implementation Defaults
+* Clock Uncertainty: 3.0 ns (--> 3.25 ns)
+* Synthesis strategy: ~~Vivado Synthesis Defaults~~ Flow_PerfOptimized_high
+* Implementation strategy: ~~Vivado Implementation Defaults~~ Performance_ExplorePostRoutePhysOpt
 
 ## I/O 
 * Input/Output: boardstr(8bit\*41472), seed(32bit), &status(32bit), return(1bit)