From b8153fb64e8bf67dcb559412465b2b6b49751b66 Mon Sep 17 00:00:00 2001 From: Kazushi Kawamura Date: Fri, 24 Aug 2018 18:12:21 +0900 Subject: [PATCH] Add README.md --- hls_2018/README.md | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 hls_2018/README.md diff --git a/hls_2018/README.md b/hls_2018/README.md new file mode 100644 index 0000000..bb8612e --- /dev/null +++ b/hls_2018/README.md @@ -0,0 +1,28 @@ +# pynq-router (sw) + +PYNQ-router for Vivado-HLS (2018 ver.) + +## Types of router + +|Name|Operation name|Description| +|:---|:---|:---| +|01|TBD|Line-number-free router for PYNQ-Z1. Priority queue is implemented with circular array(non-parallel)| +|02|TBD|Line-number-free router for PYNQ-Z1. Priority queue is implemented with circular array(parallel)| +|03|TBD|Line-number-free router for PYNQ-Z1. Priority queue is implemented with heap(size:2^15)| +|04|TBD|Line-number-free router for AVNET-Ultra96. Priority queue is implemented with heap(size:2^16)| + +## Memo + +* Vivado HLS 2018.2 +* Vivado 2018.2 + +Options: +* Part: xc7z020clg400-1 (PYNQ-Z1), xczu3eg-sbva484-1-i (AVNET-Ultra96) +* Clock Period: 10.0 ns +* Clock Uncertainty: 3.0 ns +* Synthesis strategy: Vivado Synthesis Defaults +* Implementation strategy: Vivado Implementation Defaults + +## I/O +* Input/Output: boardstr, seed, &status, return + -- 2.22.0