diff --git a/hls_2018/router_03_boardstr/bitstream/pynqrouter_AXI4LS_s_axi.v b/hls_2018/router_03_boardstr/bitstream/pynqrouter_AXI4LS_s_axi.v new file mode 100755 index 0000000000000000000000000000000000000000..adfcc74080632040ef0e9bf64827242194dd9d66 --- /dev/null +++ b/hls_2018/router_03_boardstr/bitstream/pynqrouter_AXI4LS_s_axi.v @@ -0,0 +1,654 @@ +// ============================================================== +// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC +// Version: 2018.2 +// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. +// +// ============================================================== + +`timescale 1ns/1ps +module pynqrouter_AXI4LS_s_axi +#(parameter + C_S_AXI_ADDR_WIDTH = 18, + C_S_AXI_DATA_WIDTH = 32 +)( + // axi4 lite slave signals + input wire ACLK, + input wire ARESET, + input wire ACLK_EN, + input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR, + input wire AWVALID, + output wire AWREADY, + input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA, + input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB, + input wire WVALID, + output wire WREADY, + output wire [1:0] BRESP, + output wire BVALID, + input wire BREADY, + input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR, + input wire ARVALID, + output wire ARREADY, + output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA, + output wire [1:0] RRESP, + output wire RVALID, + input wire RREADY, + output wire interrupt, + // user signals + output wire ap_start, + input wire ap_done, + input wire ap_ready, + input wire ap_idle, + input wire [0:0] ap_return, + input wire [15:0] boardstr_address0, + input wire boardstr_ce0, + input wire boardstr_we0, + input wire [7:0] boardstr_d0, + output wire [7:0] boardstr_q0, + input wire [15:0] boardstr_high_address0, + input wire boardstr_high_ce0, + input wire boardstr_high_we0, + input wire [7:0] boardstr_high_d0, + output wire [31:0] seed_V, + input wire [31:0] status_V, + input wire status_V_ap_vld +); +//------------------------Address Info------------------- +// 0x00000 : Control signals +// bit 0 - ap_start (Read/Write/COH) +// bit 1 - ap_done (Read/COR) +// bit 2 - ap_idle (Read) +// bit 3 - ap_ready (Read) +// bit 7 - auto_restart (Read/Write) +// others - reserved +// 0x00004 : Global Interrupt Enable Register +// bit 0 - Global Interrupt Enable (Read/Write) +// others - reserved +// 0x00008 : IP Interrupt Enable Register (Read/Write) +// bit 0 - Channel 0 (ap_done) +// bit 1 - Channel 1 (ap_ready) +// others - reserved +// 0x0000c : IP Interrupt Status Register (Read/TOW) +// bit 0 - Channel 0 (ap_done) +// bit 1 - Channel 1 (ap_ready) +// others - reserved +// 0x00010 : Data signal of ap_return +// bit 0 - ap_return[0] (Read) +// others - reserved +// 0x30000 : Data signal of seed_V +// bit 31~0 - seed_V[31:0] (Read/Write) +// 0x30004 : reserved +// 0x30008 : Data signal of status_V +// bit 31~0 - status_V[31:0] (Read) +// 0x3000c : Control signal of status_V +// bit 0 - status_V_ap_vld (Read/COR) +// others - reserved +// 0x10000 ~ +// 0x1ffff : Memory 'boardstr' (41472 * 8b) +// Word n : bit [ 7: 0] - boardstr[4n] +// bit [15: 8] - boardstr[4n+1] +// bit [23:16] - boardstr[4n+2] +// bit [31:24] - boardstr[4n+3] +// 0x20000 ~ +// 0x2ffff : Memory 'boardstr_high' (41472 * 8b) +// Word n : bit [ 7: 0] - boardstr_high[4n] +// bit [15: 8] - boardstr_high[4n+1] +// bit [23:16] - boardstr_high[4n+2] +// bit [31:24] - boardstr_high[4n+3] +// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) + +//------------------------Parameter---------------------- +localparam + ADDR_AP_CTRL = 18'h00000, + ADDR_GIE = 18'h00004, + ADDR_IER = 18'h00008, + ADDR_ISR = 18'h0000c, + ADDR_AP_RETURN_0 = 18'h00010, + ADDR_SEED_V_DATA_0 = 18'h30000, + ADDR_SEED_V_CTRL = 18'h30004, + ADDR_STATUS_V_DATA_0 = 18'h30008, + ADDR_STATUS_V_CTRL = 18'h3000c, + ADDR_BOARDSTR_BASE = 18'h10000, + ADDR_BOARDSTR_HIGH = 18'h1ffff, + ADDR_BOARDSTR_HIGH_BASE = 18'h20000, + ADDR_BOARDSTR_HIGH_HIGH = 18'h2ffff, + WRIDLE = 2'd0, + WRDATA = 2'd1, + WRRESP = 2'd2, + WRRESET = 2'd3, + RDIDLE = 2'd0, + RDDATA = 2'd1, + RDRESET = 2'd2, + ADDR_BITS = 18; + +//------------------------Local signal------------------- + reg [1:0] wstate = WRRESET; + reg [1:0] wnext; + reg [ADDR_BITS-1:0] waddr; + wire [31:0] wmask; + wire aw_hs; + wire w_hs; + reg [1:0] rstate = RDRESET; + reg [1:0] rnext; + reg [31:0] rdata; + wire ar_hs; + wire [ADDR_BITS-1:0] raddr; + // internal registers + reg int_ap_idle; + reg int_ap_ready; + reg int_ap_done = 1'b0; + reg int_ap_start = 1'b0; + reg int_auto_restart = 1'b0; + reg int_gie = 1'b0; + reg [1:0] int_ier = 2'b0; + reg [1:0] int_isr = 2'b0; + reg [0:0] int_ap_return; + reg [31:0] int_seed_V = 'b0; + reg [31:0] int_status_V = 'b0; + reg int_status_V_ap_vld; + // memory signals + wire [13:0] int_boardstr_address0; + wire int_boardstr_ce0; + wire int_boardstr_we0; + wire [3:0] int_boardstr_be0; + wire [31:0] int_boardstr_d0; + wire [31:0] int_boardstr_q0; + wire [13:0] int_boardstr_address1; + wire int_boardstr_ce1; + wire int_boardstr_we1; + wire [3:0] int_boardstr_be1; + wire [31:0] int_boardstr_d1; + wire [31:0] int_boardstr_q1; + reg int_boardstr_read; + reg int_boardstr_write; + reg [1:0] int_boardstr_shift; + wire [13:0] int_boardstr_high_address0; + wire int_boardstr_high_ce0; + wire int_boardstr_high_we0; + wire [3:0] int_boardstr_high_be0; + wire [31:0] int_boardstr_high_d0; + wire [31:0] int_boardstr_high_q0; + wire [13:0] int_boardstr_high_address1; + wire int_boardstr_high_ce1; + wire int_boardstr_high_we1; + wire [3:0] int_boardstr_high_be1; + wire [31:0] int_boardstr_high_d1; + wire [31:0] int_boardstr_high_q1; + reg int_boardstr_high_read; + reg int_boardstr_high_write; + reg [1:0] int_boardstr_high_shift; + +//------------------------Instantiation------------------ +// int_boardstr +pynqrouter_AXI4LS_s_axi_ram #( + .BYTES ( 4 ), + .DEPTH ( 10368 ) +) int_boardstr ( + .clk0 ( ACLK ), + .address0 ( int_boardstr_address0 ), + .ce0 ( int_boardstr_ce0 ), + .we0 ( int_boardstr_we0 ), + .be0 ( int_boardstr_be0 ), + .d0 ( int_boardstr_d0 ), + .q0 ( int_boardstr_q0 ), + .clk1 ( ACLK ), + .address1 ( int_boardstr_address1 ), + .ce1 ( int_boardstr_ce1 ), + .we1 ( int_boardstr_we1 ), + .be1 ( int_boardstr_be1 ), + .d1 ( int_boardstr_d1 ), + .q1 ( int_boardstr_q1 ) +); +// int_boardstr_high +pynqrouter_AXI4LS_s_axi_ram #( + .BYTES ( 4 ), + .DEPTH ( 10368 ) +) int_boardstr_high ( + .clk0 ( ACLK ), + .address0 ( int_boardstr_high_address0 ), + .ce0 ( int_boardstr_high_ce0 ), + .we0 ( int_boardstr_high_we0 ), + .be0 ( int_boardstr_high_be0 ), + .d0 ( int_boardstr_high_d0 ), + .q0 ( int_boardstr_high_q0 ), + .clk1 ( ACLK ), + .address1 ( int_boardstr_high_address1 ), + .ce1 ( int_boardstr_high_ce1 ), + .we1 ( int_boardstr_high_we1 ), + .be1 ( int_boardstr_high_be1 ), + .d1 ( int_boardstr_high_d1 ), + .q1 ( int_boardstr_high_q1 ) +); + +//------------------------AXI write fsm------------------ +assign AWREADY = (wstate == WRIDLE); +assign WREADY = (wstate == WRDATA); +assign BRESP = 2'b00; // OKAY +assign BVALID = (wstate == WRRESP); +assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} }; +assign aw_hs = AWVALID & AWREADY; +assign w_hs = WVALID & WREADY; + +// wstate +always @(posedge ACLK) begin + if (ARESET) + wstate <= WRRESET; + else if (ACLK_EN) + wstate <= wnext; +end + +// wnext +always @(*) begin + case (wstate) + WRIDLE: + if (AWVALID) + wnext = WRDATA; + else + wnext = WRIDLE; + WRDATA: + if (WVALID) + wnext = WRRESP; + else + wnext = WRDATA; + WRRESP: + if (BREADY) + wnext = WRIDLE; + else + wnext = WRRESP; + default: + wnext = WRIDLE; + endcase +end + +// waddr +always @(posedge ACLK) begin + if (ACLK_EN) begin + if (aw_hs) + waddr <= AWADDR[ADDR_BITS-1:0]; + end +end + +//------------------------AXI read fsm------------------- +assign ARREADY = (rstate == RDIDLE); +assign RDATA = rdata; +assign RRESP = 2'b00; // OKAY +assign RVALID = (rstate == RDDATA) & !int_boardstr_read & !int_boardstr_high_read; +assign ar_hs = ARVALID & ARREADY; +assign raddr = ARADDR[ADDR_BITS-1:0]; + +// rstate +always @(posedge ACLK) begin + if (ARESET) + rstate <= RDRESET; + else if (ACLK_EN) + rstate <= rnext; +end + +// rnext +always @(*) begin + case (rstate) + RDIDLE: + if (ARVALID) + rnext = RDDATA; + else + rnext = RDIDLE; + RDDATA: + if (RREADY & RVALID) + rnext = RDIDLE; + else + rnext = RDDATA; + default: + rnext = RDIDLE; + endcase +end + +// rdata +always @(posedge ACLK) begin + if (ACLK_EN) begin + if (ar_hs) begin + rdata <= 1'b0; + case (raddr) + ADDR_AP_CTRL: begin + rdata[0] <= int_ap_start; + rdata[1] <= int_ap_done; + rdata[2] <= int_ap_idle; + rdata[3] <= int_ap_ready; + rdata[7] <= int_auto_restart; + end + ADDR_GIE: begin + rdata <= int_gie; + end + ADDR_IER: begin + rdata <= int_ier; + end + ADDR_ISR: begin + rdata <= int_isr; + end + ADDR_AP_RETURN_0: begin + rdata <= int_ap_return[0:0]; + end + ADDR_SEED_V_DATA_0: begin + rdata <= int_seed_V[31:0]; + end + ADDR_STATUS_V_DATA_0: begin + rdata <= int_status_V[31:0]; + end + ADDR_STATUS_V_CTRL: begin + rdata[0] <= int_status_V_ap_vld; + end + endcase + end + else if (int_boardstr_read) begin + rdata <= int_boardstr_q1; + end + else if (int_boardstr_high_read) begin + rdata <= int_boardstr_high_q1; + end + end +end + + +//------------------------Register logic----------------- +assign interrupt = int_gie & (|int_isr); +assign ap_start = int_ap_start; +assign seed_V = int_seed_V; +// int_ap_start +always @(posedge ACLK) begin + if (ARESET) + int_ap_start <= 1'b0; + else if (ACLK_EN) begin + if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0]) + int_ap_start <= 1'b1; + else if (ap_ready) + int_ap_start <= int_auto_restart; // clear on handshake/auto restart + end +end + +// int_ap_done +always @(posedge ACLK) begin + if (ARESET) + int_ap_done <= 1'b0; + else if (ACLK_EN) begin + if (ap_done) + int_ap_done <= 1'b1; + else if (ar_hs && raddr == ADDR_AP_CTRL) + int_ap_done <= 1'b0; // clear on read + end +end + +// int_ap_idle +always @(posedge ACLK) begin + if (ARESET) + int_ap_idle <= 1'b0; + else if (ACLK_EN) begin + int_ap_idle <= ap_idle; + end +end + +// int_ap_ready +always @(posedge ACLK) begin + if (ARESET) + int_ap_ready <= 1'b0; + else if (ACLK_EN) begin + int_ap_ready <= ap_ready; + end +end + +// int_auto_restart +always @(posedge ACLK) begin + if (ARESET) + int_auto_restart <= 1'b0; + else if (ACLK_EN) begin + if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0]) + int_auto_restart <= WDATA[7]; + end +end + +// int_gie +always @(posedge ACLK) begin + if (ARESET) + int_gie <= 1'b0; + else if (ACLK_EN) begin + if (w_hs && waddr == ADDR_GIE && WSTRB[0]) + int_gie <= WDATA[0]; + end +end + +// int_ier +always @(posedge ACLK) begin + if (ARESET) + int_ier <= 1'b0; + else if (ACLK_EN) begin + if (w_hs && waddr == ADDR_IER && WSTRB[0]) + int_ier <= WDATA[1:0]; + end +end + +// int_isr[0] +always @(posedge ACLK) begin + if (ARESET) + int_isr[0] <= 1'b0; + else if (ACLK_EN) begin + if (int_ier[0] & ap_done) + int_isr[0] <= 1'b1; + else if (w_hs && waddr == ADDR_ISR && WSTRB[0]) + int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write + end +end + +// int_isr[1] +always @(posedge ACLK) begin + if (ARESET) + int_isr[1] <= 1'b0; + else if (ACLK_EN) begin + if (int_ier[1] & ap_ready) + int_isr[1] <= 1'b1; + else if (w_hs && waddr == ADDR_ISR && WSTRB[0]) + int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write + end +end + +// int_ap_return +always @(posedge ACLK) begin + if (ARESET) + int_ap_return <= 0; + else if (ACLK_EN) begin + if (ap_done) + int_ap_return <= ap_return; + end +end + +// int_seed_V[31:0] +always @(posedge ACLK) begin + if (ARESET) + int_seed_V[31:0] <= 0; + else if (ACLK_EN) begin + if (w_hs && waddr == ADDR_SEED_V_DATA_0) + int_seed_V[31:0] <= (WDATA[31:0] & wmask) | (int_seed_V[31:0] & ~wmask); + end +end + +// int_status_V +always @(posedge ACLK) begin + if (ARESET) + int_status_V <= 0; + else if (ACLK_EN) begin + if (status_V_ap_vld) + int_status_V <= status_V; + end +end + +// int_status_V_ap_vld +always @(posedge ACLK) begin + if (ARESET) + int_status_V_ap_vld <= 1'b0; + else if (ACLK_EN) begin + if (status_V_ap_vld) + int_status_V_ap_vld <= 1'b1; + else if (ar_hs && raddr == ADDR_STATUS_V_CTRL) + int_status_V_ap_vld <= 1'b0; // clear on read + end +end + + +//------------------------Memory logic------------------- +// boardstr +assign int_boardstr_address0 = boardstr_address0 >> 2; +assign int_boardstr_ce0 = boardstr_ce0; +assign int_boardstr_we0 = boardstr_we0; +assign int_boardstr_be0 = 1 << boardstr_address0[1:0]; +assign int_boardstr_d0 = {4{boardstr_d0}}; +assign boardstr_q0 = int_boardstr_q0 >> (int_boardstr_shift * 8); +assign int_boardstr_address1 = ar_hs? raddr[15:2] : waddr[15:2]; +assign int_boardstr_ce1 = ar_hs | (int_boardstr_write & WVALID); +assign int_boardstr_we1 = int_boardstr_write & WVALID; +assign int_boardstr_be1 = WSTRB; +assign int_boardstr_d1 = WDATA; +// boardstr_high +assign int_boardstr_high_address0 = boardstr_high_address0 >> 2; +assign int_boardstr_high_ce0 = boardstr_high_ce0; +assign int_boardstr_high_we0 = boardstr_high_we0; +assign int_boardstr_high_be0 = 1 << boardstr_high_address0[1:0]; +assign int_boardstr_high_d0 = {4{boardstr_high_d0}}; +assign int_boardstr_high_address1 = ar_hs? raddr[15:2] : waddr[15:2]; +assign int_boardstr_high_ce1 = ar_hs | (int_boardstr_high_write & WVALID); +assign int_boardstr_high_we1 = int_boardstr_high_write & WVALID; +assign int_boardstr_high_be1 = WSTRB; +assign int_boardstr_high_d1 = WDATA; +// int_boardstr_read +always @(posedge ACLK) begin + if (ARESET) + int_boardstr_read <= 1'b0; + else if (ACLK_EN) begin + if (ar_hs && raddr >= ADDR_BOARDSTR_BASE && raddr <= ADDR_BOARDSTR_HIGH) + int_boardstr_read <= 1'b1; + else + int_boardstr_read <= 1'b0; + end +end + +// int_boardstr_write +always @(posedge ACLK) begin + if (ARESET) + int_boardstr_write <= 1'b0; + else if (ACLK_EN) begin + if (aw_hs && AWADDR[ADDR_BITS-1:0] >= ADDR_BOARDSTR_BASE && AWADDR[ADDR_BITS-1:0] <= ADDR_BOARDSTR_HIGH) + int_boardstr_write <= 1'b1; + else if (WVALID) + int_boardstr_write <= 1'b0; + end +end + +// int_boardstr_shift +always @(posedge ACLK) begin + if (ACLK_EN) begin + if (boardstr_ce0) + int_boardstr_shift <= boardstr_address0[1:0]; + end +end + +// int_boardstr_high_read +always @(posedge ACLK) begin + if (ARESET) + int_boardstr_high_read <= 1'b0; + else if (ACLK_EN) begin + if (ar_hs && raddr >= ADDR_BOARDSTR_HIGH_BASE && raddr <= ADDR_BOARDSTR_HIGH_HIGH) + int_boardstr_high_read <= 1'b1; + else + int_boardstr_high_read <= 1'b0; + end +end + +// int_boardstr_high_write +always @(posedge ACLK) begin + if (ARESET) + int_boardstr_high_write <= 1'b0; + else if (ACLK_EN) begin + if (aw_hs && AWADDR[ADDR_BITS-1:0] >= ADDR_BOARDSTR_HIGH_BASE && AWADDR[ADDR_BITS-1:0] <= ADDR_BOARDSTR_HIGH_HIGH) + int_boardstr_high_write <= 1'b1; + else if (WVALID) + int_boardstr_high_write <= 1'b0; + end +end + +// int_boardstr_high_shift +always @(posedge ACLK) begin + if (ACLK_EN) begin + if (boardstr_high_ce0) + int_boardstr_high_shift <= boardstr_high_address0[1:0]; + end +end + + +endmodule + + +`timescale 1ns/1ps + +module pynqrouter_AXI4LS_s_axi_ram +#(parameter + BYTES = 4, + DEPTH = 256, + AWIDTH = log2(DEPTH) +) ( + input wire clk0, + input wire [AWIDTH-1:0] address0, + input wire ce0, + input wire we0, + input wire [BYTES-1:0] be0, + input wire [BYTES*8-1:0] d0, + output reg [BYTES*8-1:0] q0, + input wire clk1, + input wire [AWIDTH-1:0] address1, + input wire ce1, + input wire we1, + input wire [BYTES-1:0] be1, + input wire [BYTES*8-1:0] d1, + output reg [BYTES*8-1:0] q1 +); +//------------------------Local signal------------------- +reg [BYTES*8-1:0] mem[0:DEPTH-1]; +//------------------------Task and function-------------- +function integer log2; + input integer x; + integer n, m; +begin + n = 1; + m = 2; + while (m < x) begin + n = n + 1; + m = m * 2; + end + log2 = n; +end +endfunction +//------------------------Body--------------------------- +// read port 0 +always @(posedge clk0) begin + if (ce0) q0 <= mem[address0]; +end + +// read port 1 +always @(posedge clk1) begin + if (ce1) q1 <= mem[address1]; +end + +genvar i; +generate + for (i = 0; i < BYTES; i = i + 1) begin : gen_write + // write port 0 + always @(posedge clk0) begin + if (ce0 & we0 & be0[i]) begin + mem[address0][8*i+7:8*i] <= d0[8*i+7:8*i]; + end + end + // write port 1 + always @(posedge clk1) begin + if (ce1 & we1 & be1[i]) begin + mem[address1][8*i+7:8*i] <= d1[8*i+7:8*i]; + end + end + end +endgenerate + +endmodule + diff --git a/hls_2018/router_03_boardstr/bitstream/router_design.bit b/hls_2018/router_03_boardstr/bitstream/router_design.bit new file mode 100755 index 0000000000000000000000000000000000000000..38548854bbee9afbe307d91ebb5fe19c7d1d229d Binary files /dev/null and b/hls_2018/router_03_boardstr/bitstream/router_design.bit differ diff --git a/hls_2018/router_03_boardstr/bitstream/router_design.tcl b/hls_2018/router_03_boardstr/bitstream/router_design.tcl new file mode 100755 index 0000000000000000000000000000000000000000..e5347dff159dc309b6768469faa92beeede33e8e --- /dev/null +++ b/hls_2018/router_03_boardstr/bitstream/router_design.tcl @@ -0,0 +1,1113 @@ + +################################################################ +# This is a generated script based on design: router_design +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2018.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source router_design_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z020clg400-1 +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name router_design + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:processing_system7:5.5\ +xilinx.com:hls:pynqrouter:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + # Create ports + set LD [ create_bd_port -dir O -from 3 -to 0 LD ] + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_GPIO_WIDTH {4} \ + ] $axi_gpio_0 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ + CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ + CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ + CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ + CONFIG.PCW_CAN0_CAN0_IO {} \ + CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ + CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ + CONFIG.PCW_CAN1_CAN1_IO {} \ + CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ + CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ + CONFIG.PCW_CLK0_FREQ {100000000} \ + CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CORE0_FIQ_INTR {0} \ + CONFIG.PCW_CORE0_IRQ_INTR {0} \ + CONFIG.PCW_CORE1_FIQ_INTR {0} \ + CONFIG.PCW_CORE1_IRQ_INTR {0} \ + CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ + CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ + CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ + CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ + CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PRIORITY_READPORT_0 {} \ + CONFIG.PCW_DDR_PRIORITY_READPORT_2 {} \ + CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {} \ + CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {} \ + CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ + CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DM_WIDTH {4} \ + CONFIG.PCW_DQS_WIDTH {4} \ + CONFIG.PCW_DQ_WIDTH {32} \ + CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ + CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ + CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {1} \ + CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ + CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ + CONFIG.PCW_ENET1_ENET1_IO {} \ + CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ + CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET1_RESET_IO {} \ + CONFIG.PCW_FTM_CTI_IN1 {} \ + CONFIG.PCW_FTM_CTI_IN3 {} \ + CONFIG.PCW_FTM_CTI_OUT1 {} \ + CONFIG.PCW_FTM_CTI_OUT3 {} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C0_GRP_INT_IO {} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_IO {} \ + CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ + CONFIG.PCW_I2C1_I2C1_IO {} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ + CONFIG.PCW_I2C_RESET_ENABLE {1} \ + CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ + CONFIG.PCW_I2C_RESET_SELECT {} \ + CONFIG.PCW_NAND_NAND_IO {} \ + CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS0_IO {} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_IO {} \ + CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ + CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ + CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ + CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ + CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ + CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ + CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ + CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ + CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ + CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ + CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ + CONFIG.PCW_P2F_CAN0_INTR {0} \ + CONFIG.PCW_P2F_CAN1_INTR {0} \ + CONFIG.PCW_P2F_CTI_INTR {0} \ + CONFIG.PCW_P2F_DMAC0_INTR {0} \ + CONFIG.PCW_P2F_DMAC1_INTR {0} \ + CONFIG.PCW_P2F_DMAC2_INTR {0} \ + CONFIG.PCW_P2F_DMAC3_INTR {0} \ + CONFIG.PCW_P2F_DMAC4_INTR {0} \ + CONFIG.PCW_P2F_DMAC5_INTR {0} \ + CONFIG.PCW_P2F_DMAC6_INTR {0} \ + CONFIG.PCW_P2F_DMAC7_INTR {0} \ + CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ + CONFIG.PCW_P2F_ENET0_INTR {0} \ + CONFIG.PCW_P2F_ENET1_INTR {0} \ + CONFIG.PCW_P2F_GPIO_INTR {0} \ + CONFIG.PCW_P2F_I2C0_INTR {0} \ + CONFIG.PCW_P2F_I2C1_INTR {0} \ + CONFIG.PCW_P2F_QSPI_INTR {0} \ + CONFIG.PCW_P2F_SDIO0_INTR {0} \ + CONFIG.PCW_P2F_SDIO1_INTR {0} \ + CONFIG.PCW_P2F_SMC_INTR {0} \ + CONFIG.PCW_P2F_SPI0_INTR {0} \ + CONFIG.PCW_P2F_SPI1_INTR {0} \ + CONFIG.PCW_P2F_UART0_INTR {0} \ + CONFIG.PCW_P2F_UART1_INTR {0} \ + CONFIG.PCW_P2F_USB0_INTR {0} \ + CONFIG.PCW_P2F_USB1_INTR {0} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ + CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ + CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ + CONFIG.PCW_PACKAGE_NAME {clg400} \ + CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \ + CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_PJTAG_PJTAG_IO {} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ + CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SS1_IO {} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_IO {} \ + CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD1_GRP_POW_IO {} \ + CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SD1_SD1_IO {} \ + CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_SPI0_GRP_SS1_IO {} \ + CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SPI0_SPI0_IO {} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_SPI1_GRP_SS1_IO {} \ + CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SPI1_SPI1_IO {} \ + CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_2BIT_IO {} \ + CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ + CONFIG.PCW_TRACE_GRP_4BIT_IO {} \ + CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ + CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PCW_TRACE_TRACE_IO {} \ + CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ + CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_TTC1_TTC1_IO {} \ + CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ + CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ + CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ + CONFIG.PCW_UART1_BAUD_RATE {115200} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_GRP_FULL_IO {} \ + CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ + CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ + CONFIG.PCW_UIPARAM_DDR_AL {0} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_BL {8} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ + CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ + CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ + CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ + CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ + CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ + CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ + CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ + CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ + CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ + CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ + CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ + CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ + CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ + CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ + CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ + CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ + CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ + CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB0_RESET_ENABLE {1} \ + CONFIG.PCW_USB0_RESET_IO {MIO 46} \ + CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ + CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ + CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ + CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB1_RESET_IO {} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ + CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ + CONFIG.PCW_USE_AXI_NONSECURE {0} \ + CONFIG.PCW_USE_CORESIGHT {0} \ + CONFIG.PCW_USE_CROSS_TRIGGER {0} \ + CONFIG.PCW_USE_CR_FABRIC {1} \ + CONFIG.PCW_USE_DDR_BYPASS {0} \ + CONFIG.PCW_USE_DEBUG {0} \ + CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ + CONFIG.PCW_USE_DMA0 {0} \ + CONFIG.PCW_USE_DMA1 {0} \ + CONFIG.PCW_USE_DMA2 {0} \ + CONFIG.PCW_USE_DMA3 {0} \ + CONFIG.PCW_USE_EXPANDED_IOP {0} \ + CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \ + CONFIG.PCW_USE_HIGH_OCM {0} \ + CONFIG.PCW_USE_M_AXI_GP0 {1} \ + CONFIG.PCW_USE_M_AXI_GP1 {0} \ + CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ + CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ + CONFIG.PCW_USE_S_AXI_ACP {0} \ + CONFIG.PCW_USE_S_AXI_GP0 {0} \ + CONFIG.PCW_USE_S_AXI_GP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP0 {0} \ + CONFIG.PCW_USE_S_AXI_HP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP2 {0} \ + CONFIG.PCW_USE_S_AXI_HP3 {0} \ + CONFIG.PCW_USE_TRACE {0} \ + CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ + CONFIG.PCW_VALUE_SILVERSION {3} \ + CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ + CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_WDT_WDT_IO {