Fix bugs in router and upload a bitstream file

hls/auto/auto_compile.c

@@ -6,7 +6,7 @@
 int main(void){
 
    char q[STRLEN], command[STRLEN];
-   char dir[64] = "../lines128_length256";
+   char dir[64] = "../lines256_length128";
 
    FILE *fp;
    fp = fopen("q.txt", "r");

hls/auto/q.txt

@@ -23,3 +23,7 @@ X72Y72Z8L0000171023L0000271022L0000371021L0001171013L0001371011L0002171003L00022
 X03Y03Z3L0000102002L0101101002L0200101012L0001101023L0001201013L0102102013
 X72Y72Z1L0100161061L2300164131L5500142501L0062106031L1771171341L2271166661L5967146631L2565161681L2665167661L2467159701L2369169691L5668157661L5569157671L0200159181L0116125331L4701170011L0209139261L6117103351L1628148341L0428103091L2400150061L1860119691L0114152461L2107156021L2158170361L0117112321L1213168041L0342114681L1643151591L5544161161L1115134161L1116134151L4342124521L0238146371L1449120631L0259113681L2243138471L0642146381L0404151031L5616159471L1216135161L1137126331L3911141261L0214159331L0269111321L6315168051L1741155561L0540109331L2322134211L4353129461L0713160351L1362118691L2244127471L0934108431L1120126191L1410140261L1957168571L5808146391L6653169311L0765166521L2719129191L3044125471L0425133311L1352110631L0405163111L0858110571L2645143541L5809165141L0515132261L2649141431L1252109611L0604141061L1955143411L1704153121L1448119541L2405145181L2447142511L1058113461L4605146211L1639122391L4613151111L4710146221L4414144181L0516105251L6822168331
 X40Y40Z3L0000139001L0001139011L0002139021L0003139031L0004139041L0005139051L0006139061L0007139071L0008139081L0009139091L0010139101L0011139111L0012139121L0013139131L0014139141L0015139151L0016139161L0017139171L0018139181L0019139191L0020139201L0021139211L0022139221L0023139231L0024139241L0025139251L0026139261L0027139271L0028139281L0029139291L0030139301L0031139311L0032139321L0033139331L0034139341L0035139351L0036139361L0037139371L0038139381L0039139391L0100101391L0500105391L0900109391L1300113391L1700117391L2100121391L2500125391L2900129391L3300133391L3700137391L0100201392L0300203392L0500205392L0700207392L0900209392L1100211392L1300213392L1500215392L1700217392L1900219392L2100221392L2300223392L2500225392L2700227392L2900229392L3100231392L3300233392L3500235392L3700237392L3900239392L0300303393L0700307393L1100311393L1500315393L1900319393L2300323393L2700327393L3100331393L3500335393L3900339393
+X30Y30Z3L1212111103L1811311041L0412101102L0410218072L2612328231L2411128111L0503313081L1810314062L2301315031L2415326192L2224229251L0323201211L2911229192L1801317002L1128115162L1629211293L2026212291L1701317033L1714120233L2105121031L1014309152L0716104051L2221128271L1205311042L0420308243L0718204271L1221311252L0223201273L0502209071L1314109142L0317204222L2312319131L2026119241L0302116022L1611118011L1224110263L2229116171L1319220271L1710114091L0607203032L0513203131L0109100161L1424315231L1727113241L1416111182L1213213112L2510316102L2521228222L0321306273L2305228003L1501310013L1918120182L2226222241L2313220152L0117203201L2700318033L2103228022L1806215073L2813329182L0318202172L0903109022L2629228193L2610123121L1528320243L1607115061L0124103231L0216103141L2506223051L0624307253L0902110011L1128201291L2907228011L0109202103L2923329263L1016309153L1912320142L1807118051L1216211143L2504124051L1714217113L1828312293L0200100032L0705208072L1321312173L2007120031L0001201002L1312315123L0819107181L0927210281L2410225071L2726121282L1705316033L2609328093L2503321011L0018101201L2328222261L0301306011L2617225202L1112115142L0712108111L0624109221L0606104101L2728228272L0607304073L0514206161L0800306003L1006107042L2013321143L0827310273L1206111051L2715128141L2608122081L0116301183L0313302102L0715209131L2120223212L1627217243L2324322203L0423303241L0818209193L1624315241L2512327101L1912117111L2003323033L2416325132L0504106051L1404314022L1618317143L1318213191L2811326112L2516325142L1619315203L1606118081L2102222013L2806223021L2622324223L0805112041L0923309252L2307324053L2625225232L2023122212L0521105191L0717307153L1920118181L1226312283L2116122141L0727104261L0615105141L2427325263L0204100062L0225200253L1713115131L1928320273L0308203052L1822214232L0811310123L2428123271L2522127231L1109310073L0405207053L0215201142L2815127152L2905128041L2217322152L1216113171L0105202022L2317320172L1810114093L2707128081L0528306263L2418124161L2802329032L0411207122L0619305163L0208201103L1725217272L1108112092L0702208013L2106122063L2921129231L2118123181L2619324193L2908229102L0819307192L0022101231L1315115151L0729209282L0125201272L2708227093L0922308233L1320212222L0424305242L2606328063L1413214123L1819316203L0317104181L1719315201L1315314162L1212312133L2609224092L1212211132L2717327172L1428117281L2010220093L1316213152L0507106081L0113101121L1428314293L1117211162L0812108131
+X40Y40Z4L0000139394L3900100394L0039139004L3939100004L3800100384L3700100374L3600100364L3500100354L3400100344L3300100334L3200100324L3100100314L3000100304L2900100294L2800100284L2700100274L2600100264L2500100254L2401100244L2301100234L2201100224L2101100214L2001100204L0601119011L3938101004L3937102004L3936103004L3935104014L3934105014L3933106014L3932107014L3931108014L3930109014L3929110014L3928111014L3927112014L3926113014L3925114014L3924115014L3923116014L3922117014L0121119391L0222118381L0323117371L0424116361L0525115351L0626114341L0727113331L0828112321L0929109311L3722121381L3623122371L3524123361L3425124351L3326125341L3227126331L3128127321L2829130291L1030111311L2930128311L1801422014L0220420384L0321419374L0422418364L0523417354L0624416344L0725415334L0826414324L0927413314L1028412284L1129412304L3823422394L3724423384L3625424374L3526425364L3427426354L3328427344L3229428334L3130431324L3031429324L0020219392L0121218382L0222217372L0323216362L0424215352L0525214342L0626213332L0727212322L0828211312L0929210302L3922222392L3823223382L3724224372L3625225362L3526226352L3427227342L3328228332L3229229322L3130230312L0000220283L0100220273L0200220263L0300220253L0401220243L0500220233L0600220223L0700220213L0800220203L0900220193L1000220183L3900211293L3800221283L3700221273L3600221263L3500221253L3400221243L3300221233L3200221223L3100221213L3000221203L0019221023L0119220033L0220220043L0321220053L0422220063L0523220073L0624220083L0725220093L0826220103L0927220113L2100223002L2500229002L3128221113L3227221103L3326221093L3425221083L3524221073L3623221063L3722221053L3821221043L3921221033L2019220382L1920219372L1821218362L1722217352L1623216342L1524215332L1425214322L1326213312L1227212302L1128211292L2121221382L2222222372L2323223362L2424224352L2525225342L2626226332L2727227322L2828228312L2929229302L1912319393L2012322393L0000339003L0001302013L0601339013L2702339023L0119338213L0220337223L0321336233L0422335243L0523334253L1918306243L1819307253L1720308263L1621309273L1522310273L1423311263L1324312253L2118333263L2119332273L2220331283L2321330283L2422329273L2523328263L2624327253L1230320383L1331319373L1432318363L1533317333L1634317353L2930321383L2831322373L2732323363L2433326333L2534324353L0121318383L0222317373L0323316363L0424315353L0525314343L0626313333L0727312323L0828311313L0929310303L3823323383L3724324373L3625325363L3526326353L3427327343L3328328333L3229329323L3130330313
+X72Y72Z1L0000108151L0004171321L0013171421L0016171431L0030100631L0046170601L7164100711L7165128711L1001170321L0500105031L0501107011L0502107021L0001100031L0002102021L0705107071L0506107061L0005106161L0105101111L0106105101L0117171541L0015170341L0014165331L0518165321L0017123261L0024133411L3330169531L2228100291L0025121281L0825108271L2312169321L2412168321L2512167321L0226108261L7065131701L7066135701L7067139701L4669169691L4968143701L2605166051L2705165051L2706165061L3706149061L2707150171L2708150161L2808151161L2809161131L6009162101L5309152141L5210152131L2810132101L5512153131L5610154111L5710157131L5810158131L0664144641L0764101691L4064102661L3664103681L1564103671L3264104671L2565122661L2864109661L0965120651L1664120641L1204162311L0031169571L3131124591L0045169581L1632100441L1521140211L6421164321L1905161231L1805137231L3020130221L3021136211L2247106591L1458170611L0062170621L1457121611L1749119501L1859120591L2149120601L1205117051L1605113171L1606114161L1417116191L1607115161L1507115151L2216145201L4420146201L4118143181L4117141191L3531168511L4034143341L4434134391L3933135391L3532138381L3632138371L3634136371L3734137371L3930155361L4035164521L4330155341L4831154311L5332154331L4036162521L4840160521L4941159511L5042158501L5143157491L5244156481L5345154461L5347155471L4137147391L4037145391L5738169491L6847169481L6039169461L5938167441L6239166431L6340164411L6540165421L0234104351L0342105441L0434125571L0433126571L1534107431L0836108431L0741109421L0943125431L1035125421L1036111381L1337114391L1040110421L1041113411L1831143561L1839142451L4145129551L1838140541L2932118371L2832118361L2833119361L1933127331L2033126331L2034126341L1456100611L1447100601L1354101591L1347100591L1247100521L1248101521L1148101511L0249102511L0250110501L4045132471L3845139471L4046139521L3645140511L3646134491L3547135491
+X40Y40Z2L0000139001L0100138001L0200137001L0300136001L0400135001L0500134001L0600133001L0700132001L0800131001L0900130001L1000129001L1100128001L1200127001L1300126001L1400125001L1500124001L1600123001L1700122001L1800121001L1900120001L0001100381L0002100371L0003100361L0004100351L0005100341L0006100331L0007100321L0008100311L0009100301L0010100291L0011100281L0012100271L0013100261L0014100251L0015100241L0016100231L0017100221L0018100211L0019100201L0039139391L0139138391L0239137391L0339136391L0439135391L0539134391L0639133391L0739132391L0839131391L0939130391L1039129391L1139128391L1239127391L1339126391L1439125391L1539124391L1639123391L1739122391L1839121391L1939120391L3901139381L3902139371L3903139361L3904139351L3905139341L3906139331L3907139321L3908139311L3909139301L3910139291L3911139281L3912139271L3913139261L3914139251L3915139241L3916139231L3917139221L3918139211L3919139201L1010129101L1110128101L1210127101L1310126101L1410125101L1510124101L1610123101L1710122101L1810121101L1910120101L1011110281L1012110271L1013110261L1014110251L1015110241L1016110231L1017110221L1018110211L1019110201L1029129291L1129128291L1229127291L1329126291L1429125291L1529124291L1629123291L1729122291L1829121291L1929120291L2911129281L2912129271L2913129261L2914129251L2915129241L2916129231L2917129221L2918129211L2919129201L1515124151L1615123151L1715122151L1815121151L1915120151L1516115231L1517115221L1518115211L1519115201L1524124241L1624123241L1724122241L1824121241L1924120241L2416124231L2417124221L2418124211L2419124201L1718122181L1818121181L1918120181L1719117201L1721122211L1821121211L1921120211L2219122201L0910209292L3010230292L1415214242L2515225242L1717222172L1719222192L1720222202L1722222222

hls/auto/q_old.txt

+X24Y24Z4L0613304164L1702122032L0101403204L1601420204L2117419044L0023116021L1520309084L1921116154L1709121031L1812103211L0905208142L0704412013L0421110094L2320100142L1500319034L0915104123L0907418124L2001109101L0122202213L2102422011L2120105211L2319117132L0404119103L1215322223L0607218074L1715113123L1217220172L1602320113L0003306053L0405413144L2006421214L1301103212L0614322183L1108323004L0004322043L0602322213L1210120142L1321419172L1202116012L1303103081L0820211202L1003116142L1701305123L0312223072L0720301063L1202214024L0506207072L1610417224L1309404154L1201408124L1704410064L0822110211L1210321153L1708116072L0000100111L0201112011L0808104103L0923210212L1210413134L1500421014
+X15Y15Z2L0202212102L0303211112L0404210122L0503209112L0402210102L0204212122L0203212112L0302211102L0403210112L0504209122L0502209102L0304211122
+X20Y20Z8L0203202066L0400403037L0403105088L0503101016L0500206038L0703317055L1001104054L0505317087L0108204086L0111101177L0810406188L0313406138L0413215177L0513106176L0317302158L0715100195L0318307064L1503212048L1702112058L1206318087L1007417036L1101317047L1406216094L1111217187L1310418146L1510315145L1014310177L1317219198L0919218177
+X72Y72Z8L0000171718L0036871001L0000800718L0036171008L0071171711L3671171368
+X08Y08Z4L0000107072L0100103032L0007106072L0503106032L0506101062L0001205062L0404106051L0700207032L0201202032L0205203052L0000307074L0100303034L0007306074L0503306034L0506301064L0001405064L0404306053L0700407034L0201402034L0205403054
+X48Y36Z8L0609109051L0608108091L0709109021L0306109041L0204109091L0207105091L0208105041L0209104041L0607109031L0516105191L0417106171L0418106181L0113103131L0213104211L0214107211L0413110211L0814108211L0221110221L0226103321L0331104251L0128105321L0329108321L0733109261L0629107261L0630107271L0233106281L1400123101L1503123061L1504122101L1508122081L1509122011L1606118111L1702122041L1212119211L1319115141L1316120151L1217118171L1313119221L2020122121L1517116221L1421116171L1527123351L1328120261L1533122251L1830121311L1334120291L1426119261L1632119251L1730122291L1431121341L2501131011L2708128051L2800134051L3400135111L2400132031L2704132081L2406125021L2504133101L2401128101L2522134151L2921134161L2513134171L3013134221L2614130171L3019135191L2415130181L3414135121L3524135341L2533135281L2727135351L2435129311L2734129351L2829131331L2833132321L3607146111L4207147111L4010147001L3600137101L3608144021L4509146051L4020145141L3614141151L4218147231L3612145201L3712143141L3623144181L3912146231L3624144301L4030147241L3635137321L3835147351L4132146351L3634145311L3726144291L3733142281L2935227213L0629622066L0606335013L1728617245L0814411182L2608416057
+X72Y72Z8L0000166038L0004128038L0013104688L0016158688L0030133688L0046120038L0071149038L7165169688
+X15Y15Z2L0602214082L1406114081L0901111112L0110100072L0405209012L1108112071L0707208011L0301107002L0014101142L0405103072L0006203042L1008111071L1301214132L1403114012L1404210011L1113207112L0206206052L0603104031L1211110121L0512202141L0201203032L0105101042L0809209062L0609100121L0501204022L1110211082L0809112091L0000201001L1304114051L0102100001L1114113141L0401101012L1007109132L0714204131L1005110031L0611103112L0112102131L0208102061L0708206092L0007100101L1409214112L1300211002L0501106001L1114212142L0511104111L0704107031L0702208022
+X23Y12Z6L0303122021L1102219103L0503504065L0302105101L0200305093L0907100081L1309100071L0706221102L0500212014L0301605026L0104216063L0204408034L0910502106L1805113052L1406116041L0409310114L2106122103L1710201033L0510412024L1411222072L1503421106L1310519035L1306220044L0101201112L1701221014L0802503105L0603107091L0407113012L0000513106L0201405045L2104320086L0202606086L1804120091L0609411104L1607522005L0000101102L2002320095L0610110111L0709500116L1603422006L0203109041L2201113011L0808611016L1807519006L0611316083L0910318074L1608415035L1001602076L1203603106
+X08Y04Z8L0000107018L0100103014L0000806018L0500406014L0500701017L0001205017L0400506006L0701107014L0201202014L0201603016L0002107038L0102103034L0002806038L0502406034L0502701037L0003205037L0402506026L0703107034L0203202034L0203603036
+X36Y19Z4L0101113011L0702107151L0804112071L0803108051L0802108071L1202108091L1503106151L1501106161L0204104041L1500101041L1612109161L0216104161L1114117161L1616114171L0503105161L1216117171L0203121091L0403103141L2606132061L2706131061L2907124111L2212128121L2112129121L3103122051L2503130041L2304128051L2213131151L2813123141L3014125151L2707126111L2608128111L2408129101L2309131101L0000205052L0101204042L0202203032L0007205122L0108204112L0209203102L0115204182L2301323143L0216203172L0700219122L0801218112L0902217102L1003216092L1104215082L1205214072L2100235002L2201235012L2302235022L2403235032L2504235042L2605235052L2706235062L2807235072L2908235082L3009235092L3110235102L3211235112L3312235122L3413235142L1302402134L0709413154L0000308033L0012308153L1300335153L1301334153L0215410154L1505415134L1615426154
+X72Y72Z8L0000109098L0000809091L0000401004L0001401014L0002401024L0003401034L0004401044L0005401054L0006401064L0007401074L0008401084L0009401094L0202403024L0203403034L0204403044L0205403054L0206403064L0208403084L0209403094L0200402014L0300404004L0307404074L0401405014L0402405024L0403405034L0404405044L0405405054L0406405064L0408405084L0409405094L0604406054L0704407054L0804408054L0904409054L0608406094L0708407094L0808408094L0908409094L0507406074L0500406004L0601407014L0602406034L0700408004L0703408034L0706408064L0707408074L0801408024L0900409014L0902409034L0906409074L0009109008L0900100098
+X10Y10Z2L0802106042L0001208031L0701209021L0206209011L0004100022L0000206071L0201102022L0105101072L0809106081L0805209091L0407207051L0208101061L0108200091L0303202012L0702205042L0008200032L0703207011L0601205022L0506204062L0904209052L0404104031L0203102021
+X60Y36Z8L1702113248L1503212078L1304112137L1105311206L1309202336L1508310125L1707105075L2306307228L1804417226L1514210145L1824104328L0421106315L0319308307L0728200297L0523306266L0427322325L0228305186L0131309237L0706108136L0604201114L0502114124L0303404128L0405208156L1428114338L1229116328L1530415237L1616316257L1426311225L0310305095L0213106115L1417207175L0921312184L2400420057L2500121028L2600325026L1934213316L2219422338L2119222348L2019326255L3233335335L3331436337L3332437336L2601232035L2101124046L2206321176L2604224067L2435137357L3708324344L2433238354L2103221068L3803133018L3517237327L3617335226L3717236306L3918339358L3126322287L2229127315L2230126306L2603134037L3503259165L3603437055L3411429198L3412330204L3413337125L2607324085L2309224157L2316124097L2907436085L3325432296L2317423197L2528430268L2805131094L3307235084L3713334204L3524235288L2318124218L3009227126L3711332228L2614227227L2609326125L4006144215L5917244205L5406244196L3906245197L4905445208L5420344264L4016154194L5519250344L5520349345L5521254275L4609348155L4816356326L5115344045L5504351165L4625344305L5113346265L4925253257L5309150256L5308253246L4506250057L4608149128L5530243326
+X15Y15Z4L0401105001L0601114013L0213213023L0105105051L0014102131L0704210074L1208211133L0812110081L0612306141L1201213003L0408300142L0911114064L0411300131L0007208004L0913409121L1210307101L0502401072L0108400032L0608105074L0103301021L0814308112L0510201083L0800106001L1414310134L1209313103L0604405023L0714206144L1109412083L0409205083L1207113051L1213314123L0514206143L1207212053L0804307013L0208302064L0302300054L1009413134L0412103111L0408203074L0810309093L0313302122L1410114071L0812209132L0902408034L0604208041L0203202021L1313113092L0709406104L0510302084L0709108081L1201412034L1307214104L0611206092L1100309044L0412203132L0301304003L1002409034L1411213101L0411402114L0101301011L0907209052L0900111001L0809308102L0101401044L1404314044L0310203092L0504305041L0111301112L0205202042L0612205122L0505406054L0314102141L0011400104L1210411104L1201113011L0305104051L0401405014L1002309023L0609405094L1108112081L0900310003
+X20Y35Z8L1916104218L1917204208L1406104196L1934305197L0905205206L1420404266L0016414195L1519410346L1520309348L1521414277L0609108158L0816316327L1115204046L1504411165L0625404306L1113406266L0925113258L1309210257L1308213248L0506410056L0608409126L1530403325L0017400346
+X36Y24Z1L0003102031L0302105021L0101104041L0005104011L0603108051L0605107011L0801110011L0802110041L0009102091L0308105081L0107104101L0011104071L0608108061L0606107101L0810110101L0809110071L1203114031L1502117021L1301116041L1205116011L1803120051L1805119011L2001122011L2002122041L1209114091L1508117081L1307116101L1211116071L1808120061L1806119101L2010122101L2009122071L2403126031L2702129021L2501128041L2405128011L3003132051L3005131011L3201134011L3202134041L2409126091L2708129081L2507128101L2411128071L3008132061L3006131101L3210134101L3209134071L0015102151L0314105141L0113104161L0017104131L0615108171L0617107131L0813110131L0814110161L0021102211L0320105201L0119104221L0023104191L0620108181L0618107221L0822110221L0821110191L1215114151L1514117141L1313116161L1217116131L1815120171L1817119131L2013122131L2014122161L1221114211L1520117201L1319116221L1223116191L1820120181L1818119221L2022122221L2021122191L2415126151L2714129141L2513128161L2417128131L3015132171L3017131131L3213134131L3214134161L2421126211L2720129201L2519128221L2423128191L3020132181L3018131221L3222134221L3221134191
+X72Y72Z5L0000171715L0001170715L0002169715L0003168715L0004167715L0005166715L0006165715L0007164715L0008163715L0009162715L0010161715L0011160715L0012159715L0013158715L0014157715L0015156715L0016155715L0017154715L0018153715L0019152715L0020151715L0021150715L0022149715L0023148715L0024147715L0025146715L0026145715L0027144715L0028143715L0029142715L0030141715L0031140715L0032139715L0033138715L0034137715L0035136715L0037135715L0038134715L0039133715L0040132715L0041131715L0042130715L0043129715L0044128715L0045127715L0046126715L0047125715L0048124715L0049123715L0050122715L0051121715L0052120715L0053119715L0054118715L0055117715L0056116715L0057115715L0058114715L0059113715L0060112715L0061111715L0062110715L0063109715L0064108715L0065107715L0066106715L0067105715L0068104715L0069103715L0070102715L0071101715L3600136004L0036535365
+X72Y72Z2L0000271712L0071271002
+X40Y40Z3L0313329331L1415127043L0237337351L0039335171L3816115013L0016121091L0206138381L1119118151L3703139001L0317137381L1000139393L0932139392L3611108333L3401100383L0125104033L1911124211L1727119261L3117132101L0015106341L1201116051L0025325061L0539333181L0508330061L3200326331L0700234041L0804109001L1614130331L0516122331L2007124221L1218128301L1804100392L1301133383L2125130073L1509105093L1118138393L2705137361L1429127341L3013138361L3007136121L3118137141L2100225033L0204205022L1412338392L0738339162L0028236043L1501236022L2811221232L1408209192L0622205052L2634237192L0633228073L3613212323L2101234042L3438219373L0802216032L2710219363L0038209372L0405207242L1124225112L1217217092L1732236343L1239214193L3008237113L0401303312L1316333152L1004217032L2628231272L1125224242L1227230172L0137210372L0504206062L0611326102L1932234372L0226207063L1512331202L3227236302L0509205162L0233207282L2124229112L1231219382L0314305222L2339334172L3226335352L2934336142L3026231133L2633236332L3502239083L0032301033L2434333393L0507310043L3617336333L1601333003L0907307333L3330336353L2023323233L1305324123L3501339073L0737311303L2239329073L0239304353L3731332303L1106324053L2705332163L0238306243L2029318283L1010310273L1521326153L1207320123L2206322123L0736311293L1334318253L1738319273L0315303173L0419304213L2120324213L2222327233L2319324233L0632307343L3019331273L3418335243L3409337103L3505336133L3605336073
+X15Y15Z3L1212303012L0506203113L0705209113L1102212113L1005110033L0414200012L0701302001L0107200083L0612305143L1102112001L0702109051L1105214022L0512110042L1309113071L0507206063L1212114121L0612213121L0303306033L1110112081L0312202142L1013214123L0710108071L0806302012L1108214062L0701203023L0900303021L1307313103L1114111121L0004100081L0011101101L0614104141L0914310133L0507106061L1101113011L0914108131L1010110071L0513303101L1204110011L0305304063L0809206082L1309214082L1301311002L0500107011L0901208002L1209311083L0506105031L0210202113L1106310053L0102301003L0802308043L0311203121L1111311123L0205301053L0313303143L0909309103L1013110141L1014311143
+X72Y72Z8L0000171023L0000271022L0000371021L0001171013L0001371011L0002171003L0002271002L0002371001
+X03Y03Z3L0000102002L0101101002L0200101012L0001101023L0001201013L0102102013
+X72Y72Z1L0100161061L2300164131L5500142501L0062106031L1771171341L2271166661L5967146631L2565161681L2665167661L2467159701L2369169691L5668157661L5569157671L0200159181L0116125331L4701170011L0209139261L6117103351L1628148341L0428103091L2400150061L1860119691L0114152461L2107156021L2158170361L0117112321L1213168041L0342114681L1643151591L5544161161L1115134161L1116134151L4342124521L0238146371L1449120631L0259113681L2243138471L0642146381L0404151031L5616159471L1216135161L1137126331L3911141261L0214159331L0269111321L6315168051L1741155561L0540109331L2322134211L4353129461L0713160351L1362118691L2244127471L0934108431L1120126191L1410140261L1957168571L5808146391L6653169311L0765166521L2719129191L3044125471L0425133311L1352110631L0405163111L0858110571L2645143541L5809165141L0515132261L2649141431L1252109611L0604141061L1955143411L1704153121L1448119541L2405145181L2447142511L1058113461L4605146211L1639122391L4613151111L4710146221L4414144181L0516105251L6822168331
+X40Y40Z3L0000139001L0001139011L0002139021L0003139031L0004139041L0005139051L0006139061L0007139071L0008139081L0009139091L0010139101L0011139111L0012139121L0013139131L0014139141L0015139151L0016139161L0017139171L0018139181L0019139191L0020139201L0021139211L0022139221L0023139231L0024139241L0025139251L0026139261L0027139271L0028139281L0029139291L0030139301L0031139311L0032139321L0033139331L0034139341L0035139351L0036139361L0037139371L0038139381L0039139391L0100101391L0500105391L0900109391L1300113391L1700117391L2100121391L2500125391L2900129391L3300133391L3700137391L0100201392L0300203392L0500205392L0700207392L0900209392L1100211392L1300213392L1500215392L1700217392L1900219392L2100221392L2300223392L2500225392L2700227392L2900229392L3100231392L3300233392L3500235392L3700237392L3900239392L0300303393L0700307393L1100311393L1500315393L1900319393L2300323393L2700327393L3100331393L3500335393L3900339393

hls/lines256_length128/Makefile.cygwin

+TARGET = sim
+OBJS = $(CPPS:.cpp=.o)
+CPPS = $(wildcard *.cpp)
+CXX = g++
+CXXFLAGS = -O3 -Wall -Wno-unknown-pragmas -Wno-unused-label -DSOFTWARE -DCALCTIME
+
+all: $(TARGET)
+
+$(TARGET): $(OBJS)
+	$(CXX) -O3 -Wl,--stack,16777216 -o $@ $(OBJS)
+
+clean:
+	rm *.o
+	rm $(TARGET)

hls/lines256_length128/bitstream/router_design.tcl

+
+################################################################
+# This is a generated script based on design: router_design
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2018.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source router_design_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z020clg400-1
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name router_design
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_gpio:2.0\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:hls:pynqrouter_256x128:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+  set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+  # Create ports
+  set LD [ create_bd_port -dir O -from 3 -to 0 LD ]
+
+  # Create instance: axi_gpio_0, and set properties
+  set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+  set_property -dict [ list \
+   CONFIG.C_GPIO_WIDTH {4} \
+ ] $axi_gpio_0
+
+  # Create instance: processing_system7_0, and set properties
+  set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+  set_property -dict [ list \
+   CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \
+   CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
+   CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \
+   CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+   CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
+   CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+   CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+   CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
+   CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \
+   CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+   CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \
+   CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \
+   CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
+   CONFIG.PCW_CAN0_CAN0_IO {<Select>} \
+   CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
+   CONFIG.PCW_CAN0_GRP_CLK_IO {<Select>} \
+   CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
+   CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
+   CONFIG.PCW_CAN1_CAN1_IO {<Select>} \
+   CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
+   CONFIG.PCW_CAN1_GRP_CLK_IO {<Select>} \
+   CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
+   CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
+   CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_CLK0_FREQ {100000000} \
+   CONFIG.PCW_CLK1_FREQ {10000000} \
+   CONFIG.PCW_CLK2_FREQ {10000000} \
+   CONFIG.PCW_CLK3_FREQ {10000000} \
+   CONFIG.PCW_CORE0_FIQ_INTR {0} \
+   CONFIG.PCW_CORE0_IRQ_INTR {0} \
+   CONFIG.PCW_CORE1_FIQ_INTR {0} \
+   CONFIG.PCW_CORE1_IRQ_INTR {0} \
+   CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
+   CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \
+   CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+   CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \
+   CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
+   CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \
+   CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \
+   CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
+   CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
+   CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+   CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+   CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_0 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_1 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_2 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_READPORT_3 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_1 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {<Select>} \
+   CONFIG.PCW_DDR_PRIORITY_WRITEPORT_3 {<Select>} \
+   CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
+   CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+   CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
+   CONFIG.PCW_DM_WIDTH {4} \
+   CONFIG.PCW_DQS_WIDTH {4} \
+   CONFIG.PCW_DQ_WIDTH {32} \
+   CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
+   CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+   CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+   CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+   CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
+   CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
+   CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET0_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET0_RESET_IO {MIO 9} \
+   CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
+   CONFIG.PCW_ENET1_ENET1_IO {<Select>} \
+   CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
+   CONFIG.PCW_ENET1_GRP_MDIO_IO {<Select>} \
+   CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
+   CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
+   CONFIG.PCW_ENET1_RESET_ENABLE {0} \
+   CONFIG.PCW_ENET1_RESET_IO {<Select>} \
+   CONFIG.PCW_ENET_RESET_ENABLE {1} \
+   CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_EN_4K_TIMER {0} \
+   CONFIG.PCW_EN_CAN0 {0} \
+   CONFIG.PCW_EN_CAN1 {0} \
+   CONFIG.PCW_EN_CLK0_PORT {1} \
+   CONFIG.PCW_EN_CLK1_PORT {0} \
+   CONFIG.PCW_EN_CLK2_PORT {0} \
+   CONFIG.PCW_EN_CLK3_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
+   CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
+   CONFIG.PCW_EN_DDR {1} \
+   CONFIG.PCW_EN_EMIO_CAN0 {0} \
+   CONFIG.PCW_EN_EMIO_CAN1 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_ENET0 {0} \
+   CONFIG.PCW_EN_EMIO_ENET1 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {0} \
+   CONFIG.PCW_EN_EMIO_I2C0 {0} \
+   CONFIG.PCW_EN_EMIO_I2C1 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_PJTAG {0} \
+   CONFIG.PCW_EN_EMIO_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+   CONFIG.PCW_EN_EMIO_SPI0 {0} \
+   CONFIG.PCW_EN_EMIO_SPI1 {0} \
+   CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
+   CONFIG.PCW_EN_EMIO_TRACE {0} \
+   CONFIG.PCW_EN_EMIO_TTC0 {0} \
+   CONFIG.PCW_EN_EMIO_TTC1 {0} \
+   CONFIG.PCW_EN_EMIO_UART0 {0} \
+   CONFIG.PCW_EN_EMIO_UART1 {0} \
+   CONFIG.PCW_EN_EMIO_WDT {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
+   CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+   CONFIG.PCW_EN_ENET0 {1} \
+   CONFIG.PCW_EN_ENET1 {0} \
+   CONFIG.PCW_EN_GPIO {1} \
+   CONFIG.PCW_EN_I2C0 {0} \
+   CONFIG.PCW_EN_I2C1 {0} \
+   CONFIG.PCW_EN_MODEM_UART0 {0} \
+   CONFIG.PCW_EN_MODEM_UART1 {0} \
+   CONFIG.PCW_EN_PJTAG {0} \
+   CONFIG.PCW_EN_PTP_ENET0 {0} \
+   CONFIG.PCW_EN_PTP_ENET1 {0} \
+   CONFIG.PCW_EN_QSPI {1} \
+   CONFIG.PCW_EN_RST0_PORT {1} \
+   CONFIG.PCW_EN_RST1_PORT {0} \
+   CONFIG.PCW_EN_RST2_PORT {0} \
+   CONFIG.PCW_EN_RST3_PORT {0} \
+   CONFIG.PCW_EN_SDIO0 {1} \
+   CONFIG.PCW_EN_SDIO1 {0} \
+   CONFIG.PCW_EN_SMC {0} \
+   CONFIG.PCW_EN_SPI0 {0} \
+   CONFIG.PCW_EN_SPI1 {0} \
+   CONFIG.PCW_EN_TRACE {0} \
+   CONFIG.PCW_EN_TTC0 {0} \
+   CONFIG.PCW_EN_TTC1 {0} \
+   CONFIG.PCW_EN_UART0 {1} \
+   CONFIG.PCW_EN_UART1 {0} \
+   CONFIG.PCW_EN_USB0 {1} \
+   CONFIG.PCW_EN_USB1 {0} \
+   CONFIG.PCW_EN_WDT {0} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+   CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+   CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
+   CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
+   CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+   CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+   CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+   CONFIG.PCW_FTM_CTI_IN0 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN1 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN2 {<Select>} \
+   CONFIG.PCW_FTM_CTI_IN3 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT0 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT1 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT2 {<Select>} \
+   CONFIG.PCW_FTM_CTI_OUT3 {<Select>} \
+   CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_IO {<Select>} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
+   CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
+   CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+   CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
+   CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C0_GRP_INT_IO {<Select>} \
+   CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
+   CONFIG.PCW_I2C0_I2C0_IO {<Select>} \
+   CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C0_RESET_IO {<Select>} \
+   CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
+   CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
+   CONFIG.PCW_I2C1_GRP_INT_IO {<Select>} \
+   CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
+   CONFIG.PCW_I2C1_I2C1_IO {<Select>} \
+   CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_I2C1_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C1_RESET_IO {<Select>} \
+   CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+   CONFIG.PCW_I2C_RESET_ENABLE {1} \
+   CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_I2C_RESET_SELECT {<Select>} \
+   CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
+   CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
+   CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
+   CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \
+   CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
+   CONFIG.PCW_IRQ_F2P_INTR {0} \
+   CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
+   CONFIG.PCW_MIO_0_DIRECTION {inout} \
+   CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_0_PULLUP {enabled} \
+   CONFIG.PCW_MIO_0_SLEW {slow} \
+   CONFIG.PCW_MIO_10_DIRECTION {inout} \
+   CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_10_PULLUP {enabled} \
+   CONFIG.PCW_MIO_10_SLEW {slow} \
+   CONFIG.PCW_MIO_11_DIRECTION {inout} \
+   CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_11_PULLUP {enabled} \
+   CONFIG.PCW_MIO_11_SLEW {slow} \
+   CONFIG.PCW_MIO_12_DIRECTION {inout} \
+   CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_12_PULLUP {enabled} \
+   CONFIG.PCW_MIO_12_SLEW {slow} \
+   CONFIG.PCW_MIO_13_DIRECTION {inout} \
+   CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_13_PULLUP {enabled} \
+   CONFIG.PCW_MIO_13_SLEW {slow} \
+   CONFIG.PCW_MIO_14_DIRECTION {in} \
+   CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_14_PULLUP {enabled} \
+   CONFIG.PCW_MIO_14_SLEW {slow} \
+   CONFIG.PCW_MIO_15_DIRECTION {out} \
+   CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_15_PULLUP {enabled} \
+   CONFIG.PCW_MIO_15_SLEW {slow} \
+   CONFIG.PCW_MIO_16_DIRECTION {out} \
+   CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_16_PULLUP {enabled} \
+   CONFIG.PCW_MIO_16_SLEW {slow} \
+   CONFIG.PCW_MIO_17_DIRECTION {out} \
+   CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_17_PULLUP {enabled} \
+   CONFIG.PCW_MIO_17_SLEW {slow} \
+   CONFIG.PCW_MIO_18_DIRECTION {out} \
+   CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_18_PULLUP {enabled} \
+   CONFIG.PCW_MIO_18_SLEW {slow} \
+   CONFIG.PCW_MIO_19_DIRECTION {out} \
+   CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_19_PULLUP {enabled} \
+   CONFIG.PCW_MIO_19_SLEW {slow} \
+   CONFIG.PCW_MIO_1_DIRECTION {out} \
+   CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_1_PULLUP {enabled} \
+   CONFIG.PCW_MIO_1_SLEW {slow} \
+   CONFIG.PCW_MIO_20_DIRECTION {out} \
+   CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_20_PULLUP {enabled} \
+   CONFIG.PCW_MIO_20_SLEW {slow} \
+   CONFIG.PCW_MIO_21_DIRECTION {out} \
+   CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_21_PULLUP {enabled} \
+   CONFIG.PCW_MIO_21_SLEW {slow} \
+   CONFIG.PCW_MIO_22_DIRECTION {in} \
+   CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_22_PULLUP {enabled} \
+   CONFIG.PCW_MIO_22_SLEW {slow} \
+   CONFIG.PCW_MIO_23_DIRECTION {in} \
+   CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_23_PULLUP {enabled} \
+   CONFIG.PCW_MIO_23_SLEW {slow} \
+   CONFIG.PCW_MIO_24_DIRECTION {in} \
+   CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_24_PULLUP {enabled} \
+   CONFIG.PCW_MIO_24_SLEW {slow} \
+   CONFIG.PCW_MIO_25_DIRECTION {in} \
+   CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_25_PULLUP {enabled} \
+   CONFIG.PCW_MIO_25_SLEW {slow} \
+   CONFIG.PCW_MIO_26_DIRECTION {in} \
+   CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_26_PULLUP {enabled} \
+   CONFIG.PCW_MIO_26_SLEW {slow} \
+   CONFIG.PCW_MIO_27_DIRECTION {in} \
+   CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_27_PULLUP {enabled} \
+   CONFIG.PCW_MIO_27_SLEW {slow} \
+   CONFIG.PCW_MIO_28_DIRECTION {inout} \
+   CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_28_PULLUP {enabled} \
+   CONFIG.PCW_MIO_28_SLEW {slow} \
+   CONFIG.PCW_MIO_29_DIRECTION {in} \
+   CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_29_PULLUP {enabled} \
+   CONFIG.PCW_MIO_29_SLEW {slow} \
+   CONFIG.PCW_MIO_2_DIRECTION {inout} \
+   CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_2_PULLUP {disabled} \
+   CONFIG.PCW_MIO_2_SLEW {slow} \
+   CONFIG.PCW_MIO_30_DIRECTION {out} \
+   CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_30_PULLUP {enabled} \
+   CONFIG.PCW_MIO_30_SLEW {slow} \
+   CONFIG.PCW_MIO_31_DIRECTION {in} \
+   CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_31_PULLUP {enabled} \
+   CONFIG.PCW_MIO_31_SLEW {slow} \
+   CONFIG.PCW_MIO_32_DIRECTION {inout} \
+   CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_32_PULLUP {enabled} \
+   CONFIG.PCW_MIO_32_SLEW {slow} \
+   CONFIG.PCW_MIO_33_DIRECTION {inout} \
+   CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_33_PULLUP {enabled} \
+   CONFIG.PCW_MIO_33_SLEW {slow} \
+   CONFIG.PCW_MIO_34_DIRECTION {inout} \
+   CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_34_PULLUP {enabled} \
+   CONFIG.PCW_MIO_34_SLEW {slow} \
+   CONFIG.PCW_MIO_35_DIRECTION {inout} \
+   CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_35_PULLUP {enabled} \
+   CONFIG.PCW_MIO_35_SLEW {slow} \
+   CONFIG.PCW_MIO_36_DIRECTION {in} \
+   CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_36_PULLUP {enabled} \
+   CONFIG.PCW_MIO_36_SLEW {slow} \
+   CONFIG.PCW_MIO_37_DIRECTION {inout} \
+   CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_37_PULLUP {enabled} \
+   CONFIG.PCW_MIO_37_SLEW {slow} \
+   CONFIG.PCW_MIO_38_DIRECTION {inout} \
+   CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_38_PULLUP {enabled} \
+   CONFIG.PCW_MIO_38_SLEW {slow} \
+   CONFIG.PCW_MIO_39_DIRECTION {inout} \
+   CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_39_PULLUP {enabled} \
+   CONFIG.PCW_MIO_39_SLEW {slow} \
+   CONFIG.PCW_MIO_3_DIRECTION {inout} \
+   CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_3_PULLUP {disabled} \
+   CONFIG.PCW_MIO_3_SLEW {slow} \
+   CONFIG.PCW_MIO_40_DIRECTION {inout} \
+   CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_40_PULLUP {enabled} \
+   CONFIG.PCW_MIO_40_SLEW {slow} \
+   CONFIG.PCW_MIO_41_DIRECTION {inout} \
+   CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_41_PULLUP {enabled} \
+   CONFIG.PCW_MIO_41_SLEW {slow} \
+   CONFIG.PCW_MIO_42_DIRECTION {inout} \
+   CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_42_PULLUP {enabled} \
+   CONFIG.PCW_MIO_42_SLEW {slow} \
+   CONFIG.PCW_MIO_43_DIRECTION {inout} \
+   CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_43_PULLUP {enabled} \
+   CONFIG.PCW_MIO_43_SLEW {slow} \
+   CONFIG.PCW_MIO_44_DIRECTION {inout} \
+   CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_44_PULLUP {enabled} \
+   CONFIG.PCW_MIO_44_SLEW {slow} \
+   CONFIG.PCW_MIO_45_DIRECTION {inout} \
+   CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_45_PULLUP {enabled} \
+   CONFIG.PCW_MIO_45_SLEW {slow} \
+   CONFIG.PCW_MIO_46_DIRECTION {out} \
+   CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_46_PULLUP {enabled} \
+   CONFIG.PCW_MIO_46_SLEW {slow} \
+   CONFIG.PCW_MIO_47_DIRECTION {in} \
+   CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_47_PULLUP {enabled} \
+   CONFIG.PCW_MIO_47_SLEW {slow} \
+   CONFIG.PCW_MIO_48_DIRECTION {inout} \
+   CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_48_PULLUP {enabled} \
+   CONFIG.PCW_MIO_48_SLEW {slow} \
+   CONFIG.PCW_MIO_49_DIRECTION {inout} \
+   CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_49_PULLUP {enabled} \
+   CONFIG.PCW_MIO_49_SLEW {slow} \
+   CONFIG.PCW_MIO_4_DIRECTION {inout} \
+   CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_4_PULLUP {disabled} \
+   CONFIG.PCW_MIO_4_SLEW {slow} \
+   CONFIG.PCW_MIO_50_DIRECTION {inout} \
+   CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_50_PULLUP {enabled} \
+   CONFIG.PCW_MIO_50_SLEW {slow} \
+   CONFIG.PCW_MIO_51_DIRECTION {inout} \
+   CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_51_PULLUP {enabled} \
+   CONFIG.PCW_MIO_51_SLEW {slow} \
+   CONFIG.PCW_MIO_52_DIRECTION {out} \
+   CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_52_PULLUP {enabled} \
+   CONFIG.PCW_MIO_52_SLEW {slow} \
+   CONFIG.PCW_MIO_53_DIRECTION {inout} \
+   CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+   CONFIG.PCW_MIO_53_PULLUP {enabled} \
+   CONFIG.PCW_MIO_53_SLEW {slow} \
+   CONFIG.PCW_MIO_5_DIRECTION {inout} \
+   CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_5_PULLUP {disabled} \
+   CONFIG.PCW_MIO_5_SLEW {slow} \
+   CONFIG.PCW_MIO_6_DIRECTION {out} \
+   CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_6_PULLUP {disabled} \
+   CONFIG.PCW_MIO_6_SLEW {slow} \
+   CONFIG.PCW_MIO_7_DIRECTION {out} \
+   CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_7_PULLUP {disabled} \
+   CONFIG.PCW_MIO_7_SLEW {slow} \
+   CONFIG.PCW_MIO_8_DIRECTION {out} \
+   CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_8_PULLUP {disabled} \
+   CONFIG.PCW_MIO_8_SLEW {slow} \
+   CONFIG.PCW_MIO_9_DIRECTION {out} \
+   CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+   CONFIG.PCW_MIO_9_PULLUP {enabled} \
+   CONFIG.PCW_MIO_9_SLEW {slow} \
+   CONFIG.PCW_MIO_PRIMITIVE {54} \
+   CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \
+   CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \
+   CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
+   CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
+   CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
+   CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
+   CONFIG.PCW_NAND_CYCLES_T_AR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_REA {1} \
+   CONFIG.PCW_NAND_CYCLES_T_RR {1} \
+   CONFIG.PCW_NAND_CYCLES_T_WC {11} \
+   CONFIG.PCW_NAND_CYCLES_T_WP {1} \
+   CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
+   CONFIG.PCW_NAND_GRP_D8_IO {<Select>} \
+   CONFIG.PCW_NAND_NAND_IO {<Select>} \
+   CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_CS1_WE_TIME {0} \
+   CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_A25_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS0_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_CS1_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {<Select>} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
+   CONFIG.PCW_NOR_GRP_SRAM_INT_IO {<Select>} \
+   CONFIG.PCW_NOR_NOR_IO {<Select>} \
+   CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
+   CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
+   CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
+   CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
+   CONFIG.PCW_P2F_CAN0_INTR {0} \
+   CONFIG.PCW_P2F_CAN1_INTR {0} \
+   CONFIG.PCW_P2F_CTI_INTR {0} \
+   CONFIG.PCW_P2F_DMAC0_INTR {0} \
+   CONFIG.PCW_P2F_DMAC1_INTR {0} \
+   CONFIG.PCW_P2F_DMAC2_INTR {0} \
+   CONFIG.PCW_P2F_DMAC3_INTR {0} \
+   CONFIG.PCW_P2F_DMAC4_INTR {0} \
+   CONFIG.PCW_P2F_DMAC5_INTR {0} \
+   CONFIG.PCW_P2F_DMAC6_INTR {0} \
+   CONFIG.PCW_P2F_DMAC7_INTR {0} \
+   CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
+   CONFIG.PCW_P2F_ENET0_INTR {0} \
+   CONFIG.PCW_P2F_ENET1_INTR {0} \
+   CONFIG.PCW_P2F_GPIO_INTR {0} \
+   CONFIG.PCW_P2F_I2C0_INTR {0} \
+   CONFIG.PCW_P2F_I2C1_INTR {0} \
+   CONFIG.PCW_P2F_QSPI_INTR {0} \
+   CONFIG.PCW_P2F_SDIO0_INTR {0} \
+   CONFIG.PCW_P2F_SDIO1_INTR {0} \
+   CONFIG.PCW_P2F_SMC_INTR {0} \
+   CONFIG.PCW_P2F_SPI0_INTR {0} \
+   CONFIG.PCW_P2F_SPI1_INTR {0} \
+   CONFIG.PCW_P2F_UART0_INTR {0} \
+   CONFIG.PCW_P2F_UART1_INTR {0} \
+   CONFIG.PCW_P2F_USB0_INTR {0} \
+   CONFIG.PCW_P2F_USB1_INTR {0} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \
+   CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+   CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
+   CONFIG.PCW_PACKAGE_NAME {clg400} \
+   CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
+   CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_PJTAG_PJTAG_IO {<Select>} \
+   CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
+   CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+   CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+   CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
+   CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_IO1_IO {<Select>} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+   CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+   CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_QSPI_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
+   CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+   CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+   CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+   CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
+   CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_POW_IO {<Select>} \
+   CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD0_GRP_WP_IO {<Select>} \
+   CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+   CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_CD_IO {<Select>} \
+   CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_POW_IO {<Select>} \
+   CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+   CONFIG.PCW_SD1_GRP_WP_IO {<Select>} \
+   CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SD1_SD1_IO {<Select>} \
+   CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
+   CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
+   CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
+   CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
+   CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \
+   CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+   CONFIG.PCW_SMC_CYCLE_T0 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T1 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T2 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T3 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T4 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T5 {NA} \
+   CONFIG.PCW_SMC_CYCLE_T6 {NA} \
+   CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
+   CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS0_IO {<Select>} \
+   CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI0_GRP_SS2_IO {<Select>} \
+   CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
+   CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI0_SPI0_IO {<Select>} \
+   CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
+   CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS0_IO {<Select>} \
+   CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS1_IO {<Select>} \
+   CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
+   CONFIG.PCW_SPI1_GRP_SS2_IO {<Select>} \
+   CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
+   CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_SPI1_SPI1_IO {<Select>} \
+   CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+   CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
+   CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
+   CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
+   CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
+   CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
+   CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
+   CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
+   CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
+   CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
+   CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
+   CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_16BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_2BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_32BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_4BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
+   CONFIG.PCW_TRACE_GRP_8BIT_IO {<Select>} \
+   CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
+   CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
+   CONFIG.PCW_TRACE_TRACE_IO {<Select>} \
+   CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
+   CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TTC0_TTC0_IO {<Select>} \
+   CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
+   CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_TTC1_TTC1_IO {<Select>} \
+   CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
+   CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
+   CONFIG.PCW_UART0_BAUD_RATE {115200} \
+   CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART0_GRP_FULL_IO {<Select>} \
+   CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
+   CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
+   CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
+   CONFIG.PCW_UART1_BAUD_RATE {115200} \
+   CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+   CONFIG.PCW_UART1_GRP_FULL_IO {<Select>} \
+   CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
+   CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_UART1_UART1_IO {<Select>} \
+   CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+   CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
+   CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+   CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \
+   CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
+   CONFIG.PCW_UIPARAM_DDR_AL {0} \
+   CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
+   CONFIG.PCW_UIPARAM_DDR_BL {8} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \
+   CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \
+   CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+   CONFIG.PCW_UIPARAM_DDR_CL {7} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
+   CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
+   CONFIG.PCW_UIPARAM_DDR_CWL {6} \
+   CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
+   CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \
+   CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
+   CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
+   CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+   CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
+   CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \
+   CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
+   CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \
+   CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
+   CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
+   CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+   CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
+   CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
+   CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
+   CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
+   CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+   CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
+   CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
+   CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
+   CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+   CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB0_RESET_ENABLE {1} \
+   CONFIG.PCW_USB0_RESET_IO {MIO 46} \
+   CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+   CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
+   CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
+   CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
+   CONFIG.PCW_USB1_RESET_ENABLE {0} \
+   CONFIG.PCW_USB1_RESET_IO {<Select>} \
+   CONFIG.PCW_USB1_USB1_IO {<Select>} \
+   CONFIG.PCW_USB_RESET_ENABLE {1} \
+   CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
+   CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+   CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
+   CONFIG.PCW_USE_AXI_NONSECURE {0} \
+   CONFIG.PCW_USE_CORESIGHT {0} \
+   CONFIG.PCW_USE_CROSS_TRIGGER {0} \
+   CONFIG.PCW_USE_CR_FABRIC {1} \
+   CONFIG.PCW_USE_DDR_BYPASS {0} \
+   CONFIG.PCW_USE_DEBUG {0} \
+   CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
+   CONFIG.PCW_USE_DMA0 {0} \
+   CONFIG.PCW_USE_DMA1 {0} \
+   CONFIG.PCW_USE_DMA2 {0} \
+   CONFIG.PCW_USE_DMA3 {0} \
+   CONFIG.PCW_USE_EXPANDED_IOP {0} \
+   CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
+   CONFIG.PCW_USE_HIGH_OCM {0} \
+   CONFIG.PCW_USE_M_AXI_GP0 {1} \
+   CONFIG.PCW_USE_M_AXI_GP1 {0} \
+   CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
+   CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
+   CONFIG.PCW_USE_S_AXI_ACP {0} \
+   CONFIG.PCW_USE_S_AXI_GP0 {0} \
+   CONFIG.PCW_USE_S_AXI_GP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {0} \
+   CONFIG.PCW_USE_S_AXI_HP1 {0} \
+   CONFIG.PCW_USE_S_AXI_HP2 {0} \
+   CONFIG.PCW_USE_S_AXI_HP3 {0} \
+   CONFIG.PCW_USE_TRACE {0} \
+   CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
+   CONFIG.PCW_VALUE_SILVERSION {3} \
+   CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
+   CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
+   CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
+   CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
+   CONFIG.PCW_WDT_WDT_IO {<Select>} \
+ ] $processing_system7_0
+
+  # Create instance: ps7_0_axi_periph, and set properties
+  set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps7_0_axi_periph
+
+  # Create instance: pynqrouter_256x128_0, and set properties
+  set pynqrouter_256x128_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:pynqrouter_256x128:1.0 pynqrouter_256x128_0 ]
+
+  # Create instance: rst_ps7_0_100M, and set properties
+  set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ]
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+  connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+  connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins pynqrouter_256x128_0/s_axi_AXI4LS]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+
+  # Create port connections
+  connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports LD] [get_bd_pins axi_gpio_0/gpio_io_o]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins pynqrouter_256x128_0/ap_clk] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk]
+  connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
+  connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn]
+  connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins pynqrouter_256x128_0/ap_rst_n] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
+  create_bd_addr_seg -range 0x00040000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs pynqrouter_256x128_0/s_axi_AXI4LS/Reg] SEG_pynqrouter_256x128_0_Reg
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lines256_length128/main.cpp

@@ -17,6 +17,7 @@
 
 #include "router.hpp"
 
+#define PRINT_SOLUTION
 
 int main(int argc, char *argv[]) {
     using namespace std;
@@ -50,9 +51,11 @@ int main(int argc, char *argv[]) {
         seed = atoi(argv[2]);
     }
 
+#ifdef PRINT_SOLUTION
     int size_x = (boardstr[1] - '0') * 10 + (boardstr[2] - '0');
     int size_y = (boardstr[4] - '0') * 10 + (boardstr[5] - '0');
     int size_z = (boardstr[7] - '0');
+#endif
 
     // ソルバ実行
     ap_int<32> status;
@@ -68,6 +71,7 @@ int main(int argc, char *argv[]) {
     cout << "status = " << (int)status << endl;
     cout << "elapsed = " << ((double)(clock_done - clock_start) / CLOCKS_PER_SEC) << endl << endl;
 
+#ifdef PRINT_SOLUTION
     // 解表示
     cout << "SOLUTION" << endl;
     cout << "========" << endl;
@@ -80,12 +84,13 @@ int main(int argc, char *argv[]) {
                     cout << ",";
                 }
                 int i = ((x * MAX_WIDTH + y) << BITWIDTH_Z) | z;
-                //cout << setfill('0') << setw(2) << right << (unsigned int)(unsigned char)(boardstr[i]);
-                cout << (unsigned int)(unsigned char)(boardstr[i]);
+                cout << setfill('0') << setw(3) << right << (unsigned int)(unsigned char)(boardstr[i]);
+                //cout << (unsigned int)(unsigned char)(boardstr[i]);
             }
             cout << endl;
         }
     }
+#endif
 
     return 0;
 }

hls/lines256_length128/router.cpp

@@ -210,7 +210,6 @@ bool pynqrouter_256x128(char boardstr[BOARDSTR_SIZE], ap_uint<32> seed, ap_int<3
     FIRST_ROUTING:
     for (ap_uint<9> i = 0; i < (ap_uint<9>)(line_num); i++) {
 #pragma HLS LOOP_TRIPCOUNT min=2 max=255 avg=50
-//#pragma HLS LOOP_TRIPCOUNT min=2 max=127 avg=50
 //#pragma HLS PIPELINE
 //#pragma HLS UNROLL factor=2
 
@@ -245,6 +244,7 @@ bool pynqrouter_256x128(char boardstr[BOARDSTR_SIZE], ap_uint<32> seed, ap_int<3
     ap_uint<8> last_target = 255;
 
     // [Step 2] Rip-up 再ルーティング
+	cout << "Rip-up Routing" << endl;
     ROUTING:
     for (ap_uint<16> round = 1; round <= 32768 /* = (2048 * 16) */; round++) {
 #pragma HLS LOOP_TRIPCOUNT min=1 max=4000 avg=50
@@ -285,8 +285,6 @@ bool pynqrouter_256x128(char boardstr[BOARDSTR_SIZE], ap_uint<32> seed, ap_int<3
 #pragma HLS LOOP_TRIPCOUNT min=1 max=255 avg=50
             weights[paths[target][j]] = 1;
         }
-        // 対象ラインのスタートの重みも一旦リセット あとで (*) で戻す
-        weights[starts[target]] = 1;
 
         // (2) 重みを更新
         ap_uint<8> current_round_weight = new_weight(round);
@@ -304,10 +302,18 @@ bool pynqrouter_256x128(char boardstr[BOARDSTR_SIZE], ap_uint<32> seed, ap_int<3
                 }
             }
         }
+		WEIGHT_TERMINAL:
+        for (ap_uint<9> i = 0; i < (ap_uint<9>)(line_num); i++) {
+#pragma HLS LOOP_TRIPCOUNT min=2 max=255 avg=50
+            weights[starts[i]] = MAX_WEIGHT;
+            weights[goals[i]] = MAX_WEIGHT;
+        }
+		// 対象ラインのスタートの重みも一旦リセット あとで (*) で戻す
+        weights[starts[target]] = 1;
 
         // 経路探索
 #ifdef DEBUG_PRINT
-        cout << "LINE #" << (int)(target + 1) << endl;
+        cout << "(round: " << round << ")" << "LINE #" << (int)(target + 1) << endl;
 #endif
         search(&(paths_size[target]), paths[target], starts[target], goals[target], weights);
 
@@ -612,18 +618,18 @@ void search(ap_uint<8> *path_size, ap_uint<16> path[MAX_PATH], ap_uint<16> start
     ap_uint<16> t = prev[goal];
 
 #ifdef DEBUG_PRINT
-    int dbg_start_xy = start >> BITWIDTH_Z;
-    int dbg_start_x = dbg_start_xy / MAX_WIDTH;
-    int dbg_start_y = dbg_start_xy % MAX_WIDTH;
-    int dbg_start_z = start & BITMASK_Z;
-
-    int dbg_goal_xy = goal >> BITWIDTH_Z;
-    int dbg_goal_x = dbg_goal_xy / MAX_WIDTH;
-    int dbg_goal_y = dbg_goal_xy % MAX_WIDTH;
-    int dbg_goal_z = goal & BITMASK_Z;
-
-    cout << "(" << dbg_start_x << ", " << dbg_start_y << ", " << dbg_start_z << ") #" << start << " -> "
-         << "(" << dbg_goal_x  << ", " << dbg_goal_y  << ", " << dbg_goal_z  << ") #" << goal << endl;
+    //int dbg_start_xy = start >> BITWIDTH_Z;
+    //int dbg_start_x = dbg_start_xy / MAX_WIDTH;
+    //int dbg_start_y = dbg_start_xy % MAX_WIDTH;
+    //int dbg_start_z = start & BITMASK_Z;
+
+    //int dbg_goal_xy = goal >> BITWIDTH_Z;
+    //int dbg_goal_x = dbg_goal_xy / MAX_WIDTH;
+    //int dbg_goal_y = dbg_goal_xy % MAX_WIDTH;
+    //int dbg_goal_z = goal & BITMASK_Z;
+
+    //cout << "(" << dbg_start_x << ", " << dbg_start_y << ", " << dbg_start_z << ") #" << start << " -> "
+    //     << "(" << dbg_goal_x  << ", " << dbg_goal_y  << ", " << dbg_goal_z  << ") #" << goal << endl;
 #endif
 
     // バックトラック
@@ -634,11 +640,11 @@ void search(ap_uint<8> *path_size, ap_uint<16> path[MAX_PATH], ap_uint<16> start
 #pragma HLS PIPELINE II=2
 
 #ifdef DEBUG_PRINT
-        int t_xy = prev[t] >> BITWIDTH_Z;
-        int t_x = t_xy / MAX_WIDTH;
-        int t_y = t_xy % MAX_WIDTH;
-        int t_z = prev[t] & BITMASK_Z;
-        cout << "  via " << "(" << t_x << ", " << t_y << ", " << t_z << ") #" << prev[t] << " dist=" << dist[t] << endl;
+        //int t_xy = prev[t] >> BITWIDTH_Z;
+        //int t_x = t_xy / MAX_WIDTH;
+        //int t_y = t_xy % MAX_WIDTH;
+        //int t_z = prev[t] & BITMASK_Z;
+        //cout << "  via " << "(" << t_x << ", " << t_y << ", " << t_z << ") #" << prev[t] << " dist=" << dist[t] << endl;
 #endif
 
         path[p] = t; // 記録
@@ -649,8 +655,8 @@ void search(ap_uint<8> *path_size, ap_uint<16> path[MAX_PATH], ap_uint<16> start
     *path_size = p;
 
 #ifdef DEBUG_PRINT
-    cout << "max_path_len = " << p << endl;
-    cout << "max_pq_len = " << max_pq_len << endl;
+    //cout << "max_path_len = " << p << endl;
+    //cout << "max_pq_len = " << max_pq_len << endl;
 #endif
 
 }
@@ -676,6 +682,7 @@ void pq_push(ap_uint<16> priority, ap_uint<16> data, ap_uint<13> *pq_len, ap_uin
 #pragma HLS INLINE
 
     (*pq_len)++;
+	if ((*pq_len) == 0) { (*pq_len)--; } // Queue is full -> Last element is automatically removed
     ap_uint<13> i = (*pq_len);      // target
     ap_uint<13> p = (*pq_len) >> 1; // i.e., (*pq_len) / 2; // 親
     PQ_PUSH_LOOP:
@@ -708,7 +715,7 @@ void pq_pop(ap_uint<16> *ret_priority, ap_uint<16> *ret_data, ap_uint<13> *pq_le
     ap_uint<16> last_priority = (ap_uint<16>)(pq_nodes[*pq_len] & PQ_PRIORITY_MASK); // 末尾ノードの優先度
 
     PQ_POP_LOOP:
-    while (1) {
+    while (!(i >> 11)) { // (2018.08.25) Loop condition fixed
 #pragma HLS LOOP_TRIPCOUNT min=1 max=8 avg=4
 //#pragma HLS PIPELINE
 //#pragma HLS UNROLL factor=2